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<P><B>5 Analysis of Design</B> <BR>
<B>5. 1 Problem</B><BR>
Here is a section of source code analysis. An example analysis was performed
using trace mode-2 in Veritak Simulator. (Off course, you can use
another tool).<BR>
</P>
<P>Load Veritak Project "altera_rtl_trace_count.vtakprj"<BR>
Let's look at the instruction "ori $sp,$sp,#$3380". Micro operation
is<BR>
</P>
<TABLE border="1">
<TBODY>
<TR>
<TH bgcolor="#97ffff">$sp | #$3380 => $sp</TH>
</TR>
</TBODY>
</TABLE>
<P>It is noted that Register File $sp has not been written yet even at Stage5.<BR>
What will be happened if $sp is referenced in any stage of stage2-stage5
? This is called RAW (Read After Write) Data Hazard. <BR>
<B>Forwarding mechanism </B>overcomes this problem.</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center" height="32">Time Slot</TH>
<TH valign="middle" align="center" height="32">Stage1</TH>
<TH valign="middle" align="center" height="32">Stage2</TH>
<TH valign="middle" align="center" height="32" width="240">Stage3</TH>
<TH valign="middle" align="center" height="32" width="46">Stage4</TH>
<TH valign="middle" align="center" width="185" height="32">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center" height="48"> </TD>
<TD valign="middle" align="center" height="48">Set Register File Address</TD>
<TD valign="middle" align="center" height="48">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center" height="48" width="240">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center" height="48" width="46">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center" width="185" height="48">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode<BR>
ori $sp,$sp,#$3380</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" width="240"></TD>
<TD valign="middle" align="center" width="46"></TD>
<TD valign="middle" align="center" width="185"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Fetch & Decode<BR>
sw $z0,0($a0)</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile<BR>
ALU_LEFT<=0<BR>
ALU_RIGHT<=#$3380</TD>
<TD valign="middle" align="center" width="240"></TD>
<TD valign="middle" align="center" width="46"></TD>
<TD valign="middle" align="center" width="185"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode<BR>
slt $v1,$a0,$a1</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00" width="240">ALU=LEFT(0) or RIGHT(#$3380);<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center" width="46"></TD>
<TD valign="middle" align="center" width="185"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#00cccc" width="240">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00" width="46">NReg<=AReg</TD>
<TD valign="middle" align="center" width="185"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc" width="240">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cccc" width="46">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00" width="185">WB<BR>
Register FieAddres=$sp<BR>
Write Data=#$3380<BR>
</TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" width="240"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc" width="46">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cccc" width="185">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" width="240"></TD>
<TD valign="middle" align="center" width="46"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc" width="185">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" width="240"></TD>
<TD valign="middle" align="center" width="46"></TD>
<TD valign="middle" align="center" width="185"></TD>
</TR>
</TBODY>
</TABLE>
<P><BR>
<BR>
<IMG src="yacc12.jpg" width="1280" height="1024" border="0"></P>
<P><BR>
<BR>
<B>5.2 "Forwarding" Analysis</B><BR>
<BR>
Let's look at tool-tip displays "sw $z0, 0($a0)"<BR>
This instruction causes RAM Write operation at the address of 0x928 followed
by 2 clocks. However, 0x928(=$a0) has been set by the instruction ori $a0,$a0,0x928
prior to 5cycles. So this is the <B>forwarding</B> case.<BR>
<BR>
Pipelined Registers carry 0x928 in <B>forwarding</B>.<BR>
Let' trace the situation back in following analysis.</P>
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<TR>
<TH align="left" bgcolor="#d7ffff">
<P>0: 3c1c0000 lui $gp,0x0 <BR>
4: 379c0000 ori $gp,$gp,0x88a0 <BR>
8: 3c040000 lui $a0,0x0 <I><BR>
<B><U><FONT color="#ff0000">c: 34840000 ori $a0,$a0,0x928</FONT></U></B></I> <BR>
10: 3c050000 lui $a1,0x0 <BR>
14: 34a50000 ori $a1,$a1,0x934 <BR>
18: 3c1d0000 lui $sp,0x0 <BR>
1c: 37bdfff0 ori $sp,$sp,0x3f80 <FONT color="#ff0000"><U><B><BR>
20: ac800000 sw $zero,0($a0)</B></U></FONT> <BR>
24: 0085182a slt $v1,$a0,$a1 <BR>
28: 1460fffd bnez $v1,0x20 <BR>
2c: 24840004 addiu $a0,$a0,4 <BR>
30: 0c00019d jal 0x674 </P>
</TH>
</TR>
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</TABLE>
<P><IMG src="yacc2.png" width="1280" height="1024" border="0"></P>
<P><BR>
To investigate what is driving the Daddress 0x928, Jump to tag file,<BR>
<IMG src="yacc_trace1.png" width="1199" height="934" border="0"><BR>
<BR>
Then jump to the tag file which describes entire structure of design by
text file.<BR>
<BR>
<IMG src="yacc_trace2.png" width="1210" height="967" border="0"><BR>
<BR>
Move to <FONT color="#ff00ff">SourceDriver</FONT> =><FONT color="#ff00ff">Assigned</FONT>:<BR>
Select the signal,and DBLCLICK<BR>
<IMG src="yacc_trace3.png" width="1210" height="967" border="0"><BR>
<BR>
Jumps to the source code where DAddress is assigned.<BR>
We realize that DAddress is result of ( not time consuming) add operation
between alu_source and IRD2 concerned.<BR>
<IMG src="yacc_trace4.png" width="1210" height="967" border="0"><BR>
<BR>
There is another way to jump to the driver.<BR>
You can jump to the source code by "Jump to Driver" directly.<BR>Set T1 cursor at write strobe time, select the signal ,and Jump to Driver..<BR>
<IMG src="yacc_trace5.png" width="1210" height="967" border="0"><BR>
<BR>
Same result as tag-jump.<BR>
<IMG src="yacc_trace6.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Since this assignment is combinational logic, you can view the value by
tool tip.<BR>
<IMG src="yacc_trace7.png" width="1210" height="967" border="0"><BR>
<BR>
Now, we realize that "alu_source" is 32'h928 which is next target
for further analysis.<BR>
<IMG src="yacc_trace8.png" width="1210" height="967" border="0"><BR>
<BR>
Add "alu_source " to WaveformView for further analysis.<BR>
<IMG src="yacc_trace9.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Jump to Driver for "alu_source"<BR>
<IMG src="yacc_trace10.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Warning Displayed.<BR>
<IMG src="yacc_trace11.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Expand the signal to bits.<BR>
<IMG src="yacc_trace12.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Then jump to driver by any signal activated.<BR>
<IMG src="yacc_trace13.png" width="1210" height="967" border="0"><BR>
<BR>
Then jumps to the position. This is combinational circuit which has no
time-consumption. We can tool-tip the value in this case.<BR>
<IMG src="yacc_trace14.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Add "alu_left_latch " to the WaveformView for further analysis.<BR>
<IMG src="yacc_trace15.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Jump to Driver..<BR>
<IMG src="yacc_trace16.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
Jumps to the position where "alu_left_latch" is assigned by non-blocking
statement<BR>
<IMG src="yacc_trace17.png" width="1210" height="967" border="0"><BR>
</P>
<P>Jump to Driver by "DReg" at T1 cursor.<BR>
<IMG src="yacc_trace18.png" width="1210" height="967" border="0"><BR>
</P>
<P>We realize "DReg " is just pipelined register</P>
<P><IMG src="yacc_trace19.png" width="1210" height="967" border="0"></P>
<P><BR>
Let's investigate what is driving "RReg".</P>
<P><IMG src="yacc_trace20.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
NReg is Driving.<BR>
<IMG src="yacc_trace21.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
What is driving "NReg" ?<BR>
<IMG src="yacc_trace22.png" width="1210" height="967" border="0"><BR>
<BR>
"AReg" is driving.<BR>
<IMG src="yacc_trace23.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
What is driving "AReg"?<BR>
<IMG src="yacc_trace24.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
"alu_out " is driving.<BR>
<IMG src="yacc_trace25.png" width="1210" height="967" border="0"><BR>
<BR>
Then investigate the driver of "alu_out".<BR>
<IMG src="yacc_trace27.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
We realize alu_out=a | b;<BR>
<IMG src="yacc_trace28.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
<BR>
Finally We understand "the value 0x928 is derived from the instruction
" ori $a0, $a0,#$928" through pipelined registers ,not from register
file's output<B></B>. You can see <A href="pipelined_reg.gif">block diagram</A> I wrote ,which is a sketch in early design stage.<BR>
<IMG src="yacc_trace29.png" width="1210" height="967" border="0"><BR>
<BR>
<BR>
<BR>
</P>
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