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<P><B>7 Examples of C compilation</B><BR>
FPGA Vendor's library is not attached since they are property of vendors.
Set them under \lib folder as below to run RTL/Delay simulation in Veritak.(XilinxCorelib
is not attached in free Web Edition. BaseX or higher edition will be necessary.)<BR>
<IMG src="folder_structure.png" width="847" height="334" border="0"><BR>
<BR>
<B>7.1 RTL</B><BR>
<BR>
In RTL simulation using UART is too slow for debugging the cpu. Therefore output is changed
to console instead of UART PORT. Please note RTL
simulation takes very long time in running actual 10msec .</P>
<TABLE border=1>
<TBODY>
<TR>
<TD width=176>Folder</TD>
<TD width=136>C Program</TD>
<TD>Description</TD>
<TD>Batch File</TD>
<TD>Veritak Project(\bench\verilog)</TD>
</TR>
<TR>
<TD width=176>\bench\c_src\count</TD>
<TD width=136>count_tak.c</TD>
<TD>By Steve Rhords</TD>
<TD>compile.bat</TD>
<TD>altera_rtl/xilinx_rtl</TD>
</TR>
<TR>
<TD width=176>\bench\c_src\pi</TD>
<TD width=136>pi2.c</TD>
<TD>pi 10digits</TD>
<TD>compile.bat</TD>
<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
</TR>
<TR>
<TD width=176>\bench\c_src\dhrystone</TD>
<TD width=136>dhry21_tak.c</TD>
<TD>Dhrystone</TD>
<TD>compile.bat</TD>
<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
</TR>
<TR>
<TD width=176>\bench\c_src\reed solomon</TD>
<TD width=136>rs_tak.c</TD>
<TD>By Phil Karn</TD>
<TD>compile.bat</TD>
<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
</TR>
<TR>
<TD width=176>\bench\c_src\calculator</TD>
<TD width=136>uart_echo_test.c</TD>
<TD>Interactive Calculator. Interrupt debug use</TD>
<TD>compile.bat</TD>
<TD>altera_calculator_test_using_uart_echo/xilinx_calculator_test_using_uart_echo<BR>
</TD>
</TR>
</TBODY>
</TABLE>
<P><BR>
(1) count </P>
<P><IMG src="count_rtl_sim.png" width="783" height="734" border="0"></P>
<P>(2)Pi<BR>
<IMG src="xilinx_pi_rtl_sim.png" width="877" height="295" border="0"><BR>
<BR>
(3)Reed Solomon<IMG src="rs_rtl_sim_by_cyclone.png" width="1007" height="719" border="0"></P>
<P><BR>
(4) Calculator<BR>
This is console output only, not interactive. Using echo-back technique,
UART interrupt test was done.<BR>
<IMG src="xilinx_calculator_rtl_sim.png" width="877" height="715" border="0"></P>
<P>RTL Simulation Procedure<BR>
</P>
<UL>
<LI>Compile C program using compile.bat
<LI>conver_mips.exe will generate memory initialization file for both Altera
and Xilinx,which will be sent to\rtl\xilinx and \rtl\altera.
<LI>Load Veritak Project=>Go
</UL>
<P><B>7.2 Gate Simulation</B><BR>
Using "count" above,Post-Layout Gate Simulation was performed.<BR>
</P>
<TABLE border=1>
<TBODY>
<TR>
<TD>Folder</TD>
<TD>Veritak Project File</TD>
<TD>Frequency</TD>
</TR>
<TR>
<TD>\syn\altra_stratix2\simulation\custom</TD>
<TD>Gate_altera</TD>
<TD>165MHz</TD>
</TR>
<TR>
<TD>\syn\altera\simulation\custom</TD>
<TD>Gate_altera</TD>
<TD>100MHz</TD>
</TR>
<TR>
<TD>\syn\xilinx</TD>
<TD>Gate_xilinx</TD>
<TD>25MHz</TD>
</TR>
</TBODY>
</TABLE>
<P><BR>
<BR>
<B>7.3 FPGA</B></P>
<TABLE border=1>
<TBODY>
<TR>
<TD>Folder</TD>
<TD>C Program</TD>
<TD>Batch File</TD>
<TD>Description</TD>
</TR>
<TR>
<TD>\syn\c_src\count</TD>
<TD>count_tak.c</TD>
<TD>compile.bat</TD>
<TD>By Steve Rhords</TD>
</TR>
<TR>
<TD>\syn\c_src\pi</TD>
<TD>pi2.c</TD>
<TD>compile.bat</TD>
<TD>pi 800 digits calculation</TD>
</TR>
<TR>
<TD>\syn\c_src\reed solomon</TD>
<TD>rs_tak.c</TD>
<TD>compile.bat</TD>
<TD>By Phil Karn</TD>
</TR>
<TR>
<TD>\syn\yacc\bench\c_src\calculator</TD>
<TD>uart_echo_test.c</TD>
<TD>compile.bat</TD>
<TD>Interactive Calculater</TD>
</TR>
</TBODY>
</TABLE>
<P><Synthesis Procedure><BR>
</P>
<UL>
<LI>Run Batch File
<LI>Synthesize top of hardware Regenerate RAM using core-generator, then Synthesize
top of hardware
</UL>
<P><BR>
<BR>
FPGA Confirmation<BR>
</P>
<TABLE border=1>
<TBODY>
<TR>
<TD>FPGA</TD>
<TD>FPGA BOARD</TD>
<TD>Device</TD>
<TD>Clock</TD>
<TD>CPU<BR>
CLOCK</TD>
<TD>UART Baud Rate</TD>
<TD>Synthesized by</TD>
</TR>
<TR>
<TD>Altera</TD>
<TD><EM>Future Electronics Cyclone/Nios II Development</EM> <EM>Board</EM></TD>
<TD>EP1C12Q240C6</TD>
<TD>50MHz</TD>
<TD>50MHz</TD>
<TD>115.2KBPS</TD>
<TD>Quartus4.2</TD>
</TR>
<TR>
<TD>Xilinx</TD>
<TD>Xilin‚˜ Spartan3 Starter Kit</TD>
<TD>XC3S200-4FT256C </TD>
<TD>50MHz</TD>
<TD>25MHz</TD>
<TD>57.6KBPS</TD>
<TD>ISE7.1</TD>
</TR>
</TBODY>
</TABLE>
<P><IMG src="future.jpg" width="320" height="240" border="0"><IMG src="spartan3.jpg" width="320" height="240" border="0"></P>
<P><EM>Future Electronics Cyclone/Nios II Development</EM> <EM>Board</EM>
Spartan3 Starter Kit</P>
<P>(1) count<BR>
Same as RTL simulation except for endless loop.<BR>
(2) pi<BR>
3.1415...follows by 800 digits.It was the same
result as PC.<BR>
<BR>
<IMG src="pi800_by_cyclone.png" width="860" height="566" border="0"><BR>
<BR>
(3)Interactive Calculator<BR>
Use PC terminal software.You can calcuate like C program.<BR>
<IMG src="calculator.png" width="860" height="540" border="0"><BR>
<BR>
<BR>
(4) Reed Solomon<BR>
Very Complex program (255,223) performs 120 cycles of 21bytes correction(including
erasures). No miss-correction is detected.</P>
<P><IMG src="rs_by_xilinx.png" width="836" height="566" border="0"></P>
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