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<P><B>6 Post-Layout Gate Simulation</B><BR>
<B>6.1 Spartan3 Gate Simulation</B><BR>
<BR>
Memory Collision Errors are frequently reported as follows. <BR>
</P>
<P><IMG src="xilinx_gatesim2.png" width="783" height="734" border="0"><BR>
<BR>
Since this messages are meaningless for YACC. I checked disable warning
option in coregen generation. However situation was the same. There is
no help for it , I changed primitive description temporally as follows.<BR>
<BR>
parameter 
SIM_COLLISION_CHECK = "NONE";//All ORIG TAK 
Apr.12.2005<BR>
<BR>
<BR>
<IMG src="xilinx_gate_sim1.png" width="783" height="734" border="0"><BR>
Note:<BR>
&nbsp;SDF Error Messages are due to transitional state of simulator at
initial power on sequence.<BR>
<BR>
<BR>
<BR>
<BR>
<B>6.2 Stratix2</B><BR>
<BR>
Run Test Bench at 165MHz.<BR>
<IMG src="stratix2_gatesim.png" width="783" height="715" border="0"><BR>
<BR>
<BR>
<B>6.3 Cyclone</B><BR>
<BR>
Run test bench at 104MHz<BR>
<IMG src="cyclone_gate_sim.png" width="783" height="715" border="0"></P>
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