URL
https://opencores.org/ocsvn/yacc/yacc/trunk
Subversion Repositories yacc
[/] [yacc/] [trunk/] [doc/] [ovewview.htm] - Rev 4
Compare with Previous | Blame | View Log
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<HTML>
<HEAD>
<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">
<META http-equiv="Content-Style-Type" content="text/css">
<TITLE></TITLE>
</HEAD>
<BODY>
<P><B>1.0 Overview</B><BR>
<BR>
YACC (<B>Y</B>et <B>A</B>nother <B>C</B>PU <B>C</B>PU) is MIPS I (TM) subset cpu written in Verilog.-2001HDL. YACC
has 5 pipeline and shows 110DMIPS in stratix2 with synthesized allowable
clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips
tools provided by Steve Rhords, author of plasma (Most mips written in VHDL).<BR>
The core was developed by using Veritak Simulator, with post layout gate
simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit
and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed
Solomon Error Correction ,and Interactive calculator written by C language.</P>
<P><B><FONT class="block_title" size="+0">1.1 Disclaimer</FONT></B>
<P>MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS
Technologies, Inc. MIPS Technologies, Inc. does not endorse and is not
associated with this project. Tak.Sugawara is not affiliated
in any way with MIPS Technologies, Inc.<BR>
</P>
<P><B>1.2 Legal</B><BR>
<BR>I have no idea if implementing this core will or will not violate<BR>
patents, copyrights or cause any other type of lawsuits.<BR>
<BR>
I provide this core "as is", without any warranties. If you decide to<BR>
build this core, you are responsible for any legal resolutions, such<BR>
as patents and copyrights, and perhaps others ....<BR>
<BR>
THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY<BR>
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT<BR>
LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND<BR>
FITNESS FOR A PARTICULAR PURPOSE.</P>
<P><BR>
<BR>
<B> 1.3 Background</B><BR>
<BR>
When I am developing VHDL to Verilog translator , I found plasma core in opencores. It is excellent work to learn a lot. After I <A href="http://www.sugawara-systems.com/opencores/plasma.htm">translated plasma</A> written by VHDL to Verilog HDL almost automatically using
Veritak Translator, I stated to design my own CPU per following target
spec.</P>
<UL>
<LI>works with free C compiler ->use plasma resources
<LI>pretend to be <B><I>fast</I></B> (Actually ..)
<UL>
<LI>5 stage pipeline
<LI>use dual port memory in FPGA (Dhrystone benchmark test requires only
16KB memory !)
</UL>
<LI>works with Altera/Xilinx FPGAs
<LI>with minimum logic cells in FPGA
</UL>
</BODY>
</HTML>