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<P><B>2. Design</B><BR>
<B>2.1 Pipeline Consideration</B><BR>
<BR>
If PC is incremental then YACC performs all instruction at 1 clock
cycle including memory R/W. However, if PC is not incremental, Jump address
calculation is necessary , which requires more cycles in YACC.</P>
<P>(1) Normal Commands :- 1Clock Cycle</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ALU</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">MEM</TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
</TBODY>
</TABLE>
<P>(2) Jump address is known at fetch Cycle -2 Clock Cycle</P>
<P>GCC tries to insert delayed branch command just after jump command. Therefore
no performance penalty will be in most cases.</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Jump Detected)</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Jumped Address)</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
</TBODY>
</TABLE>
<P>(3) Register Jump : -3 Clock Cycle</P>
<P> Jump Address is not determined until Register File is read. This
will result performance penalty.</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Register Jump Detected)</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Jumped Address)</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
</TR>
</TBODY>
</TABLE>
<P>
<BR>
</P>
<P>(4) Branch with Branch commands : -4 Clock Cycle</P>
<P> We can not set branch address until take is set. This will be big
penalty in YACC. To improve this situation, branch prediction mechanism
will be necessary. (Not implemented in YACC).</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Branch command Detected)</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Not Taken</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Branch Address</TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Branch Address)</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
</TR>
</TBODY>
</TABLE>
<P>(5) Not Branch with Branch commands : -3 Clock Cycle</P>
<P> After Taken is Not set, we understand PC is incremental.</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Branch command Detected)</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Not Taken</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & DecFetch (Not Branched Address)</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile </TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
</TR>
</TBODY>
</TABLE>
<P>(6) Interrupt -2 Clock Cycle</P>
<P>In YACC interrupt is like jump command.To simplify the interrupt logic,Interrupt
is inhibited during mul/div/jump/branch commands in YACC implementation.</P>
<TABLE border="1">
<TBODY>
<TR>
<TH valign="middle" align="center">Time Slot</TH>
<TH valign="middle" align="center">Stage1</TH>
<TH valign="middle" align="center">Stage2</TH>
<TH valign="middle" align="center">Stage3</TH>
<TH valign="middle" align="center">Stage4</TH>
<TH valign="middle" align="center">Stage5</TH>
</TR>
<TR>
<TD valign="middle" align="center"> </TD>
<TD valign="middle" align="center">Set Register File Address</TD>
<TD valign="middle" align="center">Read Register File<BR>
ALU_LEFT/Right Latch</TD>
<TD valign="middle" align="center">Mem Write<BR>
AReg<=ALU</TD>
<TD valign="middle" align="center">Mem Read<BR>
NReg<=AReg</TD>
<TD valign="middle" align="center">Write Register File<BR>
RReg<=NReg</TD>
</TR>
<TR>
<TD valign="middle" align="center">1</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Interrupt)</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">2</TD>
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#ffff00">Set Interrupt Address/<BR>
Save Returned Address</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">3</TD>
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Interrupt Address)</TD>
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">4</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
<TD valign="middle" align="center"></TD>
</TR>
<TR>
<TD valign="middle" align="center">5</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
</TR>
<TR>
<TD valign="middle" align="center">6</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
</TR>
<TR>
<TD valign="middle" align="center">7</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
</TR>
<TR>
<TD valign="middle" align="center">8</TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
<TD valign="middle" align="center"></TD>
</TR>
</TBODY>
</TABLE>
<P>
<BR>
</P>
</BODY>
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