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<P><B>3 Logic Synthesis</B><BR>
<BR>
First, I considered pipeline design using Stratix2 synthesis result.(Many
Try and Errors). After that Xilinx implementation has been done.Therefore
Stratix2 implementation should give more optimal result than Xilinx.</P>
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<TD width=238 height=73>Platform</TD>
<TD width=168 height=73>Result of Logic Synthesis </TD>
<TD width=191 height=73>Frequency</TD>
<TD width=189 height=73>Remarks</TD>
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<TD width=238 height=2>Xilinx Starter Kit(XC3S200 ISE7.1)</TD>
<TD width=168 height=2>1918(99%)</TD>
<TD width=191 height=2>25MHz</TD>
<TD width=189 height=2>AREA Priority First</TD>
</TR>
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<TD width=238>Cyclone(EP1C12Q240C6Web Edition Quartus4.2SP1)</TD>
<TD width=168>3624(30%)</TD>
<TD width=191>104.7MHz</TD>
<TD width=189>SPEED Priority First</TD>
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<TD height=66>StratixUiEP2S15F484C3<BR>
Web Edition Quartus4.2SP1)</TD>
<TD height=66>2926(23%)</TD>
<TD height=66>165MHz</TD>
<TD width=189 height=66>SPEED Priority First</TD>
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<P><BR>
<B>Spartan3</B></P>
<P><IMG src="xilinx_synthesis.png" width="897" height="672" border="0"><BR>
<BR>
<BR>
<B>Cyclon</B>e<BR>
<IMG src="cyclone_synthesis2.png" width="952" height="683" border="0"></P>
<P><IMG src="cyclone_synthesis.png" width="952" height="683" border="0"></P>
<P><BR>
<B>Stratix2</B><BR>
<IMG src="stratix2_synthesis1.png" width="952" height="683" border="0"><BR>
<IMG src="stratix2_synthesis2.png" width="952" height="683" border="0"><BR>
<BR>
</P>
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