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[/] [yacc/] [trunk/] [syn/] [altra_stratix2/] [fifo512_cyclone_bb.v] - Rev 2
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// megafunction wizard: %FIFO%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: scfifo // ============================================================ // File Name: fifo512_cyclone.v // Megafunction Name(s): // scfifo // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2005 Altera Corporation //Any megafunction design, and related netlist (encrypted or decrypted), //support information, device programming or simulation file, and any other //associated documentation or information provided by Altera or a partner //under Altera's Megafunction Partnership Program may be used only //to program PLD devices (but not masked PLD devices) from Altera. Any //other use of such megafunction design, netlist, support information, //device programming or simulation file, or any other related documentation //or information is prohibited for any other purpose, including, but not //limited to modification, reverse engineering, de-compiling, or use with //any other silicon devices, unless such use is explicitly licensed under //a separate agreement with Altera or a megafunction partner. Title to the //intellectual property, including patents, copyrights, trademarks, trade //secrets, or maskworks, embodied in any such megafunction design, netlist, //support information, device programming or simulation file, or any other //related documentation or information provided by Altera or a megafunction //partner, remains with Altera, the megafunction partner, or their respective //licensors. No other licenses, including any licenses needed under any third //party's intellectual property, are provided herein. module fifo512_cyclone ( data, wrreq, rdreq, clock, q, full, empty); input [7:0] data; input wrreq; input rdreq; input clock; output [7:0] q; output full; output empty; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: Width NUMERIC "8" // Retrieval info: PRIVATE: Depth NUMERIC "512" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: UsedW NUMERIC "0" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "2" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty // Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 // Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_wave*.jpg FALSE
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