Subversion Repositories yacc

The following files were generated for <ram1k0> in directory 
F:\yacc\syn\xilinx:

ram1k0.asy:
   Graphical symbol information file. Used by the ISE tools and some
   third party tools to create a symbol representing the core.

ram1k0.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

ram1k0.mif:
   Memory Initialization File which is automatically generated by the
   CORE Generator System for some modules when a simulation flow is
   specified. A MIF data file is used to support HDL functional
   simulation of modules which use arrays of values.

ram1k0.sym:
   Please see the core data sheet.

ram1k0.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

ram1k0.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

ram1k0.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

ram1k0.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

ram1k0.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

ram1k0_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

ram1k0_readme.txt:
   Text file indicating the files generated and how they are used.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.