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Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 4 -pcf s3_vsmpl.pcf -sdf_anno true -w
-ofmt verilog -sim s3_vsmpl.ncd s3_vsmpl_timesim.v  

Read and Annotate design 's3_vsmpl.ncd' ...
Loading device for application Rf_Device from file '3s200.nph' in environment
E:/Xilinx7.1.
   "s3_vsmpl" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
Loading constraints from 's3_vsmpl.pcf'...
The speed grade (-4) differs from the speed grade specified in the .ncd file
(-4).
The number of routable networks is 3575
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog SDF file 's3_vsmpl_timesim.sdf' ...
Writing Verilog netlist file 's3_vsmpl_timesim.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Verification Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Number of warnings: 0
Number of info messages: 2
Total memory usage is 120472 kilobytes