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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [CII_Starter_USB_API.sta.rpt] - Rev 12
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TimeQuest Timing Analyzer report for CII_Starter_USB_APISun Oct 11 12:25:21 2009Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. TimeQuest Timing Analyzer Summary3. Clocks4. Slow Model Fmax Summary5. Slow Model Setup Summary6. Slow Model Hold Summary7. Slow Model Recovery Summary8. Slow Model Removal Summary9. Slow Model Minimum Pulse Width10. Setup Times11. Hold Times12. Clock to Output Times13. Minimum Clock to Output Times14. Propagation Delay15. Minimum Propagation Delay16. Fast Model Setup Summary17. Fast Model Hold Summary18. Fast Model Recovery Summary19. Fast Model Removal Summary20. Fast Model Minimum Pulse Width21. Setup Times22. Hold Times23. Clock to Output Times24. Minimum Clock to Output Times25. Propagation Delay26. Minimum Propagation Delay27. Multicorner Timing Analysis Summary28. Setup Times29. Hold Times30. Clock to Output Times31. Minimum Clock to Output Times32. Progagation Delay33. Minimum Progagation Delay34. Setup Transfers35. Hold Transfers36. Recovery Transfers37. Removal Transfers38. Report TCCS39. Report RSKM40. Unconstrained Paths41. TimeQuest Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------------+; TimeQuest Timing Analyzer Summary ;+--------------------+----------------------------------------------------------------+; Quartus II Version ; Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition ;; Revision Name ; CII_Starter_USB_API ;; Device Family ; Cyclone II ;; Device Name ; EP2C20F484C7 ;; Timing Models ; Final ;; Delay Model ; Combined ;; Rise/Fall Delays ; Unavailable ;+--------------------+----------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clocks ;+----------------------------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------+------------------------------------------------+--------------------------------------------------+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;+----------------------------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------+------------------------------------------------+--------------------------------------------------+; AUDIO_DAC:u11|LRCK_1X ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { AUDIO_DAC:u11|LRCK_1X } ;; AUDIO_DAC:u11|LRCK_2X ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { AUDIO_DAC:u11|LRCK_2X } ;; AUDIO_DAC:u11|LRCK_4X ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { AUDIO_DAC:u11|LRCK_4X } ;; AUDIO_DAC:u11|oAUD_BCK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { AUDIO_DAC:u11|oAUD_BCK } ;; CLOCK_27[0] ; Base ; 37.037 ; 27.0 MHz ; 0.000 ; 18.518 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_27[0] } ;; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { I2C_AV_Config:u10|mI2C_CTRL_CLK } ;; p1|altpll_component|pll|clk[0] ; Generated ; 39.682 ; 25.2 MHz ; 0.000 ; 19.841 ; 50.00 ; 15 ; 14 ; ; ; ; ; false ; CLOCK_27[0] ; p1|altpll_component|pll|inclk[0] ; { p1|altpll_component|pll|clk[0] } ;; p1|altpll_component|pll|clk[1] ; Generated ; 55.555 ; 18.0 MHz ; 0.000 ; 27.777 ; 50.00 ; 3 ; 2 ; ; ; ; ; false ; CLOCK_27[0] ; p1|altpll_component|pll|inclk[0] ; { p1|altpll_component|pll|clk[1] } ;; TCK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { TCK } ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; Generated ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; CLOCK_50 ; u3|u1|sdram_pll1|altpll_component|pll|inclk[0] ; { u3|u1|sdram_pll1|altpll_component|pll|clk[0] } ;; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ; Generated ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; CLOCK_50 ; u3|u1|sdram_pll1|altpll_component|pll|inclk[0] ; { u3|u1|sdram_pll1|altpll_component|pll|clk[2] } ;; USB_JTAG:u1|mTCK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { USB_JTAG:u1|mTCK } ;+----------------------------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------+------------------------------------------------+--------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------+; Slow Model Fmax Summary ;+------------+-----------------+----------------------------------------------+-------------------------------------------------------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+----------------------------------------------+-------------------------------------------------------+; 65.2 MHz ; 65.2 MHz ; p1|altpll_component|pll|clk[0] ; ;; 97.63 MHz ; 97.63 MHz ; CLOCK_50 ; ;; 189.39 MHz ; 189.39 MHz ; TCK ; ;; 190.66 MHz ; 190.66 MHz ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; ;; 207.81 MHz ; 207.81 MHz ; AUDIO_DAC:u11|LRCK_4X ; ;; 256.02 MHz ; 256.02 MHz ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; ;; 297.35 MHz ; 297.35 MHz ; p1|altpll_component|pll|clk[1] ; ;; 403.71 MHz ; 403.71 MHz ; AUDIO_DAC:u11|LRCK_1X ; ;; 476.64 MHz ; 450.05 MHz ; USB_JTAG:u1|mTCK ; limit due to high minimum pulse width violation (tch) ;; 671.14 MHz ; 450.05 MHz ; AUDIO_DAC:u11|oAUD_BCK ; limit due to low minimum pulse width violation (tcl) ;+------------+-----------------+----------------------------------------------+-------------------------------------------------------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.+-----------------------------------------------------------------------+; Slow Model Setup Summary ;+----------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------+--------+---------------+; p1|altpll_component|pll|clk[0] ; -8.207 ; -93.462 ;; TCK ; -4.280 ; -9.429 ;; AUDIO_DAC:u11|LRCK_4X ; -3.812 ; -101.895 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.906 ; -72.732 ;; CLOCK_50 ; -1.570 ; -12.001 ;; AUDIO_DAC:u11|LRCK_1X ; -1.477 ; -7.476 ;; AUDIO_DAC:u11|LRCK_2X ; -1.281 ; -12.787 ;; USB_JTAG:u1|mTCK ; -1.098 ; -9.913 ;; AUDIO_DAC:u11|oAUD_BCK ; -0.490 ; -0.861 ;; p1|altpll_component|pll|clk[1] ; -0.349 ; -1.380 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 12.201 ; 0.000 ;+----------------------------------------------+--------+---------------++-----------------------------------------------------------------------+; Slow Model Hold Summary ;+----------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------+--------+---------------+; CLOCK_50 ; -2.702 ; -29.887 ;; p1|altpll_component|pll|clk[1] ; 0.092 ; 0.000 ;; AUDIO_DAC:u11|LRCK_1X ; 0.445 ; 0.000 ;; AUDIO_DAC:u11|LRCK_4X ; 0.445 ; 0.000 ;; AUDIO_DAC:u11|oAUD_BCK ; 0.445 ; 0.000 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 0.445 ; 0.000 ;; TCK ; 0.445 ; 0.000 ;; USB_JTAG:u1|mTCK ; 0.445 ; 0.000 ;; p1|altpll_component|pll|clk[0] ; 0.445 ; 0.000 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 0.445 ; 0.000 ;; AUDIO_DAC:u11|LRCK_2X ; 1.325 ; 0.000 ;+----------------------------------------------+--------+---------------++---------------------------------------------------------+; Slow Model Recovery Summary ;+--------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------+--------+---------------+; p1|altpll_component|pll|clk[0] ; -6.299 ; -449.521 ;; p1|altpll_component|pll|clk[1] ; -5.585 ; -172.713 ;; AUDIO_DAC:u11|LRCK_4X ; -3.362 ; -112.147 ;; AUDIO_DAC:u11|LRCK_2X ; -3.234 ; -49.977 ;; AUDIO_DAC:u11|LRCK_1X ; -2.733 ; -16.398 ;; AUDIO_DAC:u11|oAUD_BCK ; -2.710 ; -18.970 ;+--------------------------------+--------+---------------++--------------------------------------------------------+; Slow Model Removal Summary ;+--------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------+-------+---------------+; AUDIO_DAC:u11|LRCK_4X ; 2.977 ; 0.000 ;; AUDIO_DAC:u11|oAUD_BCK ; 3.462 ; 0.000 ;; AUDIO_DAC:u11|LRCK_1X ; 3.485 ; 0.000 ;; AUDIO_DAC:u11|LRCK_2X ; 3.686 ; 0.000 ;; p1|altpll_component|pll|clk[1] ; 5.306 ; 0.000 ;; p1|altpll_component|pll|clk[0] ; 5.800 ; 0.000 ;+--------------------------------+-------+---------------++----------------------------------------------------------------------------------------------------------------------------------+; Slow Model Minimum Pulse Width ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------+; -1.469 ; 1.000 ; 2.469 ; Port Rate ; TCK ; Rise ; TCK ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[0] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[0] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[10] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[10] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[11] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[11] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[12] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[12] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[13] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[13] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[14] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[14] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[15] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[15] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[16] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[16] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[17] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[17] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[18] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[18] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[19] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[19] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[1] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[1] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[20] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[20] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[21] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[21] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[2] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[2] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[3] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[3] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[4] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[4] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[5] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[5] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[6] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[6] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[7] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[7] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[8] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[8] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[9] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[9] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[0] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[0] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[10] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[10] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[11] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[11] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[12] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[12] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[13] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[13] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[14] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[14] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[15] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[15] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[1] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[1] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[2] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[2] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[3] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[3] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[4] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[4] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[5] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[5] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[6] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[6] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[7] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[7] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[8] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[8] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[9] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[9] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[0] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[0] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[10] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[10] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[11] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[11] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[12] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[12] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[13] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[13] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[14] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[14] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[15] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[15] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[1] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[1] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[2] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[2] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[3] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[3] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[4] ;; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[4] ;; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[5] ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------++------------------------------------------------------------------------------------------------------------------------------+; Setup Times ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 4.167 ; 4.167 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 4.221 ; 4.221 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 4.028 ; 4.028 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 4.109 ; 4.109 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 4.623 ; 4.623 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 4.539 ; 4.539 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 4.520 ; 4.520 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; 7.902 ; 7.902 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; 7.902 ; 7.902 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; 4.587 ; 4.587 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 7.346 ; 7.346 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 6.894 ; 6.894 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 6.418 ; 6.418 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 5.690 ; 5.690 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 6.759 ; 6.759 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 6.123 ; 6.123 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 6.675 ; 6.675 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 6.104 ; 6.104 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 6.674 ; 6.674 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 7.346 ; 7.346 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 6.634 ; 6.634 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 5.528 ; 5.528 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 6.445 ; 6.445 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 6.159 ; 6.159 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 6.111 ; 6.111 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 5.812 ; 5.812 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 7.128 ; 7.128 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; 1.706 ; 1.706 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 5.658 ; 5.658 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.291 ; 6.291 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.291 ; 6.291 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; 3.841 ; 3.841 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; 3.023 ; 3.023 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; 11.831 ; 11.831 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; 9.880 ; 9.880 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; 9.905 ; 9.905 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; 9.635 ; 9.635 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; 11.508 ; 11.508 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; 9.475 ; 9.475 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; 9.193 ; 9.193 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; 9.341 ; 9.341 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; 11.831 ; 11.831 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 7.723 ; 7.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 7.209 ; 7.209 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 7.160 ; 7.160 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 7.479 ; 7.479 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 7.134 ; 7.134 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 7.559 ; 7.559 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 7.175 ; 7.175 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 7.182 ; 7.182 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 7.723 ; 7.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 6.713 ; 6.713 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 6.828 ; 6.828 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 6.860 ; 6.860 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 6.589 ; 6.589 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 7.306 ; 7.306 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 6.709 ; 6.709 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 7.651 ; 7.651 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 7.324 ; 7.324 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; 8.649 ; 8.649 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; 8.649 ; 8.649 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------++------------------------------------------------------------------------------------------------------------------------------+; Hold Times ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; -3.780 ; -3.780 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; -3.919 ; -3.919 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; -3.973 ; -3.973 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; -3.780 ; -3.780 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; -3.861 ; -3.861 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; -4.375 ; -4.375 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; -4.291 ; -4.291 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; -4.433 ; -4.433 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; -4.272 ; -4.272 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; -3.810 ; -3.810 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; -3.810 ; -3.810 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; -4.339 ; -4.339 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; -4.346 ; -4.346 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; -5.280 ; -5.280 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; -6.646 ; -6.646 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; -6.170 ; -6.170 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; -5.442 ; -5.442 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; -6.511 ; -6.511 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; -5.875 ; -5.875 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; -6.427 ; -6.427 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; -5.856 ; -5.856 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; -6.426 ; -6.426 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; -7.098 ; -7.098 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; -6.386 ; -6.386 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; -5.280 ; -5.280 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; -6.197 ; -6.197 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; -5.911 ; -5.911 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; -5.863 ; -5.863 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; -5.564 ; -5.564 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; -6.880 ; -6.880 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; -1.458 ; -1.458 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -4.148 ; -4.148 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -5.416 ; -5.416 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -5.416 ; -5.416 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; -2.850 ; -2.850 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; -2.760 ; -2.760 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; -8.743 ; -8.743 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; -9.406 ; -9.406 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; -9.653 ; -9.653 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; -9.037 ; -9.037 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; -8.911 ; -8.911 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; -9.001 ; -9.001 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; -8.941 ; -8.941 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; -8.743 ; -8.743 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; -9.234 ; -9.234 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; -6.341 ; -6.341 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; -6.961 ; -6.961 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; -6.912 ; -6.912 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; -7.231 ; -7.231 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; -6.886 ; -6.886 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; -7.311 ; -7.311 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; -6.927 ; -6.927 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; -6.934 ; -6.934 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; -7.475 ; -7.475 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; -6.465 ; -6.465 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; -6.580 ; -6.580 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; -6.612 ; -6.612 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; -6.341 ; -6.341 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; -7.058 ; -7.058 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; -6.461 ; -6.461 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; -7.403 ; -7.403 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; -7.076 ; -7.076 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; -7.227 ; -7.227 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; -7.227 ; -7.227 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.897 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.907 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.897 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 17.724 ; 17.724 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.907 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 16.094 ; 16.094 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 7.961 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 7.961 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 18.331 ; 18.331 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 12.237 ; 12.237 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 11.637 ; 11.637 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 11.654 ; 11.654 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 10.537 ; 10.537 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 11.960 ; 11.960 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 10.852 ; 10.852 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 12.237 ; 12.237 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 11.640 ; 11.640 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 11.659 ; 11.659 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 11.086 ; 11.086 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 11.593 ; 11.593 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 11.632 ; 11.632 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 11.856 ; 11.856 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 9.936 ; 9.936 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 10.068 ; 10.068 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 9.846 ; 9.846 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 10.079 ; 10.079 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 10.022 ; 10.022 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 10.273 ; 10.273 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 9.575 ; 9.575 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 9.999 ; 9.999 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 10.304 ; 10.304 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 10.069 ; 10.069 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 7.575 ; 7.575 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 10.889 ; 10.889 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 9.462 ; 9.462 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 9.206 ; 9.206 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 9.938 ; 9.938 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 9.184 ; 9.184 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 10.889 ; 10.889 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 10.696 ; 10.696 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 10.431 ; 10.431 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 10.695 ; 10.695 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 8.623 ; 8.623 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 9.683 ; 9.683 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 9.803 ; 9.803 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 9.252 ; 9.252 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 8.771 ; 8.771 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 9.696 ; 9.696 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 9.803 ; 9.803 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 9.612 ; 9.612 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 8.850 ; 8.850 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 9.719 ; 9.719 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 10.139 ; 10.139 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 9.522 ; 9.522 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 9.460 ; 9.460 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 8.904 ; 8.904 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 8.701 ; 8.701 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 9.648 ; 9.648 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 10.139 ; 10.139 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 10.077 ; 10.077 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 10.291 ; 10.291 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 9.911 ; 9.911 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 9.808 ; 9.808 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 9.853 ; 9.853 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 10.291 ; 10.291 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 9.796 ; 9.796 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 10.051 ; 10.051 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 9.829 ; 9.829 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 10.028 ; 10.028 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 9.998 ; 9.998 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 10.028 ; 10.028 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 10.006 ; 10.006 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 9.439 ; 9.439 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 9.103 ; 9.103 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 8.943 ; 8.943 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 10.019 ; 10.019 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 8.434 ; 8.434 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 8.003 ; 8.003 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 8.324 ; 8.324 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 8.357 ; 8.357 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 8.331 ; 8.331 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 8.434 ; 8.434 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 8.024 ; 8.024 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 8.408 ; 8.408 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 8.382 ; 8.382 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 8.900 ; 8.900 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 7.980 ; 7.980 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 8.008 ; 8.008 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 8.365 ; 8.365 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 8.727 ; 8.727 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 8.900 ; 8.900 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 8.700 ; 8.700 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 8.486 ; 8.486 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 8.572 ; 8.572 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 8.864 ; 8.864 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 8.876 ; 8.876 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 11.345 ; 11.345 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 10.879 ; 10.879 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 10.638 ; 10.638 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 10.442 ; 10.442 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 10.465 ; 10.465 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 10.650 ; 10.650 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 8.862 ; 8.862 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 9.490 ; 9.490 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 8.932 ; 8.932 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 9.299 ; 9.299 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 10.049 ; 10.049 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 10.089 ; 10.089 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 10.060 ; 10.060 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 10.331 ; 10.331 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 10.659 ; 10.659 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 10.570 ; 10.570 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 10.601 ; 10.601 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 11.345 ; 11.345 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 11.197 ; 11.197 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 11.882 ; 11.882 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 11.200 ; 11.200 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 11.210 ; 11.210 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 11.535 ; 11.535 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 11.545 ; 11.545 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 10.671 ; 10.671 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 10.669 ; 10.669 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 10.960 ; 10.960 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 10.965 ; 10.965 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 11.515 ; 11.515 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 11.515 ; 11.515 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 11.484 ; 11.484 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 11.199 ; 11.199 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 11.219 ; 11.219 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 11.494 ; 11.494 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 11.408 ; 11.408 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 11.882 ; 11.882 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 12.012 ; 12.012 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 10.085 ; 10.085 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 12.189 ; 12.189 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 8.797 ; 8.797 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.344 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 7.369 ; 7.369 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 9.386 ; 9.386 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 8.683 ; 8.683 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 8.702 ; 8.702 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 8.037 ; 8.037 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 8.243 ; 8.243 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 9.386 ; 9.386 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 6.460 ; 6.460 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 7.288 ; 7.288 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 6.541 ; 6.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 7.088 ; 7.088 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 7.422 ; 7.422 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 7.436 ; 7.436 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 7.729 ; 7.729 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 7.725 ; 7.725 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 7.976 ; 7.976 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 8.634 ; 8.634 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 8.669 ; 8.669 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 8.794 ; 8.794 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 8.541 ; 8.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 13.283 ; 13.283 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 13.283 ; 13.283 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 11.613 ; 11.613 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 11.408 ; 11.408 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 11.968 ; 11.968 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 13.260 ; 13.260 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 12.329 ; 12.329 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 12.956 ; 12.956 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 12.040 ; 12.040 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 13.260 ; 13.260 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 5.757 ; 5.757 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 13.529 ; 13.529 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 13.360 ; 13.360 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 13.529 ; 13.529 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 13.236 ; 13.236 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 12.655 ; 12.655 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 5.878 ; 5.878 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 2.904 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 2.904 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 5.419 ; 5.419 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 5.322 ; 5.322 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 5.359 ; 5.359 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 5.419 ; 5.419 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 5.340 ; 5.340 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 4.925 ; 4.925 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 4.948 ; 4.948 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 4.919 ; 4.919 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 4.910 ; 4.910 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 4.600 ; 4.600 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 5.323 ; 5.323 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 4.929 ; 4.929 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 5.621 ; 5.621 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 5.746 ; 5.746 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 5.307 ; 5.307 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 5.319 ; 5.319 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 5.587 ; 5.587 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 6.298 ; 6.298 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 5.829 ; 5.829 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 6.167 ; 6.167 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 6.291 ; 6.291 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 5.609 ; 5.609 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 5.667 ; 5.667 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 6.298 ; 6.298 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 6.238 ; 6.238 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 5.524 ; 5.524 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 5.883 ; 5.883 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 5.883 ; 5.883 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 5.874 ; 5.874 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 5.874 ; 5.874 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 5.902 ; 5.902 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 5.538 ; 5.538 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 5.846 ; 5.846 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 5.820 ; 5.820 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 6.348 ; 6.348 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 5.046 ; 5.046 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 6.723 ; 6.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 4.620 ; 4.620 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; 1.072 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; 1.072 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Minimum Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.897 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.907 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.897 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 11.735 ; 11.735 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.907 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 12.772 ; 12.772 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 7.961 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 7.961 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 13.731 ; 13.731 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 8.111 ; 8.111 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 9.851 ; 9.851 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 9.428 ; 9.428 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 8.111 ; 8.111 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 9.072 ; 9.072 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 8.522 ; 8.522 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 9.857 ; 9.857 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 9.215 ; 9.215 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 8.777 ; 8.777 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 9.303 ; 9.303 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 8.713 ; 8.713 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 9.777 ; 9.777 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 8.978 ; 8.978 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 9.067 ; 9.067 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 9.200 ; 9.200 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 8.976 ; 8.976 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 9.209 ; 9.209 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 9.484 ; 9.484 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 9.383 ; 9.383 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 8.923 ; 8.923 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 9.295 ; 9.295 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 9.257 ; 9.257 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 9.039 ; 9.039 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 7.575 ; 7.575 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 8.044 ; 8.044 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 8.591 ; 8.591 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 8.044 ; 8.044 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 8.044 ; 8.044 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 8.328 ; 8.328 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 8.642 ; 8.642 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 8.647 ; 8.647 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 9.171 ; 9.171 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 9.161 ; 9.161 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 8.623 ; 8.623 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 8.573 ; 8.573 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 8.007 ; 8.007 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 8.694 ; 8.694 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 8.216 ; 8.216 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 9.137 ; 9.137 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 9.034 ; 9.034 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 8.773 ; 8.773 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 8.007 ; 8.007 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 8.878 ; 8.878 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 8.103 ; 8.103 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 9.137 ; 9.137 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 9.066 ; 9.066 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 8.549 ; 8.549 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 8.103 ; 8.103 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 9.053 ; 9.053 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 9.325 ; 9.325 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 9.265 ; 9.265 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 9.211 ; 9.211 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 9.702 ; 9.702 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 9.568 ; 9.568 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 9.606 ; 9.606 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 9.246 ; 9.246 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 9.211 ; 9.211 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 9.287 ; 9.287 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 9.211 ; 9.211 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 8.326 ; 8.326 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 9.589 ; 9.589 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 9.628 ; 9.628 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 9.600 ; 9.600 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 8.818 ; 8.818 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 8.488 ; 8.488 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 8.326 ; 8.326 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 9.401 ; 9.401 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 8.003 ; 8.003 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 8.003 ; 8.003 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 8.324 ; 8.324 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 8.357 ; 8.357 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 8.331 ; 8.331 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 8.434 ; 8.434 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 8.024 ; 8.024 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 8.408 ; 8.408 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 8.382 ; 8.382 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 7.980 ; 7.980 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 7.980 ; 7.980 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 8.008 ; 8.008 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 8.365 ; 8.365 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 8.727 ; 8.727 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 8.900 ; 8.900 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 8.700 ; 8.700 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 8.486 ; 8.486 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 8.572 ; 8.572 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 8.864 ; 8.864 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 8.876 ; 8.876 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 8.274 ; 8.274 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 10.087 ; 10.087 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 10.122 ; 10.122 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 9.855 ; 9.855 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 9.678 ; 9.678 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 9.863 ; 9.863 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 8.274 ; 8.274 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 8.697 ; 8.697 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 8.345 ; 8.345 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 8.506 ; 8.506 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 8.860 ; 8.860 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 8.894 ; 8.894 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 8.865 ; 8.865 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 9.144 ; 9.144 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 9.463 ; 9.463 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 9.339 ; 9.339 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 9.379 ; 9.379 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 10.153 ; 10.153 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 10.011 ; 10.011 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 8.289 ; 8.289 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 8.604 ; 8.604 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 8.590 ; 8.590 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 9.453 ; 9.453 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 8.807 ; 8.807 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 8.575 ; 8.575 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 8.572 ; 8.572 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 8.289 ; 8.289 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 8.576 ; 8.576 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 8.816 ; 8.816 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 8.492 ; 8.492 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 8.842 ; 8.842 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 8.810 ; 8.810 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 8.594 ; 8.594 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 8.821 ; 8.821 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 9.302 ; 9.302 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 8.855 ; 8.855 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 11.145 ; 11.145 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 9.216 ; 9.216 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 9.909 ; 6.344 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 8.797 ; 8.797 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.344 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 7.369 ; 7.369 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 6.460 ; 6.460 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 8.683 ; 8.683 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 8.702 ; 8.702 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 8.037 ; 8.037 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 8.243 ; 8.243 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 9.386 ; 9.386 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 6.460 ; 6.460 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 7.288 ; 7.288 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 6.541 ; 6.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 7.088 ; 7.088 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 7.422 ; 7.422 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 7.436 ; 7.436 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 7.729 ; 7.729 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 7.725 ; 7.725 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 7.976 ; 7.976 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 8.634 ; 8.634 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 8.669 ; 8.669 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 8.794 ; 8.794 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 8.541 ; 8.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 5.908 ; 5.908 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 7.522 ; 7.522 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 7.145 ; 7.145 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 7.533 ; 7.533 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 5.908 ; 5.908 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 6.988 ; 6.988 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 7.299 ; 7.299 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 7.730 ; 7.730 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 6.988 ; 6.988 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 8.367 ; 8.367 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 5.757 ; 5.757 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 7.429 ; 7.429 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 7.868 ; 7.868 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 8.287 ; 8.287 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 8.016 ; 8.016 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 7.429 ; 7.429 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 5.878 ; 5.878 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 2.904 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 2.904 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 5.322 ; 5.322 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 5.359 ; 5.359 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 5.419 ; 5.419 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 5.340 ; 5.340 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 4.925 ; 4.925 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 4.948 ; 4.948 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 4.919 ; 4.919 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 4.910 ; 4.910 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 4.600 ; 4.600 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 5.323 ; 5.323 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 4.929 ; 4.929 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 5.621 ; 5.621 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 5.746 ; 5.746 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 5.307 ; 5.307 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 5.319 ; 5.319 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 5.587 ; 5.587 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 4.647 ; 4.647 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 5.507 ; 5.507 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 5.507 ; 5.507 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 5.167 ; 5.167 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 5.167 ; 5.167 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 5.514 ; 5.514 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 5.484 ; 5.484 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 5.524 ; 5.524 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 5.134 ; 5.134 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 4.647 ; 4.647 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 5.388 ; 5.388 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 5.200 ; 5.200 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 5.789 ; 5.789 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 5.513 ; 5.513 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 5.513 ; 5.513 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 5.513 ; 5.513 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 5.513 ; 5.513 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 6.348 ; 6.348 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 5.046 ; 5.046 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 6.723 ; 6.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 4.620 ; 4.620 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; 1.072 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; 1.072 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------+; Propagation Delay ;+------------+-------------+--------+--------+--------+--------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+--------+--------+--------+--------+; SW[0] ; AUD_DACDAT ; 11.020 ; 11.758 ; 11.758 ; 11.020 ;; SW[1] ; AUD_DACDAT ; ; 11.398 ; 11.398 ; ;+------------+-------------+--------+--------+--------+--------++--------------------------------------------------------------+; Minimum Propagation Delay ;+------------+-------------+--------+--------+--------+--------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+--------+--------+--------+--------+; SW[0] ; AUD_DACDAT ; 11.020 ; 10.601 ; 10.601 ; 11.020 ;; SW[1] ; AUD_DACDAT ; ; 10.241 ; 10.241 ; ;+------------+-------------+--------+--------+--------+--------++-----------------------------------------------------------------------+; Fast Model Setup Summary ;+----------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------+--------+---------------+; p1|altpll_component|pll|clk[0] ; -4.123 ; -47.614 ;; TCK ; -1.188 ; -1.216 ;; AUDIO_DAC:u11|LRCK_4X ; -0.857 ; -22.460 ;; p1|altpll_component|pll|clk[1] ; -0.493 ; -1.956 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -0.456 ; -5.870 ;; AUDIO_DAC:u11|LRCK_2X ; -0.221 ; -0.692 ;; CLOCK_50 ; -0.193 ; -0.496 ;; AUDIO_DAC:u11|LRCK_1X ; 0.029 ; 0.000 ;; USB_JTAG:u1|mTCK ; 0.071 ; 0.000 ;; AUDIO_DAC:u11|oAUD_BCK ; 0.418 ; 0.000 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 15.989 ; 0.000 ;+----------------------------------------------+--------+---------------++-----------------------------------------------------------------------+; Fast Model Hold Summary ;+----------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------+--------+---------------+; CLOCK_50 ; -1.811 ; -29.851 ;; TCK ; 0.148 ; 0.000 ;; AUDIO_DAC:u11|LRCK_1X ; 0.215 ; 0.000 ;; AUDIO_DAC:u11|LRCK_4X ; 0.215 ; 0.000 ;; AUDIO_DAC:u11|oAUD_BCK ; 0.215 ; 0.000 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 0.215 ; 0.000 ;; USB_JTAG:u1|mTCK ; 0.215 ; 0.000 ;; p1|altpll_component|pll|clk[0] ; 0.215 ; 0.000 ;; p1|altpll_component|pll|clk[1] ; 0.215 ; 0.000 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 0.215 ; 0.000 ;; AUDIO_DAC:u11|LRCK_2X ; 0.805 ; 0.000 ;+----------------------------------------------+--------+---------------++---------------------------------------------------------+; Fast Model Recovery Summary ;+--------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------+--------+---------------+; p1|altpll_component|pll|clk[0] ; -3.677 ; -264.018 ;; p1|altpll_component|pll|clk[1] ; -3.379 ; -104.241 ;; AUDIO_DAC:u11|LRCK_4X ; -1.334 ; -39.561 ;; AUDIO_DAC:u11|LRCK_2X ; -1.264 ; -19.520 ;; AUDIO_DAC:u11|LRCK_1X ; -1.079 ; -6.474 ;; AUDIO_DAC:u11|oAUD_BCK ; -1.071 ; -7.497 ;+--------------------------------+--------+---------------++--------------------------------------------------------+; Fast Model Removal Summary ;+--------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------+-------+---------------+; AUDIO_DAC:u11|LRCK_4X ; 1.458 ; 0.000 ;; AUDIO_DAC:u11|oAUD_BCK ; 1.951 ; 0.000 ;; AUDIO_DAC:u11|LRCK_1X ; 1.959 ; 0.000 ;; AUDIO_DAC:u11|LRCK_2X ; 2.025 ; 0.000 ;; p1|altpll_component|pll|clk[1] ; 3.242 ; 0.000 ;; p1|altpll_component|pll|clk[0] ; 3.466 ; 0.000 ;+--------------------------------+-------+---------------++----------------------------------------------------------------------------------------------------------------------------------+; Fast Model Minimum Pulse Width ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------+; -1.222 ; 1.000 ; 2.222 ; Port Rate ; TCK ; Rise ; TCK ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[0] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[0] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[10] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[10] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[11] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[11] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[12] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[12] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[13] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[13] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[14] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[14] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[15] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[15] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[16] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[16] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[17] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[17] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[18] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[18] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[19] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[19] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[1] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[1] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[20] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[20] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[21] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[21] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[2] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[2] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[3] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[3] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[4] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[4] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[5] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[5] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[6] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[6] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[7] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[7] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[8] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[8] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[9] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Fall ; AUDIO_DAC:u11|FLASH_Cont[9] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[0] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[0] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[10] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[10] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[11] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[11] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[12] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[12] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[13] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[13] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[14] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[14] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[15] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[15] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[1] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[1] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[2] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[2] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[3] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[3] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[4] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[4] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[5] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[5] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[6] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[6] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[7] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[7] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[8] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[8] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[9] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_2X ; Fall ; AUDIO_DAC:u11|FLASH_Out[9] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[0] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[0] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[10] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[10] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[11] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[11] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[12] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[12] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[13] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[13] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[14] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[14] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[15] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[15] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[1] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[1] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[2] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[2] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[3] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[3] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[4] ;; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[4] ;; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; AUDIO_DAC:u11|LRCK_4X ; Rise ; AUDIO_DAC:u11|FLASH_Out_Tmp[5] ;+--------+--------------+----------------+------------------+-----------------------+------------+---------------------------------++----------------------------------------------------------------------------------------------------------------------------+; Setup Times ;+--------------+---------------------------------+-------+-------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+-------+-------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; 2.185 ; 2.185 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 1.930 ; 1.930 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 1.970 ; 1.970 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 1.845 ; 1.845 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 1.905 ; 1.905 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 2.147 ; 2.147 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 2.080 ; 2.080 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 2.185 ; 2.185 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 2.068 ; 2.068 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; 3.489 ; 3.489 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; 3.489 ; 3.489 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; 2.125 ; 2.125 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; 2.127 ; 2.127 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 3.258 ; 3.258 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 3.049 ; 3.049 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 2.872 ; 2.872 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 2.576 ; 2.576 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 2.937 ; 2.937 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 2.698 ; 2.698 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 2.905 ; 2.905 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 2.660 ; 2.660 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 2.896 ; 2.896 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 3.258 ; 3.258 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 2.925 ; 2.925 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 2.473 ; 2.473 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 2.808 ; 2.808 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 2.718 ; 2.718 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 2.679 ; 2.679 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 2.584 ; 2.584 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 3.093 ; 3.093 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; 0.693 ; 0.693 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.541 ; 2.541 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.970 ; 2.970 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.970 ; 2.970 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; 1.764 ; 1.764 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; 1.387 ; 1.387 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; 5.767 ; 5.767 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; 5.049 ; 5.049 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; 5.090 ; 5.090 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; 4.955 ; 4.955 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; 5.663 ; 5.663 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; 4.914 ; 4.914 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; 4.812 ; 4.812 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; 4.875 ; 4.875 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; 5.767 ; 5.767 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 4.361 ; 4.361 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 4.128 ; 4.128 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 4.099 ; 4.099 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 4.229 ; 4.229 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 4.079 ; 4.079 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 4.273 ; 4.273 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 4.099 ; 4.099 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 4.119 ; 4.119 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 4.361 ; 4.361 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 3.896 ; 3.896 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 3.963 ; 3.963 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 3.988 ; 3.988 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 3.816 ; 3.816 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 4.183 ; 4.183 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 3.894 ; 3.894 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 4.308 ; 4.308 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 4.130 ; 4.130 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; 4.741 ; 4.741 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; 4.741 ; 4.741 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+-------+-------+------------+----------------------------------------------++------------------------------------------------------------------------------------------------------------------------------+; Hold Times ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; -1.725 ; -1.725 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; -1.810 ; -1.810 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; -1.850 ; -1.850 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; -1.725 ; -1.725 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; -1.785 ; -1.785 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; -2.027 ; -2.027 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; -1.960 ; -1.960 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; -2.065 ; -2.065 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; -1.948 ; -1.948 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; -1.777 ; -1.777 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; -1.777 ; -1.777 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; -2.005 ; -2.005 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; -2.007 ; -2.007 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; -2.353 ; -2.353 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; -2.929 ; -2.929 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; -2.752 ; -2.752 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; -2.456 ; -2.456 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; -2.817 ; -2.817 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; -2.578 ; -2.578 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; -2.785 ; -2.785 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; -2.540 ; -2.540 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; -2.776 ; -2.776 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; -3.138 ; -3.138 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; -2.805 ; -2.805 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; -2.353 ; -2.353 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; -2.688 ; -2.688 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; -2.598 ; -2.598 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; -2.559 ; -2.559 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; -2.464 ; -2.464 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; -2.973 ; -2.973 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; -0.573 ; -0.573 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -1.985 ; -1.985 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.642 ; -2.642 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.642 ; -2.642 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; -1.357 ; -1.357 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; -1.259 ; -1.259 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; -4.631 ; -4.631 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; -4.853 ; -4.853 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; -4.965 ; -4.965 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; -4.711 ; -4.711 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; -4.717 ; -4.717 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; -4.718 ; -4.718 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; -4.687 ; -4.687 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; -4.631 ; -4.631 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; -4.821 ; -4.821 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; -3.696 ; -3.696 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; -4.008 ; -4.008 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; -3.979 ; -3.979 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; -4.109 ; -4.109 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; -3.959 ; -3.959 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; -4.153 ; -4.153 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; -3.979 ; -3.979 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; -3.999 ; -3.999 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; -4.241 ; -4.241 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; -3.776 ; -3.776 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; -3.843 ; -3.843 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; -3.868 ; -3.868 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; -3.696 ; -3.696 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; -4.063 ; -4.063 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; -3.774 ; -3.774 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; -4.188 ; -4.188 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; -4.010 ; -4.010 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; -4.112 ; -4.112 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; -4.112 ; -4.112 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.550 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.560 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.550 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 7.815 ; 7.815 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.560 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 7.220 ; 7.220 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 3.617 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 3.617 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 8.021 ; 8.021 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 5.824 ; 5.824 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 5.605 ; 5.605 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 5.603 ; 5.603 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 5.201 ; 5.201 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 5.722 ; 5.722 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 5.316 ; 5.316 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 5.824 ; 5.824 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 5.596 ; 5.596 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 5.599 ; 5.599 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 5.392 ; 5.392 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 5.563 ; 5.563 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 5.587 ; 5.587 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 5.648 ; 5.648 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 4.994 ; 4.994 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 5.002 ; 5.002 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 4.939 ; 4.939 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 5.008 ; 5.008 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 4.991 ; 4.991 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 5.099 ; 5.099 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 4.866 ; 4.866 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 4.968 ; 4.968 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 5.093 ; 5.093 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 5.019 ; 5.019 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 3.953 ; 3.953 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 5.340 ; 5.340 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 4.804 ; 4.804 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 4.713 ; 4.713 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 4.940 ; 4.940 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 4.699 ; 4.699 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 5.340 ; 5.340 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 5.246 ; 5.246 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 5.129 ; 5.129 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 5.241 ; 5.241 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 4.480 ; 4.480 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 4.838 ; 4.838 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 4.844 ; 4.844 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 4.615 ; 4.615 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 4.461 ; 4.461 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 4.779 ; 4.779 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 4.844 ; 4.844 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 4.763 ; 4.763 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 4.503 ; 4.503 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 4.780 ; 4.780 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 4.963 ; 4.963 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 4.719 ; 4.719 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 4.669 ; 4.669 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 4.528 ; 4.528 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 4.451 ; 4.451 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 4.787 ; 4.787 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 4.963 ; 4.963 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 4.923 ; 4.923 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 5.001 ; 5.001 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 4.877 ; 4.877 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 4.805 ; 4.805 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 4.855 ; 4.855 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 5.001 ; 5.001 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 4.834 ; 4.834 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 4.917 ; 4.917 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 4.834 ; 4.834 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 4.974 ; 4.974 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 4.928 ; 4.928 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 4.974 ; 4.974 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 4.968 ; 4.968 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 4.657 ; 4.657 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 4.563 ; 4.563 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 4.543 ; 4.543 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 4.945 ; 4.945 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 4.353 ; 4.353 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 4.156 ; 4.156 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 4.276 ; 4.276 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 4.300 ; 4.300 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 4.286 ; 4.286 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 4.353 ; 4.353 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 4.214 ; 4.214 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 4.341 ; 4.341 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 4.322 ; 4.322 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 4.135 ; 4.135 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 4.151 ; 4.151 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 4.304 ; 4.304 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 4.458 ; 4.458 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 4.438 ; 4.438 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 4.409 ; 4.409 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 4.490 ; 4.490 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 4.463 ; 4.463 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 4.471 ; 4.471 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 5.555 ; 5.555 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 5.339 ; 5.339 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 5.346 ; 5.346 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 5.208 ; 5.208 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 5.181 ; 5.181 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 5.289 ; 5.289 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 4.568 ; 4.568 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 4.922 ; 4.922 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 4.615 ; 4.615 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 4.717 ; 4.717 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 5.020 ; 5.020 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 5.036 ; 5.036 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 5.032 ; 5.032 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 5.130 ; 5.130 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 5.262 ; 5.262 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 5.268 ; 5.268 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 5.258 ; 5.258 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 5.555 ; 5.555 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 5.467 ; 5.467 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 5.697 ; 5.697 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 5.445 ; 5.445 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 5.455 ; 5.455 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 5.580 ; 5.580 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 5.590 ; 5.590 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 5.253 ; 5.253 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 5.251 ; 5.251 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 5.359 ; 5.359 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 5.365 ; 5.365 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 5.560 ; 5.560 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 5.560 ; 5.560 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 5.534 ; 5.534 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 5.422 ; 5.422 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 5.442 ; 5.442 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 5.544 ; 5.544 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 5.535 ; 5.535 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 5.697 ; 5.697 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 5.833 ; 5.833 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 5.030 ; 5.030 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 5.631 ; 5.631 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 4.441 ; 4.441 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.845 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 3.958 ; 3.958 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 3.731 ; 3.731 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 3.432 ; 3.432 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 3.575 ; 3.575 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 3.241 ; 3.241 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 3.271 ; 3.271 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 3.731 ; 3.731 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 2.601 ; 2.601 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 3.017 ; 3.017 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 2.657 ; 2.657 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 2.807 ; 2.807 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 3.104 ; 3.104 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 3.093 ; 3.093 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 3.203 ; 3.203 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 3.481 ; 3.481 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 3.486 ; 3.486 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 3.553 ; 3.553 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 3.402 ; 3.402 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 5.346 ; 5.346 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 5.346 ; 5.346 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 4.547 ; 4.547 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 4.502 ; 4.502 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 4.747 ; 4.747 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 5.213 ; 5.213 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 4.921 ; 4.921 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 5.090 ; 5.090 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 4.826 ; 4.826 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 5.213 ; 5.213 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 2.350 ; 2.350 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 5.306 ; 5.306 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 5.285 ; 5.285 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 5.306 ; 5.306 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 5.202 ; 5.202 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 5.011 ; 5.011 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 2.397 ; 2.397 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 1.117 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 1.117 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 2.195 ; 2.195 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 2.133 ; 2.133 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 2.150 ; 2.150 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 2.195 ; 2.195 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 2.149 ; 2.149 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 1.954 ; 1.954 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 1.967 ; 1.967 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 1.944 ; 1.944 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 1.938 ; 1.938 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 1.827 ; 1.827 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 1.825 ; 1.825 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 2.132 ; 2.132 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 1.942 ; 1.942 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 2.341 ; 2.341 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 2.115 ; 2.115 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 2.113 ; 2.113 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 2.215 ; 2.215 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 2.532 ; 2.532 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 2.323 ; 2.323 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 2.457 ; 2.457 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 2.532 ; 2.532 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 2.293 ; 2.293 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 2.327 ; 2.327 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 2.522 ; 2.522 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 2.503 ; 2.503 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 2.217 ; 2.217 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 2.362 ; 2.362 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 2.362 ; 2.362 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 2.353 ; 2.353 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 2.353 ; 2.353 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 2.359 ; 2.359 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 2.250 ; 2.250 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 2.326 ; 2.326 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 2.313 ; 2.313 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 2.586 ; 2.586 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 2.028 ; 2.028 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 2.647 ; 2.647 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 1.844 ; 1.844 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; -0.119 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; -0.119 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Minimum Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.550 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.560 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.550 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 5.641 ; 5.641 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.560 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 6.104 ; 6.104 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 3.617 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 3.617 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 6.418 ; 6.418 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 4.284 ; 4.284 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 4.923 ; 4.923 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 4.757 ; 4.757 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 4.284 ; 4.284 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 4.639 ; 4.639 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 4.431 ; 4.431 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 4.925 ; 4.925 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 4.680 ; 4.680 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 4.520 ; 4.520 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 4.717 ; 4.717 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 4.484 ; 4.484 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 4.897 ; 4.897 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 4.697 ; 4.697 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 4.707 ; 4.707 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 4.640 ; 4.640 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 4.709 ; 4.709 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 4.788 ; 4.788 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 4.767 ; 4.767 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 4.619 ; 4.619 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 4.686 ; 4.686 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 4.621 ; 4.621 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 3.953 ; 3.953 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 4.460 ; 4.460 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 4.372 ; 4.372 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 4.498 ; 4.498 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 4.502 ; 4.502 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 4.694 ; 4.694 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 4.684 ; 4.684 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 4.480 ; 4.480 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 4.475 ; 4.475 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 4.228 ; 4.228 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 4.409 ; 4.409 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 4.267 ; 4.267 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 4.581 ; 4.581 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 4.600 ; 4.600 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 4.497 ; 4.497 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 4.228 ; 4.228 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 4.515 ; 4.515 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 4.280 ; 4.280 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 4.595 ; 4.595 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 4.536 ; 4.536 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 4.396 ; 4.396 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 4.280 ; 4.280 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 4.615 ; 4.615 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 4.717 ; 4.717 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 4.679 ; 4.679 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 4.648 ; 4.648 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 4.801 ; 4.801 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 4.728 ; 4.728 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 4.768 ; 4.768 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 4.667 ; 4.667 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 4.648 ; 4.648 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 4.685 ; 4.685 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 4.649 ; 4.649 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 4.348 ; 4.348 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 4.778 ; 4.778 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 4.837 ; 4.837 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 4.824 ; 4.824 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 4.469 ; 4.469 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 4.370 ; 4.370 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 4.348 ; 4.348 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 4.757 ; 4.757 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 4.156 ; 4.156 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 4.156 ; 4.156 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 4.276 ; 4.276 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 4.300 ; 4.300 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 4.286 ; 4.286 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 4.353 ; 4.353 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 4.214 ; 4.214 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 4.341 ; 4.341 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 4.322 ; 4.322 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 4.135 ; 4.135 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 4.135 ; 4.135 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 4.151 ; 4.151 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 4.304 ; 4.304 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 4.458 ; 4.458 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 4.438 ; 4.438 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 4.409 ; 4.409 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 4.490 ; 4.490 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 4.463 ; 4.463 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 4.471 ; 4.471 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 4.369 ; 4.369 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 5.060 ; 5.060 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 5.202 ; 5.202 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 4.905 ; 4.905 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 5.013 ; 5.013 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 4.369 ; 4.369 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 4.639 ; 4.639 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 4.418 ; 4.418 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 4.436 ; 4.436 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 4.584 ; 4.584 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 4.596 ; 4.596 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 4.591 ; 4.591 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 4.696 ; 4.696 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 4.821 ; 4.821 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 4.827 ; 4.827 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 4.825 ; 4.825 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 5.118 ; 5.118 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 5.033 ; 5.033 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 4.382 ; 4.382 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 4.560 ; 4.560 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 4.548 ; 4.548 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 4.818 ; 4.818 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 4.608 ; 4.608 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 4.491 ; 4.491 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 4.489 ; 4.489 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 4.382 ; 4.382 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 4.487 ; 4.487 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 4.564 ; 4.564 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 4.469 ; 4.469 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 4.578 ; 4.578 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 4.559 ; 4.559 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 4.550 ; 4.550 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 4.569 ; 4.569 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 4.764 ; 4.764 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 4.634 ; 4.634 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 5.500 ; 5.500 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 4.695 ; 4.695 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 4.842 ; 2.845 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 4.441 ; 4.441 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.845 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 3.958 ; 3.958 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 2.601 ; 2.601 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 3.432 ; 3.432 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 3.575 ; 3.575 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 3.241 ; 3.241 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 3.271 ; 3.271 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 3.731 ; 3.731 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 2.601 ; 2.601 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 3.017 ; 3.017 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 2.657 ; 2.657 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 2.807 ; 2.807 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 3.104 ; 3.104 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 3.093 ; 3.093 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 3.203 ; 3.203 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 3.481 ; 3.481 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 3.486 ; 3.486 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 3.553 ; 3.553 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 3.402 ; 3.402 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 2.426 ; 2.426 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 3.138 ; 3.138 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 2.842 ; 2.842 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 3.006 ; 3.006 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 2.426 ; 2.426 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 2.919 ; 2.919 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 3.005 ; 3.005 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 3.082 ; 3.082 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 2.919 ; 2.919 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 3.329 ; 3.329 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 2.350 ; 2.350 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 3.000 ; 3.000 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 3.183 ; 3.183 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 3.286 ; 3.286 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 3.196 ; 3.196 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 3.000 ; 3.000 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 2.397 ; 2.397 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 1.117 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 1.117 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 1.825 ; 1.825 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 2.133 ; 2.133 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 2.150 ; 2.150 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 2.195 ; 2.195 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 2.149 ; 2.149 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 1.954 ; 1.954 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 1.967 ; 1.967 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 1.944 ; 1.944 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 1.938 ; 1.938 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 1.827 ; 1.827 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 1.825 ; 1.825 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 2.132 ; 2.132 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 1.942 ; 1.942 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 2.341 ; 2.341 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 2.115 ; 2.115 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 2.113 ; 2.113 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 2.215 ; 2.215 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 1.916 ; 1.916 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 2.200 ; 2.200 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 2.200 ; 2.200 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 2.068 ; 2.068 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 2.068 ; 2.068 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 2.207 ; 2.207 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 2.177 ; 2.177 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 2.217 ; 2.217 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 2.150 ; 2.150 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 1.916 ; 1.916 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 2.162 ; 2.162 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 2.071 ; 2.071 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 2.289 ; 2.289 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 2.586 ; 2.586 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 2.028 ; 2.028 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 2.647 ; 2.647 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 1.844 ; 1.844 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; -0.119 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; -0.119 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++----------------------------------------------------------+; Propagation Delay ;+------------+-------------+-------+-------+-------+-------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+-------+-------+-------+-------+; SW[0] ; AUD_DACDAT ; 4.931 ; 5.202 ; 5.202 ; 4.931 ;; SW[1] ; AUD_DACDAT ; ; 5.033 ; 5.033 ; ;+------------+-------------+-------+-------+-------+-------++----------------------------------------------------------+; Minimum Propagation Delay ;+------------+-------------+-------+-------+-------+-------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+-------+-------+-------+-------+; SW[0] ; AUD_DACDAT ; 4.931 ; 4.802 ; 4.802 ; 4.931 ;; SW[1] ; AUD_DACDAT ; ; 4.633 ; 4.633 ; ;+------------+-------------+-------+-------+-------+-------++---------------------------------------------------------------------------------------------------------------+; Multicorner Timing Analysis Summary ;+-----------------------------------------------+----------+---------+----------+---------+---------------------+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;+-----------------------------------------------+----------+---------+----------+---------+---------------------+; Worst-case Slack ; -8.207 ; -2.702 ; -6.299 ; 0.0 ; -1.469 ;; AUDIO_DAC:u11|LRCK_1X ; -1.477 ; 0.215 ; -2.733 ; 1.959 ; N/A ;; AUDIO_DAC:u11|LRCK_2X ; -1.281 ; 0.805 ; -3.234 ; 2.025 ; -0.611 ;; AUDIO_DAC:u11|LRCK_4X ; -3.812 ; 0.215 ; -3.362 ; 1.458 ; -0.611 ;; AUDIO_DAC:u11|oAUD_BCK ; -0.490 ; 0.215 ; -2.710 ; 1.951 ; N/A ;; CLOCK_50 ; -1.570 ; -2.702 ; N/A ; N/A ; N/A ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.906 ; 0.215 ; N/A ; N/A ; N/A ;; TCK ; -4.280 ; 0.148 ; N/A ; N/A ; -1.469 ;; USB_JTAG:u1|mTCK ; -1.098 ; 0.215 ; N/A ; N/A ; N/A ;; p1|altpll_component|pll|clk[0] ; -8.207 ; 0.215 ; -6.299 ; 3.466 ; N/A ;; p1|altpll_component|pll|clk[1] ; -0.493 ; 0.092 ; -5.585 ; 3.242 ; N/A ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 12.201 ; 0.215 ; N/A ; N/A ; N/A ;; Design-wide TNS ; -321.936 ; -29.887 ; -819.726 ; 0.0 ; N/A ;; AUDIO_DAC:u11|LRCK_1X ; -7.476 ; 0.000 ; -16.398 ; 0.000 ; N/A ;; AUDIO_DAC:u11|LRCK_2X ; -12.787 ; 0.000 ; -49.977 ; 0.000 ; N/A ;; AUDIO_DAC:u11|LRCK_4X ; -101.895 ; 0.000 ; -112.147 ; 0.000 ; N/A ;; AUDIO_DAC:u11|oAUD_BCK ; -0.861 ; 0.000 ; -18.970 ; 0.000 ; N/A ;; CLOCK_50 ; -12.001 ; -29.887 ; N/A ; N/A ; N/A ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -72.732 ; 0.000 ; N/A ; N/A ; N/A ;; TCK ; -9.429 ; 0.000 ; N/A ; N/A ; N/A ;; USB_JTAG:u1|mTCK ; -9.913 ; 0.000 ; N/A ; N/A ; N/A ;; p1|altpll_component|pll|clk[0] ; -93.462 ; 0.000 ; -449.521 ; 0.000 ; N/A ;; p1|altpll_component|pll|clk[1] ; -1.956 ; 0.000 ; -172.713 ; 0.000 ; N/A ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 0.000 ; 0.000 ; N/A ; N/A ; N/A ;+-----------------------------------------------+----------+---------+----------+---------+---------------------++------------------------------------------------------------------------------------------------------------------------------+; Setup Times ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 4.167 ; 4.167 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 4.221 ; 4.221 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 4.028 ; 4.028 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 4.109 ; 4.109 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 4.623 ; 4.623 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 4.539 ; 4.539 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 4.520 ; 4.520 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; 7.902 ; 7.902 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; 7.902 ; 7.902 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; 4.587 ; 4.587 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 7.346 ; 7.346 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 6.894 ; 6.894 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 6.418 ; 6.418 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 5.690 ; 5.690 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 6.759 ; 6.759 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 6.123 ; 6.123 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 6.675 ; 6.675 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 6.104 ; 6.104 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 6.674 ; 6.674 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 7.346 ; 7.346 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 6.634 ; 6.634 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 5.528 ; 5.528 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 6.445 ; 6.445 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 6.159 ; 6.159 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 6.111 ; 6.111 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 5.812 ; 5.812 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 7.128 ; 7.128 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; 1.706 ; 1.706 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 5.658 ; 5.658 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.291 ; 6.291 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.291 ; 6.291 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; 3.841 ; 3.841 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; 3.023 ; 3.023 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; 11.831 ; 11.831 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; 9.880 ; 9.880 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; 9.905 ; 9.905 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; 9.635 ; 9.635 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; 11.508 ; 11.508 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; 9.475 ; 9.475 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; 9.193 ; 9.193 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; 9.341 ; 9.341 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; 11.831 ; 11.831 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 7.723 ; 7.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 7.209 ; 7.209 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 7.160 ; 7.160 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 7.479 ; 7.479 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 7.134 ; 7.134 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 7.559 ; 7.559 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 7.175 ; 7.175 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 7.182 ; 7.182 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 7.723 ; 7.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 6.713 ; 6.713 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 6.828 ; 6.828 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 6.860 ; 6.860 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 6.589 ; 6.589 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 7.306 ; 7.306 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 6.709 ; 6.709 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 7.651 ; 7.651 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 7.324 ; 7.324 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; 8.649 ; 8.649 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; 8.649 ; 8.649 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------++------------------------------------------------------------------------------------------------------------------------------+; Hold Times ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------+; FL_DQ[*] ; CLOCK_50 ; -1.725 ; -1.725 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; -1.810 ; -1.810 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; -1.850 ; -1.850 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; -1.725 ; -1.725 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; -1.785 ; -1.785 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; -2.027 ; -2.027 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; -1.960 ; -1.960 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; -2.065 ; -2.065 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; -1.948 ; -1.948 ; Rise ; CLOCK_50 ;; KEY[*] ; CLOCK_50 ; -1.777 ; -1.777 ; Rise ; CLOCK_50 ;; KEY[0] ; CLOCK_50 ; -1.777 ; -1.777 ; Rise ; CLOCK_50 ;; PS2_CLK ; CLOCK_50 ; -2.005 ; -2.005 ; Rise ; CLOCK_50 ;; PS2_DAT ; CLOCK_50 ; -2.007 ; -2.007 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; -2.353 ; -2.353 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; -2.929 ; -2.929 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; -2.752 ; -2.752 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; -2.456 ; -2.456 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; -2.817 ; -2.817 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; -2.578 ; -2.578 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; -2.785 ; -2.785 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; -2.540 ; -2.540 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; -2.776 ; -2.776 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; -3.138 ; -3.138 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; -2.805 ; -2.805 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; -2.353 ; -2.353 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; -2.688 ; -2.688 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; -2.598 ; -2.598 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; -2.559 ; -2.559 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; -2.464 ; -2.464 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; -2.973 ; -2.973 ; Rise ; CLOCK_50 ;; TCK ; CLOCK_50 ; -0.573 ; -0.573 ; Rise ; CLOCK_50 ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -1.985 ; -1.985 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[*] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.642 ; -2.642 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; KEY[0] ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; -2.642 ; -2.642 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TCS ; USB_JTAG:u1|mTCK ; -1.357 ; -1.357 ; Rise ; USB_JTAG:u1|mTCK ;; TDI ; USB_JTAG:u1|mTCK ; -1.259 ; -1.259 ; Rise ; USB_JTAG:u1|mTCK ;; SRAM_DQ[*] ; CLOCK_27[0] ; -4.631 ; -4.631 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[4] ; CLOCK_27[0] ; -4.853 ; -4.853 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[5] ; CLOCK_27[0] ; -4.965 ; -4.965 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[6] ; CLOCK_27[0] ; -4.711 ; -4.711 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[7] ; CLOCK_27[0] ; -4.717 ; -4.717 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[12] ; CLOCK_27[0] ; -4.718 ; -4.718 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[13] ; CLOCK_27[0] ; -4.687 ; -4.687 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[14] ; CLOCK_27[0] ; -4.631 ; -4.631 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_DQ[15] ; CLOCK_27[0] ; -4.821 ; -4.821 ; Rise ; p1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; -3.696 ; -3.696 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; -4.008 ; -4.008 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; -3.979 ; -3.979 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; -4.109 ; -4.109 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; -3.959 ; -3.959 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; -4.153 ; -4.153 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; -3.979 ; -3.979 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; -3.999 ; -3.999 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; -4.241 ; -4.241 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; -3.776 ; -3.776 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; -3.843 ; -3.843 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; -3.868 ; -3.868 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; -3.696 ; -3.696 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; -4.063 ; -4.063 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; -3.774 ; -3.774 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; -4.188 ; -4.188 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; -4.010 ; -4.010 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[*] ; CLOCK_50 ; -4.112 ; -4.112 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; KEY[0] ; CLOCK_50 ; -4.112 ; -4.112 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;+--------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.897 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 7.907 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.897 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 17.724 ; 17.724 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 7.907 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 16.094 ; 16.094 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 7.961 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 7.961 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 18.331 ; 18.331 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 12.237 ; 12.237 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 11.637 ; 11.637 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 11.654 ; 11.654 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 10.537 ; 10.537 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 11.960 ; 11.960 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 10.852 ; 10.852 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 12.237 ; 12.237 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 11.640 ; 11.640 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 11.659 ; 11.659 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 11.086 ; 11.086 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 11.593 ; 11.593 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 11.632 ; 11.632 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 11.856 ; 11.856 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 9.936 ; 9.936 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 10.068 ; 10.068 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 9.846 ; 9.846 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 10.079 ; 10.079 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 10.022 ; 10.022 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 10.273 ; 10.273 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 9.575 ; 9.575 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 9.999 ; 9.999 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 10.304 ; 10.304 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 10.069 ; 10.069 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 7.575 ; 7.575 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 10.889 ; 10.889 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 9.462 ; 9.462 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 9.206 ; 9.206 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 9.938 ; 9.938 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 9.184 ; 9.184 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 10.889 ; 10.889 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 10.696 ; 10.696 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 10.431 ; 10.431 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 10.695 ; 10.695 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 8.623 ; 8.623 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 9.683 ; 9.683 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 9.803 ; 9.803 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 9.252 ; 9.252 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 8.771 ; 8.771 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 9.696 ; 9.696 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 9.803 ; 9.803 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 9.612 ; 9.612 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 8.850 ; 8.850 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 9.719 ; 9.719 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 10.139 ; 10.139 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 9.522 ; 9.522 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 9.460 ; 9.460 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 8.904 ; 8.904 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 8.701 ; 8.701 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 9.648 ; 9.648 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 10.139 ; 10.139 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 10.077 ; 10.077 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 10.291 ; 10.291 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 9.911 ; 9.911 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 9.808 ; 9.808 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 9.853 ; 9.853 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 10.291 ; 10.291 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 9.796 ; 9.796 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 10.051 ; 10.051 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 9.829 ; 9.829 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 10.028 ; 10.028 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 9.998 ; 9.998 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 10.028 ; 10.028 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 10.006 ; 10.006 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 9.439 ; 9.439 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 9.103 ; 9.103 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 8.943 ; 8.943 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 10.019 ; 10.019 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 8.434 ; 8.434 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 8.003 ; 8.003 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 8.324 ; 8.324 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 8.357 ; 8.357 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 8.331 ; 8.331 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 8.434 ; 8.434 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 8.024 ; 8.024 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 8.408 ; 8.408 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 8.382 ; 8.382 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 8.900 ; 8.900 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 7.980 ; 7.980 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 8.008 ; 8.008 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 8.365 ; 8.365 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 8.727 ; 8.727 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 8.900 ; 8.900 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 8.700 ; 8.700 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 8.486 ; 8.486 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 8.572 ; 8.572 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 8.864 ; 8.864 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 8.876 ; 8.876 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 11.345 ; 11.345 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 10.879 ; 10.879 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 10.638 ; 10.638 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 10.442 ; 10.442 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 10.465 ; 10.465 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 10.650 ; 10.650 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 8.862 ; 8.862 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 9.490 ; 9.490 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 8.932 ; 8.932 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 9.299 ; 9.299 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 10.049 ; 10.049 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 10.089 ; 10.089 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 10.060 ; 10.060 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 10.331 ; 10.331 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 10.659 ; 10.659 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 10.570 ; 10.570 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 10.601 ; 10.601 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 11.345 ; 11.345 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 11.197 ; 11.197 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 11.882 ; 11.882 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 11.200 ; 11.200 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 11.210 ; 11.210 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 11.535 ; 11.535 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 11.545 ; 11.545 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 10.671 ; 10.671 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 10.669 ; 10.669 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 10.960 ; 10.960 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 10.965 ; 10.965 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 11.515 ; 11.515 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 11.515 ; 11.515 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 11.484 ; 11.484 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 11.199 ; 11.199 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 11.219 ; 11.219 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 11.494 ; 11.494 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 11.408 ; 11.408 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 11.882 ; 11.882 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 12.012 ; 12.012 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 10.085 ; 10.085 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 12.189 ; 12.189 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 8.797 ; 8.797 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 6.344 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 7.369 ; 7.369 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 9.386 ; 9.386 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 8.683 ; 8.683 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 8.702 ; 8.702 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 8.037 ; 8.037 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 8.243 ; 8.243 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 9.386 ; 9.386 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 6.460 ; 6.460 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 7.288 ; 7.288 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 6.541 ; 6.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 7.088 ; 7.088 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 7.422 ; 7.422 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 7.436 ; 7.436 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 7.729 ; 7.729 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 7.725 ; 7.725 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 7.976 ; 7.976 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 8.634 ; 8.634 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 8.669 ; 8.669 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 8.794 ; 8.794 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 8.541 ; 8.541 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 13.283 ; 13.283 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 13.283 ; 13.283 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 11.613 ; 11.613 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 11.408 ; 11.408 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 11.968 ; 11.968 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 13.260 ; 13.260 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 12.329 ; 12.329 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 12.956 ; 12.956 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 12.040 ; 12.040 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 13.260 ; 13.260 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 5.757 ; 5.757 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 13.529 ; 13.529 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 13.360 ; 13.360 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 13.529 ; 13.529 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 13.236 ; 13.236 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 12.655 ; 12.655 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 5.878 ; 5.878 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 2.904 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 2.904 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 5.419 ; 5.419 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 5.322 ; 5.322 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 5.359 ; 5.359 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 5.419 ; 5.419 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 5.340 ; 5.340 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 4.925 ; 4.925 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 4.948 ; 4.948 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 4.919 ; 4.919 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 4.910 ; 4.910 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 4.594 ; 4.594 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 4.600 ; 4.600 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 5.323 ; 5.323 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 4.929 ; 4.929 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 5.621 ; 5.621 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 5.746 ; 5.746 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 5.307 ; 5.307 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 5.319 ; 5.319 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 5.587 ; 5.587 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 6.298 ; 6.298 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 5.829 ; 5.829 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 6.167 ; 6.167 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 6.291 ; 6.291 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 5.609 ; 5.609 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 5.667 ; 5.667 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 6.298 ; 6.298 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 6.238 ; 6.238 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 5.524 ; 5.524 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 5.883 ; 5.883 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 5.883 ; 5.883 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 5.874 ; 5.874 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 5.874 ; 5.874 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 5.902 ; 5.902 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 5.538 ; 5.538 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 5.846 ; 5.846 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 5.820 ; 5.820 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 6.348 ; 6.348 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 5.046 ; 5.046 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 6.723 ; 6.723 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 4.620 ; 4.620 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; 1.072 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; 1.072 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Minimum Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------+; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.550 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; 3.560 ; ; Rise ; AUDIO_DAC:u11|LRCK_1X ;; AUD_ADCLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.550 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_1X ; 5.641 ; 5.641 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACLRCK ; AUDIO_DAC:u11|LRCK_1X ; ; 3.560 ; Fall ; AUDIO_DAC:u11|LRCK_1X ;; AUD_DACDAT ; AUDIO_DAC:u11|LRCK_2X ; 6.104 ; 6.104 ; Fall ; AUDIO_DAC:u11|LRCK_2X ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; 3.617 ; ; Rise ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_BCLK ; AUDIO_DAC:u11|oAUD_BCK ; ; 3.617 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; AUD_DACDAT ; AUDIO_DAC:u11|oAUD_BCK ; 6.418 ; 6.418 ; Fall ; AUDIO_DAC:u11|oAUD_BCK ;; FL_ADDR[*] ; CLOCK_50 ; 4.284 ; 4.284 ; Rise ; CLOCK_50 ;; FL_ADDR[0] ; CLOCK_50 ; 4.923 ; 4.923 ; Rise ; CLOCK_50 ;; FL_ADDR[1] ; CLOCK_50 ; 4.757 ; 4.757 ; Rise ; CLOCK_50 ;; FL_ADDR[2] ; CLOCK_50 ; 4.284 ; 4.284 ; Rise ; CLOCK_50 ;; FL_ADDR[3] ; CLOCK_50 ; 4.639 ; 4.639 ; Rise ; CLOCK_50 ;; FL_ADDR[4] ; CLOCK_50 ; 4.431 ; 4.431 ; Rise ; CLOCK_50 ;; FL_ADDR[5] ; CLOCK_50 ; 4.925 ; 4.925 ; Rise ; CLOCK_50 ;; FL_ADDR[6] ; CLOCK_50 ; 4.680 ; 4.680 ; Rise ; CLOCK_50 ;; FL_ADDR[7] ; CLOCK_50 ; 4.520 ; 4.520 ; Rise ; CLOCK_50 ;; FL_ADDR[8] ; CLOCK_50 ; 4.717 ; 4.717 ; Rise ; CLOCK_50 ;; FL_ADDR[9] ; CLOCK_50 ; 4.484 ; 4.484 ; Rise ; CLOCK_50 ;; FL_ADDR[10] ; CLOCK_50 ; 4.897 ; 4.897 ; Rise ; CLOCK_50 ;; FL_ADDR[11] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; FL_ADDR[12] ; CLOCK_50 ; 4.697 ; 4.697 ; Rise ; CLOCK_50 ;; FL_ADDR[13] ; CLOCK_50 ; 4.707 ; 4.707 ; Rise ; CLOCK_50 ;; FL_ADDR[14] ; CLOCK_50 ; 4.640 ; 4.640 ; Rise ; CLOCK_50 ;; FL_ADDR[15] ; CLOCK_50 ; 4.709 ; 4.709 ; Rise ; CLOCK_50 ;; FL_ADDR[16] ; CLOCK_50 ; 4.788 ; 4.788 ; Rise ; CLOCK_50 ;; FL_ADDR[17] ; CLOCK_50 ; 4.767 ; 4.767 ; Rise ; CLOCK_50 ;; FL_ADDR[18] ; CLOCK_50 ; 4.619 ; 4.619 ; Rise ; CLOCK_50 ;; FL_ADDR[19] ; CLOCK_50 ; 4.686 ; 4.686 ; Rise ; CLOCK_50 ;; FL_ADDR[20] ; CLOCK_50 ; 4.681 ; 4.681 ; Rise ; CLOCK_50 ;; FL_ADDR[21] ; CLOCK_50 ; 4.621 ; 4.621 ; Rise ; CLOCK_50 ;; FL_CE_N ; CLOCK_50 ; 3.953 ; 3.953 ; Rise ; CLOCK_50 ;; FL_DQ[*] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[0] ; CLOCK_50 ; 4.460 ; 4.460 ; Rise ; CLOCK_50 ;; FL_DQ[1] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[2] ; CLOCK_50 ; 4.269 ; 4.269 ; Rise ; CLOCK_50 ;; FL_DQ[3] ; CLOCK_50 ; 4.372 ; 4.372 ; Rise ; CLOCK_50 ;; FL_DQ[4] ; CLOCK_50 ; 4.498 ; 4.498 ; Rise ; CLOCK_50 ;; FL_DQ[5] ; CLOCK_50 ; 4.502 ; 4.502 ; Rise ; CLOCK_50 ;; FL_DQ[6] ; CLOCK_50 ; 4.694 ; 4.694 ; Rise ; CLOCK_50 ;; FL_DQ[7] ; CLOCK_50 ; 4.684 ; 4.684 ; Rise ; CLOCK_50 ;; FL_OE_N ; CLOCK_50 ; 4.480 ; 4.480 ; Rise ; CLOCK_50 ;; FL_WE_N ; CLOCK_50 ; 4.475 ; 4.475 ; Rise ; CLOCK_50 ;; HEX0[*] ; CLOCK_50 ; 4.228 ; 4.228 ; Rise ; CLOCK_50 ;; HEX0[0] ; CLOCK_50 ; 4.409 ; 4.409 ; Rise ; CLOCK_50 ;; HEX0[1] ; CLOCK_50 ; 4.267 ; 4.267 ; Rise ; CLOCK_50 ;; HEX0[2] ; CLOCK_50 ; 4.581 ; 4.581 ; Rise ; CLOCK_50 ;; HEX0[3] ; CLOCK_50 ; 4.600 ; 4.600 ; Rise ; CLOCK_50 ;; HEX0[4] ; CLOCK_50 ; 4.497 ; 4.497 ; Rise ; CLOCK_50 ;; HEX0[5] ; CLOCK_50 ; 4.228 ; 4.228 ; Rise ; CLOCK_50 ;; HEX0[6] ; CLOCK_50 ; 4.515 ; 4.515 ; Rise ; CLOCK_50 ;; HEX1[*] ; CLOCK_50 ; 4.280 ; 4.280 ; Rise ; CLOCK_50 ;; HEX1[0] ; CLOCK_50 ; 4.595 ; 4.595 ; Rise ; CLOCK_50 ;; HEX1[1] ; CLOCK_50 ; 4.536 ; 4.536 ; Rise ; CLOCK_50 ;; HEX1[2] ; CLOCK_50 ; 4.396 ; 4.396 ; Rise ; CLOCK_50 ;; HEX1[3] ; CLOCK_50 ; 4.280 ; 4.280 ; Rise ; CLOCK_50 ;; HEX1[4] ; CLOCK_50 ; 4.615 ; 4.615 ; Rise ; CLOCK_50 ;; HEX1[5] ; CLOCK_50 ; 4.717 ; 4.717 ; Rise ; CLOCK_50 ;; HEX1[6] ; CLOCK_50 ; 4.679 ; 4.679 ; Rise ; CLOCK_50 ;; HEX2[*] ; CLOCK_50 ; 4.648 ; 4.648 ; Rise ; CLOCK_50 ;; HEX2[0] ; CLOCK_50 ; 4.801 ; 4.801 ; Rise ; CLOCK_50 ;; HEX2[1] ; CLOCK_50 ; 4.728 ; 4.728 ; Rise ; CLOCK_50 ;; HEX2[2] ; CLOCK_50 ; 4.768 ; 4.768 ; Rise ; CLOCK_50 ;; HEX2[3] ; CLOCK_50 ; 4.667 ; 4.667 ; Rise ; CLOCK_50 ;; HEX2[4] ; CLOCK_50 ; 4.648 ; 4.648 ; Rise ; CLOCK_50 ;; HEX2[5] ; CLOCK_50 ; 4.685 ; 4.685 ; Rise ; CLOCK_50 ;; HEX2[6] ; CLOCK_50 ; 4.649 ; 4.649 ; Rise ; CLOCK_50 ;; HEX3[*] ; CLOCK_50 ; 4.348 ; 4.348 ; Rise ; CLOCK_50 ;; HEX3[0] ; CLOCK_50 ; 4.778 ; 4.778 ; Rise ; CLOCK_50 ;; HEX3[1] ; CLOCK_50 ; 4.837 ; 4.837 ; Rise ; CLOCK_50 ;; HEX3[2] ; CLOCK_50 ; 4.824 ; 4.824 ; Rise ; CLOCK_50 ;; HEX3[3] ; CLOCK_50 ; 4.469 ; 4.469 ; Rise ; CLOCK_50 ;; HEX3[4] ; CLOCK_50 ; 4.370 ; 4.370 ; Rise ; CLOCK_50 ;; HEX3[5] ; CLOCK_50 ; 4.348 ; 4.348 ; Rise ; CLOCK_50 ;; HEX3[6] ; CLOCK_50 ; 4.757 ; 4.757 ; Rise ; CLOCK_50 ;; LEDG[*] ; CLOCK_50 ; 4.156 ; 4.156 ; Rise ; CLOCK_50 ;; LEDG[0] ; CLOCK_50 ; 4.156 ; 4.156 ; Rise ; CLOCK_50 ;; LEDG[1] ; CLOCK_50 ; 4.276 ; 4.276 ; Rise ; CLOCK_50 ;; LEDG[2] ; CLOCK_50 ; 4.300 ; 4.300 ; Rise ; CLOCK_50 ;; LEDG[3] ; CLOCK_50 ; 4.286 ; 4.286 ; Rise ; CLOCK_50 ;; LEDG[4] ; CLOCK_50 ; 4.353 ; 4.353 ; Rise ; CLOCK_50 ;; LEDG[5] ; CLOCK_50 ; 4.214 ; 4.214 ; Rise ; CLOCK_50 ;; LEDG[6] ; CLOCK_50 ; 4.341 ; 4.341 ; Rise ; CLOCK_50 ;; LEDG[7] ; CLOCK_50 ; 4.322 ; 4.322 ; Rise ; CLOCK_50 ;; LEDR[*] ; CLOCK_50 ; 4.135 ; 4.135 ; Rise ; CLOCK_50 ;; LEDR[0] ; CLOCK_50 ; 4.135 ; 4.135 ; Rise ; CLOCK_50 ;; LEDR[1] ; CLOCK_50 ; 4.151 ; 4.151 ; Rise ; CLOCK_50 ;; LEDR[2] ; CLOCK_50 ; 4.304 ; 4.304 ; Rise ; CLOCK_50 ;; LEDR[3] ; CLOCK_50 ; 4.458 ; 4.458 ; Rise ; CLOCK_50 ;; LEDR[4] ; CLOCK_50 ; 4.574 ; 4.574 ; Rise ; CLOCK_50 ;; LEDR[5] ; CLOCK_50 ; 4.438 ; 4.438 ; Rise ; CLOCK_50 ;; LEDR[6] ; CLOCK_50 ; 4.409 ; 4.409 ; Rise ; CLOCK_50 ;; LEDR[7] ; CLOCK_50 ; 4.490 ; 4.490 ; Rise ; CLOCK_50 ;; LEDR[8] ; CLOCK_50 ; 4.463 ; 4.463 ; Rise ; CLOCK_50 ;; LEDR[9] ; CLOCK_50 ; 4.471 ; 4.471 ; Rise ; CLOCK_50 ;; SRAM_ADDR[*] ; CLOCK_50 ; 4.369 ; 4.369 ; Rise ; CLOCK_50 ;; SRAM_ADDR[0] ; CLOCK_50 ; 5.060 ; 5.060 ; Rise ; CLOCK_50 ;; SRAM_ADDR[1] ; CLOCK_50 ; 5.202 ; 5.202 ; Rise ; CLOCK_50 ;; SRAM_ADDR[2] ; CLOCK_50 ; 5.011 ; 5.011 ; Rise ; CLOCK_50 ;; SRAM_ADDR[3] ; CLOCK_50 ; 4.905 ; 4.905 ; Rise ; CLOCK_50 ;; SRAM_ADDR[4] ; CLOCK_50 ; 5.013 ; 5.013 ; Rise ; CLOCK_50 ;; SRAM_ADDR[5] ; CLOCK_50 ; 4.369 ; 4.369 ; Rise ; CLOCK_50 ;; SRAM_ADDR[6] ; CLOCK_50 ; 4.639 ; 4.639 ; Rise ; CLOCK_50 ;; SRAM_ADDR[7] ; CLOCK_50 ; 4.418 ; 4.418 ; Rise ; CLOCK_50 ;; SRAM_ADDR[8] ; CLOCK_50 ; 4.436 ; 4.436 ; Rise ; CLOCK_50 ;; SRAM_ADDR[9] ; CLOCK_50 ; 4.584 ; 4.584 ; Rise ; CLOCK_50 ;; SRAM_ADDR[10] ; CLOCK_50 ; 4.596 ; 4.596 ; Rise ; CLOCK_50 ;; SRAM_ADDR[11] ; CLOCK_50 ; 4.591 ; 4.591 ; Rise ; CLOCK_50 ;; SRAM_ADDR[12] ; CLOCK_50 ; 4.696 ; 4.696 ; Rise ; CLOCK_50 ;; SRAM_ADDR[13] ; CLOCK_50 ; 4.821 ; 4.821 ; Rise ; CLOCK_50 ;; SRAM_ADDR[14] ; CLOCK_50 ; 4.827 ; 4.827 ; Rise ; CLOCK_50 ;; SRAM_ADDR[15] ; CLOCK_50 ; 4.825 ; 4.825 ; Rise ; CLOCK_50 ;; SRAM_ADDR[16] ; CLOCK_50 ; 5.118 ; 5.118 ; Rise ; CLOCK_50 ;; SRAM_ADDR[17] ; CLOCK_50 ; 5.033 ; 5.033 ; Rise ; CLOCK_50 ;; SRAM_DQ[*] ; CLOCK_50 ; 4.382 ; 4.382 ; Rise ; CLOCK_50 ;; SRAM_DQ[0] ; CLOCK_50 ; 4.560 ; 4.560 ; Rise ; CLOCK_50 ;; SRAM_DQ[1] ; CLOCK_50 ; 4.548 ; 4.548 ; Rise ; CLOCK_50 ;; SRAM_DQ[2] ; CLOCK_50 ; 4.818 ; 4.818 ; Rise ; CLOCK_50 ;; SRAM_DQ[3] ; CLOCK_50 ; 4.608 ; 4.608 ; Rise ; CLOCK_50 ;; SRAM_DQ[4] ; CLOCK_50 ; 4.491 ; 4.491 ; Rise ; CLOCK_50 ;; SRAM_DQ[5] ; CLOCK_50 ; 4.489 ; 4.489 ; Rise ; CLOCK_50 ;; SRAM_DQ[6] ; CLOCK_50 ; 4.382 ; 4.382 ; Rise ; CLOCK_50 ;; SRAM_DQ[7] ; CLOCK_50 ; 4.487 ; 4.487 ; Rise ; CLOCK_50 ;; SRAM_DQ[8] ; CLOCK_50 ; 4.564 ; 4.564 ; Rise ; CLOCK_50 ;; SRAM_DQ[9] ; CLOCK_50 ; 4.469 ; 4.469 ; Rise ; CLOCK_50 ;; SRAM_DQ[10] ; CLOCK_50 ; 4.578 ; 4.578 ; Rise ; CLOCK_50 ;; SRAM_DQ[11] ; CLOCK_50 ; 4.559 ; 4.559 ; Rise ; CLOCK_50 ;; SRAM_DQ[12] ; CLOCK_50 ; 4.550 ; 4.550 ; Rise ; CLOCK_50 ;; SRAM_DQ[13] ; CLOCK_50 ; 4.569 ; 4.569 ; Rise ; CLOCK_50 ;; SRAM_DQ[14] ; CLOCK_50 ; 4.764 ; 4.764 ; Rise ; CLOCK_50 ;; SRAM_DQ[15] ; CLOCK_50 ; 4.634 ; 4.634 ; Rise ; CLOCK_50 ;; SRAM_OE_N ; CLOCK_50 ; 5.500 ; 5.500 ; Rise ; CLOCK_50 ;; SRAM_WE_N ; CLOCK_50 ; 4.695 ; 4.695 ; Rise ; CLOCK_50 ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 4.842 ; 2.845 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SDAT ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 4.441 ; 4.441 ; Rise ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; I2C_SCLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 2.845 ; ; Fall ; I2C_AV_Config:u10|mI2C_CTRL_CLK ;; TDO ; TCK ; 3.958 ; 3.958 ; Rise ; TCK ;; SRAM_ADDR[*] ; CLOCK_27[0] ; 2.601 ; 2.601 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[0] ; CLOCK_27[0] ; 3.432 ; 3.432 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[1] ; CLOCK_27[0] ; 3.575 ; 3.575 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[2] ; CLOCK_27[0] ; 3.241 ; 3.241 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[3] ; CLOCK_27[0] ; 3.271 ; 3.271 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[4] ; CLOCK_27[0] ; 3.731 ; 3.731 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[5] ; CLOCK_27[0] ; 2.601 ; 2.601 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[6] ; CLOCK_27[0] ; 3.017 ; 3.017 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[7] ; CLOCK_27[0] ; 2.657 ; 2.657 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[8] ; CLOCK_27[0] ; 2.807 ; 2.807 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[9] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[10] ; CLOCK_27[0] ; 2.971 ; 2.971 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[11] ; CLOCK_27[0] ; 3.104 ; 3.104 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[12] ; CLOCK_27[0] ; 3.093 ; 3.093 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[13] ; CLOCK_27[0] ; 3.203 ; 3.203 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[14] ; CLOCK_27[0] ; 3.481 ; 3.481 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[15] ; CLOCK_27[0] ; 3.486 ; 3.486 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[16] ; CLOCK_27[0] ; 3.553 ; 3.553 ; Rise ; p1|altpll_component|pll|clk[0] ;; SRAM_ADDR[17] ; CLOCK_27[0] ; 3.402 ; 3.402 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[*] ; CLOCK_27[0] ; 2.426 ; 2.426 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[0] ; CLOCK_27[0] ; 3.138 ; 3.138 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[1] ; CLOCK_27[0] ; 2.842 ; 2.842 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[2] ; CLOCK_27[0] ; 3.006 ; 3.006 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_B[3] ; CLOCK_27[0] ; 2.426 ; 2.426 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[*] ; CLOCK_27[0] ; 2.919 ; 2.919 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[0] ; CLOCK_27[0] ; 3.005 ; 3.005 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[1] ; CLOCK_27[0] ; 3.082 ; 3.082 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[2] ; CLOCK_27[0] ; 2.919 ; 2.919 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_G[3] ; CLOCK_27[0] ; 3.329 ; 3.329 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_HS ; CLOCK_27[0] ; 2.350 ; 2.350 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[*] ; CLOCK_27[0] ; 3.000 ; 3.000 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[0] ; CLOCK_27[0] ; 3.183 ; 3.183 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[1] ; CLOCK_27[0] ; 3.286 ; 3.286 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[2] ; CLOCK_27[0] ; 3.196 ; 3.196 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_R[3] ; CLOCK_27[0] ; 3.000 ; 3.000 ; Rise ; p1|altpll_component|pll|clk[0] ;; VGA_VS ; CLOCK_27[0] ; 2.397 ; 2.397 ; Rise ; p1|altpll_component|pll|clk[0] ;; AUD_XCK ; CLOCK_27[0] ; 1.117 ; ; Rise ; p1|altpll_component|pll|clk[1] ;; AUD_XCK ; CLOCK_27[0] ; ; 1.117 ; Fall ; p1|altpll_component|pll|clk[1] ;; DRAM_ADDR[*] ; CLOCK_50 ; 1.825 ; 1.825 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[0] ; CLOCK_50 ; 2.133 ; 2.133 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[1] ; CLOCK_50 ; 2.150 ; 2.150 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[2] ; CLOCK_50 ; 2.195 ; 2.195 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[3] ; CLOCK_50 ; 2.149 ; 2.149 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[4] ; CLOCK_50 ; 1.954 ; 1.954 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[5] ; CLOCK_50 ; 1.967 ; 1.967 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[6] ; CLOCK_50 ; 1.944 ; 1.944 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[7] ; CLOCK_50 ; 1.938 ; 1.938 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[8] ; CLOCK_50 ; 1.827 ; 1.827 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[9] ; CLOCK_50 ; 1.825 ; 1.825 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[10] ; CLOCK_50 ; 2.132 ; 2.132 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_ADDR[11] ; CLOCK_50 ; 1.942 ; 1.942 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_0 ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_BA_1 ; CLOCK_50 ; 2.341 ; 2.341 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CAS_N ; CLOCK_50 ; 2.115 ; 2.115 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CKE ; CLOCK_50 ; 2.113 ; 2.113 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CS_N ; CLOCK_50 ; 2.215 ; 2.215 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[*] ; CLOCK_50 ; 1.916 ; 1.916 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[0] ; CLOCK_50 ; 2.200 ; 2.200 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[1] ; CLOCK_50 ; 2.200 ; 2.200 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[2] ; CLOCK_50 ; 2.068 ; 2.068 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[3] ; CLOCK_50 ; 2.068 ; 2.068 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[4] ; CLOCK_50 ; 2.207 ; 2.207 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[5] ; CLOCK_50 ; 2.177 ; 2.177 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[6] ; CLOCK_50 ; 2.217 ; 2.217 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[7] ; CLOCK_50 ; 2.150 ; 2.150 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[8] ; CLOCK_50 ; 1.916 ; 1.916 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[9] ; CLOCK_50 ; 2.162 ; 2.162 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[10] ; CLOCK_50 ; 2.071 ; 2.071 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[11] ; CLOCK_50 ; 2.289 ; 2.289 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[12] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[13] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[14] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_DQ[15] ; CLOCK_50 ; 2.203 ; 2.203 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_LDQM ; CLOCK_50 ; 2.586 ; 2.586 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_RAS_N ; CLOCK_50 ; 2.028 ; 2.028 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_UDQM ; CLOCK_50 ; 2.647 ; 2.647 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_WE_N ; CLOCK_50 ; 1.844 ; 1.844 ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; DRAM_CLK ; CLOCK_50 ; -0.119 ; ; Rise ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; DRAM_CLK ; CLOCK_50 ; ; -0.119 ; Fall ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;+----------------+---------------------------------+--------+--------+------------+----------------------------------------------++--------------------------------------------------------------+; Progagation Delay ;+------------+-------------+--------+--------+--------+--------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+--------+--------+--------+--------+; SW[0] ; AUD_DACDAT ; 11.020 ; 11.758 ; 11.758 ; 11.020 ;; SW[1] ; AUD_DACDAT ; ; 11.398 ; 11.398 ; ;+------------+-------------+--------+--------+--------+--------++----------------------------------------------------------+; Minimum Progagation Delay ;+------------+-------------+-------+-------+-------+-------+; Input Port ; Output Port ; RR ; RF ; FR ; FF ;+------------+-------------+-------+-------+-------+-------+; SW[0] ; AUD_DACDAT ; 4.931 ; 4.802 ; 4.802 ; 4.931 ;; SW[1] ; AUD_DACDAT ; ; 4.633 ; 4.633 ; ;+------------+-------------+-------+-------+-------+-------++-----------------------------------------------------------------------------------------------------------------------------------------+; Setup Transfers ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+; AUDIO_DAC:u11|LRCK_1X ; AUDIO_DAC:u11|LRCK_1X ; 0 ; 0 ; 0 ; 54 ;; AUDIO_DAC:u11|LRCK_4X ; AUDIO_DAC:u11|LRCK_2X ; 0 ; 0 ; 16 ; 0 ;; AUDIO_DAC:u11|LRCK_4X ; AUDIO_DAC:u11|LRCK_4X ; 0 ; 16 ; 0 ; 737 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_4X ; 16 ; 0 ; 0 ; 0 ;; AUDIO_DAC:u11|oAUD_BCK ; AUDIO_DAC:u11|oAUD_BCK ; 0 ; 0 ; 0 ; 13 ;; AUDIO_DAC:u11|LRCK_4X ; CLOCK_50 ; 0 ; 22 ; 0 ; 0 ;; CLOCK_50 ; CLOCK_50 ; 15981 ; 0 ; 0 ; 0 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;; TCK ; CLOCK_50 ; 3 ; 1 ; 0 ; 0 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; CLOCK_50 ; 18 ; 0 ; 0 ; 0 ;; USB_JTAG:u1|mTCK ; CLOCK_50 ; 18 ; 0 ; 0 ; 0 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 383 ; 0 ; 0 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[0] ; 887 ; 0 ; 0 ; 0 ;; p1|altpll_component|pll|clk[0] ; p1|altpll_component|pll|clk[0] ; 3996632 ; 0 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_1X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_2X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_4X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|oAUD_BCK ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; p1|altpll_component|pll|clk[1] ; p1|altpll_component|pll|clk[1] ; 339 ; 0 ; 0 ; 0 ;; CLOCK_50 ; TCK ; 94 ; 0 ; 0 ; 0 ;; TCK ; TCK ; 16 ; 0 ; 0 ; 0 ;; CLOCK_50 ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 198 ; 0 ; 0 ; 0 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 1440 ; 0 ; 0 ; 0 ;; USB_JTAG:u1|mTCK ; USB_JTAG:u1|mTCK ; 46 ; 0 ; 0 ; 0 ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------------------------------------------------------------------------+; Hold Transfers ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+; AUDIO_DAC:u11|LRCK_1X ; AUDIO_DAC:u11|LRCK_1X ; 0 ; 0 ; 0 ; 54 ;; AUDIO_DAC:u11|LRCK_4X ; AUDIO_DAC:u11|LRCK_2X ; 0 ; 0 ; 16 ; 0 ;; AUDIO_DAC:u11|LRCK_4X ; AUDIO_DAC:u11|LRCK_4X ; 0 ; 16 ; 0 ; 737 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_4X ; 16 ; 0 ; 0 ; 0 ;; AUDIO_DAC:u11|oAUD_BCK ; AUDIO_DAC:u11|oAUD_BCK ; 0 ; 0 ; 0 ; 13 ;; AUDIO_DAC:u11|LRCK_4X ; CLOCK_50 ; 0 ; 22 ; 0 ; 0 ;; CLOCK_50 ; CLOCK_50 ; 15981 ; 0 ; 0 ; 0 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ;; TCK ; CLOCK_50 ; 3 ; 1 ; 0 ; 0 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; CLOCK_50 ; 18 ; 0 ; 0 ; 0 ;; USB_JTAG:u1|mTCK ; CLOCK_50 ; 18 ; 0 ; 0 ; 0 ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; I2C_AV_Config:u10|mI2C_CTRL_CLK ; 383 ; 0 ; 0 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[0] ; 887 ; 0 ; 0 ; 0 ;; p1|altpll_component|pll|clk[0] ; p1|altpll_component|pll|clk[0] ; 3996632 ; 0 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_1X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_2X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|LRCK_4X ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; AUDIO_DAC:u11|oAUD_BCK ; p1|altpll_component|pll|clk[1] ; 1 ; 1 ; 0 ; 0 ;; p1|altpll_component|pll|clk[1] ; p1|altpll_component|pll|clk[1] ; 339 ; 0 ; 0 ; 0 ;; CLOCK_50 ; TCK ; 94 ; 0 ; 0 ; 0 ;; TCK ; TCK ; 16 ; 0 ; 0 ; 0 ;; CLOCK_50 ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 198 ; 0 ; 0 ; 0 ;; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ; 1440 ; 0 ; 0 ; 0 ;; USB_JTAG:u1|mTCK ; USB_JTAG:u1|mTCK ; 46 ; 0 ; 0 ; 0 ;+----------------------------------------------+----------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------------------------+; Recovery Transfers ;+------------+--------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+--------------------------------+----------+----------+----------+----------+; CLOCK_50 ; AUDIO_DAC:u11|LRCK_1X ; 0 ; 0 ; 6 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_2X ; 0 ; 0 ; 16 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_4X ; 16 ; 0 ; 22 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|oAUD_BCK ; 0 ; 0 ; 7 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[0] ; 73 ; 0 ; 0 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[1] ; 31 ; 0 ; 0 ; 0 ;+------------+--------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------------------------+; Removal Transfers ;+------------+--------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+--------------------------------+----------+----------+----------+----------+; CLOCK_50 ; AUDIO_DAC:u11|LRCK_1X ; 0 ; 0 ; 6 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_2X ; 0 ; 0 ; 16 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|LRCK_4X ; 16 ; 0 ; 22 ; 0 ;; CLOCK_50 ; AUDIO_DAC:u11|oAUD_BCK ; 0 ; 0 ; 7 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[0] ; 73 ; 0 ; 0 ; 0 ;; CLOCK_50 ; p1|altpll_component|pll|clk[1] ; 31 ; 0 ; 0 ; 0 ;+------------+--------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.---------------; Report TCCS ;---------------No dedicated SERDES Transmitter circuitry present in device or used in design.---------------; Report RSKM ;---------------No dedicated SERDES Receiver circuitry present in device or used in design.+------------------------------------------------+; Unconstrained Paths ;+---------------------------------+-------+------+; Property ; Setup ; Hold ;+---------------------------------+-------+------+; Illegal Clocks ; 0 ; 0 ;; Unconstrained Clocks ; 0 ; 0 ;; Unconstrained Input Ports ; 48 ; 48 ;; Unconstrained Input Port Paths ; 871 ; 871 ;; Unconstrained Output Ports ; 175 ; 175 ;; Unconstrained Output Port Paths ; 793 ; 793 ;+---------------------------------+-------+------++------------------------------------+; TimeQuest Timing Analyzer Messages ;+------------------------------------+Info: *******************************************************************Info: Running Quartus II TimeQuest Timing AnalyzerInfo: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web EditionInfo: Processing started: Sun Oct 11 12:25:10 2009Info: Command: quartus_sta CII_Starter_USB_API -c CII_Starter_USB_APIInfo: qsta_default_script.tcl version: #1Critical Warning: Synopsys Design Constraints File file not found: 'CII_Starter_USB_API.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Info: No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"Info: Deriving PLL ClocksInfo: create_clock -period 37.037 -waveform {0.000 18.518} -name CLOCK_27[0] CLOCK_27[0]Info: create_clock -period 20.000 -waveform {0.000 10.000} -name CLOCK_50 CLOCK_50Info: create_generated_clock -source {u3|u1|sdram_pll1|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {u3|u1|sdram_pll1|altpll_component|pll|clk[0]} {u3|u1|sdram_pll1|altpll_component|pll|clk[0]}Info: create_generated_clock -source {u3|u1|sdram_pll1|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {u3|u1|sdram_pll1|altpll_component|pll|clk[2]} {u3|u1|sdram_pll1|altpll_component|pll|clk[2]}Info: create_generated_clock -source {p1|altpll_component|pll|inclk[0]} -divide_by 15 -multiply_by 14 -duty_cycle 50.00 -name {p1|altpll_component|pll|clk[0]} {p1|altpll_component|pll|clk[0]}Info: create_generated_clock -source {p1|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 2 -duty_cycle 50.00 -name {p1|altpll_component|pll|clk[1]} {p1|altpll_component|pll|clk[1]}Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"Info: Deriving ClocksInfo: create_clock -period 1.000 -name USB_JTAG:u1|mTCK USB_JTAG:u1|mTCKInfo: create_clock -period 1.000 -name TCK TCKInfo: create_clock -period 1.000 -name AUDIO_DAC:u11|LRCK_4X AUDIO_DAC:u11|LRCK_4XInfo: create_clock -period 1.000 -name I2C_AV_Config:u10|mI2C_CTRL_CLK I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: create_clock -period 1.000 -name AUDIO_DAC:u11|LRCK_1X AUDIO_DAC:u11|LRCK_1XInfo: create_clock -period 1.000 -name AUDIO_DAC:u11|oAUD_BCK AUDIO_DAC:u11|oAUD_BCKInfo: create_clock -period 1.000 -name AUDIO_DAC:u11|LRCK_2X AUDIO_DAC:u11|LRCK_2XInfo: Analyzing Slow ModelCritical Warning: Timing requirements not metInfo: Worst-case setup slack is -8.207Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -8.207 -93.462 p1|altpll_component|pll|clk[0]Info: -4.280 -9.429 TCKInfo: -3.812 -101.895 AUDIO_DAC:u11|LRCK_4XInfo: -2.906 -72.732 I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: -1.570 -12.001 CLOCK_50Info: -1.477 -7.476 AUDIO_DAC:u11|LRCK_1XInfo: -1.281 -12.787 AUDIO_DAC:u11|LRCK_2XInfo: -1.098 -9.913 USB_JTAG:u1|mTCKInfo: -0.490 -0.861 AUDIO_DAC:u11|oAUD_BCKInfo: -0.349 -1.380 p1|altpll_component|pll|clk[1]Info: 12.201 0.000 u3|u1|sdram_pll1|altpll_component|pll|clk[0]Info: Worst-case hold slack is -2.702Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -2.702 -29.887 CLOCK_50Info: 0.092 0.000 p1|altpll_component|pll|clk[1]Info: 0.445 0.000 AUDIO_DAC:u11|LRCK_1XInfo: 0.445 0.000 AUDIO_DAC:u11|LRCK_4XInfo: 0.445 0.000 AUDIO_DAC:u11|oAUD_BCKInfo: 0.445 0.000 I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: 0.445 0.000 TCKInfo: 0.445 0.000 USB_JTAG:u1|mTCKInfo: 0.445 0.000 p1|altpll_component|pll|clk[0]Info: 0.445 0.000 u3|u1|sdram_pll1|altpll_component|pll|clk[0]Info: 1.325 0.000 AUDIO_DAC:u11|LRCK_2XInfo: Worst-case recovery slack is -6.299Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -6.299 -449.521 p1|altpll_component|pll|clk[0]Info: -5.585 -172.713 p1|altpll_component|pll|clk[1]Info: -3.362 -112.147 AUDIO_DAC:u11|LRCK_4XInfo: -3.234 -49.977 AUDIO_DAC:u11|LRCK_2XInfo: -2.733 -16.398 AUDIO_DAC:u11|LRCK_1XInfo: -2.710 -18.970 AUDIO_DAC:u11|oAUD_BCKInfo: Worst-case removal slack is 2.977Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: 2.977 0.000 AUDIO_DAC:u11|LRCK_4XInfo: 3.462 0.000 AUDIO_DAC:u11|oAUD_BCKInfo: 3.485 0.000 AUDIO_DAC:u11|LRCK_1XInfo: 3.686 0.000 AUDIO_DAC:u11|LRCK_2XInfo: 5.306 0.000 p1|altpll_component|pll|clk[1]Info: 5.800 0.000 p1|altpll_component|pll|clk[0]Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.Info: The selected device family is not supported by the report_metastability command.Info: Analyzing Fast ModelInfo: Started post-fitting delay annotationWarning: Found 256 output pins without output pin load capacitance assignmentInfo: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "UART_TXD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_LDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_UDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_RAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_BA_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_BA_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_RST_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_UB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_LB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "TDO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2C_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_HS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_VS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_ADCLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_DACLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_DACDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_XCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_DAT3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_CMD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_DAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2C_SDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_BCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyCritical Warning: Timing requirements not metInfo: Worst-case setup slack is -4.123Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -4.123 -47.614 p1|altpll_component|pll|clk[0]Info: -1.188 -1.216 TCKInfo: -0.857 -22.460 AUDIO_DAC:u11|LRCK_4XInfo: -0.493 -1.956 p1|altpll_component|pll|clk[1]Info: -0.456 -5.870 I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: -0.221 -0.692 AUDIO_DAC:u11|LRCK_2XInfo: -0.193 -0.496 CLOCK_50Info: 0.029 0.000 AUDIO_DAC:u11|LRCK_1XInfo: 0.071 0.000 USB_JTAG:u1|mTCKInfo: 0.418 0.000 AUDIO_DAC:u11|oAUD_BCKInfo: 15.989 0.000 u3|u1|sdram_pll1|altpll_component|pll|clk[0]Info: Worst-case hold slack is -1.811Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -1.811 -29.851 CLOCK_50Info: 0.148 0.000 TCKInfo: 0.215 0.000 AUDIO_DAC:u11|LRCK_1XInfo: 0.215 0.000 AUDIO_DAC:u11|LRCK_4XInfo: 0.215 0.000 AUDIO_DAC:u11|oAUD_BCKInfo: 0.215 0.000 I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: 0.215 0.000 USB_JTAG:u1|mTCKInfo: 0.215 0.000 p1|altpll_component|pll|clk[0]Info: 0.215 0.000 p1|altpll_component|pll|clk[1]Info: 0.215 0.000 u3|u1|sdram_pll1|altpll_component|pll|clk[0]Info: 0.805 0.000 AUDIO_DAC:u11|LRCK_2XInfo: Worst-case recovery slack is -3.677Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -3.677 -264.018 p1|altpll_component|pll|clk[0]Info: -3.379 -104.241 p1|altpll_component|pll|clk[1]Info: -1.334 -39.561 AUDIO_DAC:u11|LRCK_4XInfo: -1.264 -19.520 AUDIO_DAC:u11|LRCK_2XInfo: -1.079 -6.474 AUDIO_DAC:u11|LRCK_1XInfo: -1.071 -7.497 AUDIO_DAC:u11|oAUD_BCKInfo: Worst-case removal slack is 1.458Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: 1.458 0.000 AUDIO_DAC:u11|LRCK_4XInfo: 1.951 0.000 AUDIO_DAC:u11|oAUD_BCKInfo: 1.959 0.000 AUDIO_DAC:u11|LRCK_1XInfo: 2.025 0.000 AUDIO_DAC:u11|LRCK_2XInfo: 3.242 0.000 p1|altpll_component|pll|clk[1]Info: 3.466 0.000 p1|altpll_component|pll|clk[0]Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.Info: The selected device family is not supported by the report_metastability command.Info: Design is not fully constrained for setup requirementsInfo: Design is not fully constrained for hold requirementsInfo: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 6 warningsInfo: Peak virtual memory: 177 megabytesInfo: Processing ended: Sun Oct 11 12:25:21 2009Info: Elapsed time: 00:00:11Info: Total CPU time (on all processors): 00:00:10