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https://opencores.org/ocsvn/z80soc/z80soc/trunk
Subversion Repositories z80soc
[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [memoryCores/] [ram24k.xise] - Rev 42
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ram24k.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ram24k.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Device" xil_pn:value="xc3s500e"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|ram24k"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ram24k"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ram24k"/>
<property xil_pn:name="Package" xil_pn:value="fg320"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries/>
<partitions>
<partition xil_pn:name="/ram24k"/>
</partitions>
</project>
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