Subversion Repositories z80soc

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Z80SoC.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Z80SOC_TOP.bld"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Z80SOC_TOP.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Z80SOC_TOP.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Z80SOC_TOP.ncd" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Z80SOC_TOP.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="Z80SOC_TOP.ngd"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Z80SOC_TOP.ngr"/>
    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="Z80SOC_TOP.pad"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="Z80SOC_TOP.par" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="Z80SOC_TOP.pcf" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Z80SOC_TOP.prj"/>
    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="Z80SOC_TOP.ptwx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Z80SOC_TOP.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Z80SOC_TOP.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="Z80SOC_TOP.twr" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="Z80SOC_TOP.twx" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Z80SOC_TOP.unroutes" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="Z80SOC_TOP.ut" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:fileType="FILE_XPI" xil_pn:name="Z80SOC_TOP.xpi"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Z80SOC_TOP.xst"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="Z80SOC_TOP_envsettings.html"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="Z80SOC_TOP_guide.ncd" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Z80SOC_TOP_map.map" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Z80SOC_TOP_map.mrp" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Z80SOC_TOP_map.ncd" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="Z80SOC_TOP_map.ngm" xil_pn:subbranch="Map"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Z80SOC_TOP_map.xrpt"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Z80SOC_TOP_ngdbuild.xrpt"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="Z80SOC_TOP_pad.csv" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="Z80SOC_TOP_pad.txt" xil_pn:subbranch="Par"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Z80SOC_TOP_par.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="Z80SOC_TOP_summary.html"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="Z80SOC_TOP_summary.xml"/>
    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Z80SOC_TOP_usage.xml"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Z80SOC_TOP_vhdl.prj"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Z80SOC_TOP_xst.xrpt"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="z80soc_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="z80soc_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="z80soc_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6013518690185681363" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6976370431582440281" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7533711598888912815" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1289342240" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1341817881576410205" xil_pn:start_ts="1289342240">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1290477028" xil_pn:in_ck="-792038860299931950" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-6291703755966252302" xil_pn:start_ts="1290476968">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="Z80SOC_TOP.lso"/>
      <outfile xil_pn:name="Z80SOC_TOP.ngc"/>
      <outfile xil_pn:name="Z80SOC_TOP.ngr"/>
      <outfile xil_pn:name="Z80SOC_TOP.prj"/>
      <outfile xil_pn:name="Z80SOC_TOP.stx"/>
      <outfile xil_pn:name="Z80SOC_TOP.syr"/>
      <outfile xil_pn:name="Z80SOC_TOP.xst"/>
      <outfile xil_pn:name="Z80SOC_TOP_vhdl.prj"/>
      <outfile xil_pn:name="Z80SOC_TOP_xst.xrpt"/>
      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
    <transform xil_pn:end_ts="1289342298" xil_pn:in_ck="5743158646957779" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-6753211658516660378" xil_pn:start_ts="1289342298">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1290477033" xil_pn:in_ck="4623013076741857010" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1050951703924274100" xil_pn:start_ts="1290477028">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="Z80SOC_TOP.bld"/>
      <outfile xil_pn:name="Z80SOC_TOP.ngd"/>
      <outfile xil_pn:name="Z80SOC_TOP_ngdbuild.xrpt"/>
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1290477042" xil_pn:in_ck="4624544655727121459" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1290477033">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="Z80SOC_TOP.pcf"/>
      <outfile xil_pn:name="Z80SOC_TOP_map.map"/>
      <outfile xil_pn:name="Z80SOC_TOP_map.mrp"/>
      <outfile xil_pn:name="Z80SOC_TOP_map.ncd"/>
      <outfile xil_pn:name="Z80SOC_TOP_map.ngm"/>
      <outfile xil_pn:name="Z80SOC_TOP_map.xrpt"/>
      <outfile xil_pn:name="Z80SOC_TOP_summary.xml"/>
      <outfile xil_pn:name="Z80SOC_TOP_usage.xml"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1290477087" xil_pn:in_ck="-2880618293868837236" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1290477042">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="Z80SOC_TOP.ncd"/>
      <outfile xil_pn:name="Z80SOC_TOP.pad"/>
      <outfile xil_pn:name="Z80SOC_TOP.par"/>
      <outfile xil_pn:name="Z80SOC_TOP.ptwx"/>
      <outfile xil_pn:name="Z80SOC_TOP.unroutes"/>
      <outfile xil_pn:name="Z80SOC_TOP.xpi"/>
      <outfile xil_pn:name="Z80SOC_TOP_pad.csv"/>
      <outfile xil_pn:name="Z80SOC_TOP_pad.txt"/>
      <outfile xil_pn:name="Z80SOC_TOP_par.xrpt"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
    </transform>
    <transform xil_pn:end_ts="1290477114" xil_pn:in_ck="-4817296883179899684" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1290477087">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="Z80SOC_TOP.ut"/>
      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="z80soc_top.bgn"/>
      <outfile xil_pn:name="z80soc_top.bit"/>
      <outfile xil_pn:name="z80soc_top.drc"/>
    </transform>
    <transform xil_pn:end_ts="1290474439" xil_pn:in_ck="4083884647487168390" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1290474437">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="InputChanged"/>
    </transform>
    <transform xil_pn:end_ts="1290477087" xil_pn:in_ck="4422376229672214191" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1290477082">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="Z80SOC_TOP.twr"/>
      <outfile xil_pn:name="Z80SOC_TOP.twx"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
    </transform>
  </transforms>

</generated_project>