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[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [rom.cgp] - Rev 42

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# Date: Sun Oct 31 21:29:54 2010

SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/

# CRC: 940d4b1f

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