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--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INIT_FILE="../ROMdata/lat9-08.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END


-- Copyright (C) 1991-2013 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.


FUNCTION altsyncram_36o1 (address_a[10..0], address_b[10..0], clock0, clock1, clocken1, data_a[7..0], data_b[7..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);

--synthesis_resources = M4K 4 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_h1o1
( 
        address_a[10..0]        :       input;
        address_b[10..0]        :       input;
        clock0  :       input;
        clock1  :       input;
        data_a[7..0]    :       input;
        q_b[7..0]       :       output;
        wren_a  :       input;
) 
VARIABLE 
        altsyncram1 : altsyncram_36o1;

BEGIN 
        altsyncram1.address_a[] = address_b[];
        altsyncram1.address_b[] = address_a[];
        altsyncram1.clock0 = clock1;
        altsyncram1.clock1 = clock0;
        altsyncram1.clocken1 = wren_a;
        altsyncram1.data_a[] = B"11111111";
        altsyncram1.data_b[] = data_a[];
        altsyncram1.wren_a = B"0";
        altsyncram1.wren_b = wren_a;
        q_b[] = altsyncram1.q_a[];
END;
--VALID FILE