Subversion Repositories z80soc

|z80soc
CLOCK_27 => ~NO_FANOUT~
CLOCK_50 => clk_div:clkdiv_inst.clock_in_50Mhz
CLOCK_50 => \random:rand_temp[0].CLK
CLOCK_50 => \random:rand_temp[1].CLK
CLOCK_50 => \random:rand_temp[2].CLK
CLOCK_50 => \random:rand_temp[3].CLK
CLOCK_50 => \random:rand_temp[4].CLK
CLOCK_50 => \random:rand_temp[5].CLK
CLOCK_50 => \random:rand_temp[6].CLK
CLOCK_50 => \random:rand_temp[7].CLK
CLOCK_50 => \random:rand_temp[8].CLK
CLOCK_50 => \random:rand_temp[9].CLK
CLOCK_50 => \random:rand_temp[10].CLK
CLOCK_50 => \random:rand_temp[11].CLK
CLOCK_50 => \random:rand_temp[12].CLK
CLOCK_50 => \random:rand_temp[13].CLK
CLOCK_50 => \random:rand_temp[14].CLK
CLOCK_50 => \random:rand_temp[15].CLK
CLOCK_50 => ps2_ascii_reg1[0].CLK
CLOCK_50 => ps2_ascii_reg1[1].CLK
CLOCK_50 => ps2_ascii_reg1[2].CLK
CLOCK_50 => ps2_ascii_reg1[3].CLK
CLOCK_50 => ps2_ascii_reg1[4].CLK
CLOCK_50 => ps2_ascii_reg1[5].CLK
CLOCK_50 => ps2_ascii_reg1[6].CLK
CLOCK_50 => ps2_ascii_reg1[7].CLK
CLOCK_50 => ps2_read.CLK
CLOCK_50 => ps2kbd:ps2_kbd_inst.clock
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => DI_CPU[0].DATAA
KEY[1] => DI_CPU[1].DATAA
KEY[2] => DI_CPU[2].DATAA
KEY[3] => DI_CPU[3].DATAA
SW[0] => DI_CPU[0].DATAB
SW[1] => DI_CPU[1].DATAB
SW[2] => DI_CPU[2].DATAB
SW[3] => DI_CPU[3].DATAB
SW[4] => DI_CPU[4].DATAB
SW[5] => DI_CPU[5].DATAB
SW[6] => DI_CPU[6].DATAB
SW[7] => DI_CPU[7].DATAB
SW[8] => Clk_Z80.OUTPUTSELECT
SW[8] => LEDR[8].DATAIN
SW[9] => LEDR[9].DATAIN
SW[9] => T80se:z80_inst.RESET_n
SW[9] => ps2kbd:ps2_kbd_inst.reset
HEX0[0] <= decoder_7seg:DISPHEX0.HEX_DISP[0]
HEX0[1] <= decoder_7seg:DISPHEX0.HEX_DISP[1]
HEX0[2] <= decoder_7seg:DISPHEX0.HEX_DISP[2]
HEX0[3] <= decoder_7seg:DISPHEX0.HEX_DISP[3]
HEX0[4] <= decoder_7seg:DISPHEX0.HEX_DISP[4]
HEX0[5] <= decoder_7seg:DISPHEX0.HEX_DISP[5]
HEX0[6] <= decoder_7seg:DISPHEX0.HEX_DISP[6]
HEX1[0] <= decoder_7seg:DISPHEX1.HEX_DISP[0]
HEX1[1] <= decoder_7seg:DISPHEX1.HEX_DISP[1]
HEX1[2] <= decoder_7seg:DISPHEX1.HEX_DISP[2]
HEX1[3] <= decoder_7seg:DISPHEX1.HEX_DISP[3]
HEX1[4] <= decoder_7seg:DISPHEX1.HEX_DISP[4]
HEX1[5] <= decoder_7seg:DISPHEX1.HEX_DISP[5]
HEX1[6] <= decoder_7seg:DISPHEX1.HEX_DISP[6]
HEX2[0] <= decoder_7seg:DISPHEX2.HEX_DISP[0]
HEX2[1] <= decoder_7seg:DISPHEX2.HEX_DISP[1]
HEX2[2] <= decoder_7seg:DISPHEX2.HEX_DISP[2]
HEX2[3] <= decoder_7seg:DISPHEX2.HEX_DISP[3]
HEX2[4] <= decoder_7seg:DISPHEX2.HEX_DISP[4]
HEX2[5] <= decoder_7seg:DISPHEX2.HEX_DISP[5]
HEX2[6] <= decoder_7seg:DISPHEX2.HEX_DISP[6]
HEX3[0] <= decoder_7seg:DISPHEX3.HEX_DISP[0]
HEX3[1] <= decoder_7seg:DISPHEX3.HEX_DISP[1]
HEX3[2] <= decoder_7seg:DISPHEX3.HEX_DISP[2]
HEX3[3] <= decoder_7seg:DISPHEX3.HEX_DISP[3]
HEX3[4] <= decoder_7seg:DISPHEX3.HEX_DISP[4]
HEX3[5] <= decoder_7seg:DISPHEX3.HEX_DISP[5]
HEX3[6] <= decoder_7seg:DISPHEX3.HEX_DISP[6]
LEDG[0] <= \pinout_process:LEDG_sig[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= \pinout_process:LEDG_sig[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= \pinout_process:LEDG_sig[2].DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= \pinout_process:LEDG_sig[3].DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= \pinout_process:LEDG_sig[4].DB_MAX_OUTPUT_PORT_TYPE
LEDG[5] <= \pinout_process:LEDG_sig[5].DB_MAX_OUTPUT_PORT_TYPE
LEDG[6] <= \pinout_process:LEDG_sig[6].DB_MAX_OUTPUT_PORT_TYPE
LEDG[7] <= \pinout_process:LEDG_sig[7].DB_MAX_OUTPUT_PORT_TYPE
LEDR[0] <= \pinout_process:LEDR_sig[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= \pinout_process:LEDR_sig[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= \pinout_process:LEDR_sig[2].DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= \pinout_process:LEDR_sig[3].DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= \pinout_process:LEDR_sig[4].DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= \pinout_process:LEDR_sig[5].DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= \pinout_process:LEDR_sig[6].DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= \pinout_process:LEDR_sig[7].DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= SW[8].DB_MAX_OUTPUT_PORT_TYPE
LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE
UART_TXD <= UART_TXD.DB_MAX_OUTPUT_PORT_TYPE
UART_RXD => ~NO_FANOUT~
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <> DRAM_DQ[0]
DRAM_DQ[1] <> DRAM_DQ[1]
DRAM_DQ[2] <> DRAM_DQ[2]
DRAM_DQ[3] <> DRAM_DQ[3]
DRAM_DQ[4] <> DRAM_DQ[4]
DRAM_DQ[5] <> DRAM_DQ[5]
DRAM_DQ[6] <> DRAM_DQ[6]
DRAM_DQ[7] <> DRAM_DQ[7]
DRAM_DQ[8] <> DRAM_DQ[8]
DRAM_DQ[9] <> DRAM_DQ[9]
DRAM_DQ[10] <> DRAM_DQ[10]
DRAM_DQ[11] <> DRAM_DQ[11]
DRAM_DQ[12] <> DRAM_DQ[12]
DRAM_DQ[13] <> DRAM_DQ[13]
DRAM_DQ[14] <> DRAM_DQ[14]
DRAM_DQ[15] <> DRAM_DQ[15]
DRAM_ADDR[0] <= <GND>
DRAM_ADDR[1] <= <GND>
DRAM_ADDR[2] <= <GND>
DRAM_ADDR[3] <= <GND>
DRAM_ADDR[4] <= <GND>
DRAM_ADDR[5] <= <GND>
DRAM_ADDR[6] <= <GND>
DRAM_ADDR[7] <= <GND>
DRAM_ADDR[8] <= <GND>
DRAM_ADDR[9] <= <GND>
DRAM_ADDR[10] <= <GND>
DRAM_ADDR[11] <= <GND>
DRAM_LDQM <= <GND>
DRAM_UDQM <= <GND>
DRAM_WE_N <= <VCC>
DRAM_CAS_N <= <VCC>
DRAM_RAS_N <= <VCC>
DRAM_CS_N <= <VCC>
DRAM_BA_0 <= <GND>
DRAM_BA_1 <= <GND>
DRAM_CLK <= <GND>
DRAM_CKE <= <GND>
FL_DQ[0] <> FL_DQ[0]
FL_DQ[1] <> FL_DQ[1]
FL_DQ[2] <> FL_DQ[2]
FL_DQ[3] <> FL_DQ[3]
FL_DQ[4] <> FL_DQ[4]
FL_DQ[5] <> FL_DQ[5]
FL_DQ[6] <> FL_DQ[6]
FL_DQ[7] <> FL_DQ[7]
FL_ADDR[0] <= <GND>
FL_ADDR[1] <= <GND>
FL_ADDR[2] <= <GND>
FL_ADDR[3] <= <GND>
FL_ADDR[4] <= <GND>
FL_ADDR[5] <= <GND>
FL_ADDR[6] <= <GND>
FL_ADDR[7] <= <GND>
FL_ADDR[8] <= <GND>
FL_ADDR[9] <= <GND>
FL_ADDR[10] <= <GND>
FL_ADDR[11] <= <GND>
FL_ADDR[12] <= <GND>
FL_ADDR[13] <= <GND>
FL_ADDR[14] <= <GND>
FL_ADDR[15] <= <GND>
FL_ADDR[16] <= <GND>
FL_ADDR[17] <= <GND>
FL_ADDR[18] <= <GND>
FL_ADDR[19] <= <GND>
FL_ADDR[20] <= <GND>
FL_ADDR[21] <= <GND>
FL_WE_N <= <VCC>
FL_RST_N <= <GND>
FL_OE_N <= <VCC>
FL_CE_N <= <VCC>
SRAM_DQ[0] <> SRAM_DQ[0]
SRAM_DQ[1] <> SRAM_DQ[1]
SRAM_DQ[2] <> SRAM_DQ[2]
SRAM_DQ[3] <> SRAM_DQ[3]
SRAM_DQ[4] <> SRAM_DQ[4]
SRAM_DQ[5] <> SRAM_DQ[5]
SRAM_DQ[6] <> SRAM_DQ[6]
SRAM_DQ[7] <> SRAM_DQ[7]
SRAM_DQ[8] <> SRAM_DQ[8]
SRAM_DQ[8] <> SRAM_DQ[8]
SRAM_DQ[9] <> SRAM_DQ[9]
SRAM_DQ[9] <> SRAM_DQ[9]
SRAM_DQ[10] <> SRAM_DQ[10]
SRAM_DQ[10] <> SRAM_DQ[10]
SRAM_DQ[11] <> SRAM_DQ[11]
SRAM_DQ[11] <> SRAM_DQ[11]
SRAM_DQ[12] <> SRAM_DQ[12]
SRAM_DQ[12] <> SRAM_DQ[12]
SRAM_DQ[13] <> SRAM_DQ[13]
SRAM_DQ[13] <> SRAM_DQ[13]
SRAM_DQ[14] <> SRAM_DQ[14]
SRAM_DQ[14] <> SRAM_DQ[14]
SRAM_DQ[15] <> SRAM_DQ[15]
SRAM_DQ[15] <> SRAM_DQ[15]
SRAM_ADDR[0] <= T80se:z80_inst.A[0]
SRAM_ADDR[1] <= T80se:z80_inst.A[1]
SRAM_ADDR[2] <= T80se:z80_inst.A[2]
SRAM_ADDR[3] <= T80se:z80_inst.A[3]
SRAM_ADDR[4] <= T80se:z80_inst.A[4]
SRAM_ADDR[5] <= T80se:z80_inst.A[5]
SRAM_ADDR[6] <= T80se:z80_inst.A[6]
SRAM_ADDR[7] <= T80se:z80_inst.A[7]
SRAM_ADDR[8] <= T80se:z80_inst.A[8]
SRAM_ADDR[9] <= T80se:z80_inst.A[9]
SRAM_ADDR[10] <= T80se:z80_inst.A[10]
SRAM_ADDR[11] <= T80se:z80_inst.A[11]
SRAM_ADDR[12] <= T80se:z80_inst.A[12]
SRAM_ADDR[13] <= T80se:z80_inst.A[13]
SRAM_ADDR[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[16] <= <GND>
SRAM_ADDR[17] <= <GND>
SRAM_UB_N <= <VCC>
SRAM_LB_N <= <GND>
SRAM_WE_N <= SRAM_DQ.DB_MAX_OUTPUT_PORT_TYPE
SRAM_CE_N <= <GND>
SRAM_OE_N <= SRAM_OE_N.DB_MAX_OUTPUT_PORT_TYPE
SD_DAT => ~NO_FANOUT~
SD_DAT3 <= SD_DAT3.DB_MAX_OUTPUT_PORT_TYPE
SD_CMD <= SD_CMD.DB_MAX_OUTPUT_PORT_TYPE
SD_CLK <= UART_TXD.DB_MAX_OUTPUT_PORT_TYPE
TDI => ~NO_FANOUT~
TCK => ~NO_FANOUT~
TCS => ~NO_FANOUT~
TDO <= <GND>
I2C_SDAT <> I2C_SDAT
I2C_SCLK <= <GND>
PS2_DAT <> ps2kbd:ps2_kbd_inst.keyboard_data
PS2_CLK <> ps2kbd:ps2_kbd_inst.keyboard_clk
VGA_HS <= video:video_inst.VGA_HS
VGA_VS <= video:video_inst.VGA_VS
VGA_R[0] <= video:video_inst.VGA_R[0]
VGA_R[1] <= video:video_inst.VGA_R[1]
VGA_R[2] <= video:video_inst.VGA_R[2]
VGA_R[3] <= video:video_inst.VGA_R[3]
VGA_G[0] <= video:video_inst.VGA_G[0]
VGA_G[1] <= video:video_inst.VGA_G[1]
VGA_G[2] <= video:video_inst.VGA_G[2]
VGA_G[3] <= video:video_inst.VGA_G[3]
VGA_B[0] <= video:video_inst.VGA_B[0]
VGA_B[1] <= video:video_inst.VGA_B[1]
VGA_B[2] <= video:video_inst.VGA_B[2]
VGA_B[3] <= video:video_inst.VGA_B[3]
AUD_ADCLRCK <> AUD_ADCLRCK
AUD_ADCDAT => ~NO_FANOUT~
AUD_DACLRCK <> AUD_DACLRCK
AUD_DACDAT <= <GND>
AUD_BCLK <> AUD_BCLK
AUD_XCK <= <GND>
GPIO_0[0] <> GPIO_0[0]
GPIO_0[1] <> GPIO_0[1]
GPIO_0[2] <> GPIO_0[2]
GPIO_0[3] <> GPIO_0[3]
GPIO_0[4] <> GPIO_0[4]
GPIO_0[5] <> GPIO_0[5]
GPIO_0[6] <> GPIO_0[6]
GPIO_0[7] <> GPIO_0[7]
GPIO_0[8] <> GPIO_0[8]
GPIO_0[9] <> GPIO_0[9]
GPIO_0[10] <> GPIO_0[10]
GPIO_0[11] <> GPIO_0[11]
GPIO_0[12] <> GPIO_0[12]
GPIO_0[13] <> GPIO_0[13]
GPIO_0[14] <> GPIO_0[14]
GPIO_0[15] <> GPIO_0[15]
GPIO_0[16] <> GPIO_0[16]
GPIO_0[17] <> GPIO_0[17]
GPIO_0[18] <> GPIO_0[18]
GPIO_0[19] <> GPIO_0[19]
GPIO_0[20] <> GPIO_0[20]
GPIO_0[21] <> GPIO_0[21]
GPIO_0[22] <> GPIO_0[22]
GPIO_0[23] <> GPIO_0[23]
GPIO_0[24] <> GPIO_0[24]
GPIO_0[25] <> GPIO_0[25]
GPIO_0[26] <> GPIO_0[26]
GPIO_0[27] <> GPIO_0[27]
GPIO_0[28] <> GPIO_0[28]
GPIO_0[29] <> GPIO_0[29]
GPIO_0[30] <> GPIO_0[30]
GPIO_0[31] <> GPIO_0[31]
GPIO_0[32] <> GPIO_0[32]
GPIO_0[33] <> GPIO_0[33]
GPIO_0[34] <> GPIO_0[34]
GPIO_0[35] <> GPIO_0[35]
GPIO_1[0] <> GPIO_1[0]
GPIO_1[1] <> GPIO_1[1]
GPIO_1[2] <> GPIO_1[2]
GPIO_1[3] <> GPIO_1[3]
GPIO_1[4] <> GPIO_1[4]
GPIO_1[5] <> GPIO_1[5]
GPIO_1[6] <> GPIO_1[6]
GPIO_1[7] <> GPIO_1[7]
GPIO_1[8] <> GPIO_1[8]
GPIO_1[9] <> GPIO_1[9]
GPIO_1[10] <> GPIO_1[10]
GPIO_1[11] <> GPIO_1[11]
GPIO_1[12] <> GPIO_1[12]
GPIO_1[13] <> GPIO_1[13]
GPIO_1[14] <> GPIO_1[14]
GPIO_1[15] <> GPIO_1[15]
GPIO_1[16] <> GPIO_1[16]
GPIO_1[17] <> GPIO_1[17]
GPIO_1[18] <> GPIO_1[18]
GPIO_1[19] <> GPIO_1[19]
GPIO_1[20] <> GPIO_1[20]
GPIO_1[21] <> GPIO_1[21]
GPIO_1[22] <> GPIO_1[22]
GPIO_1[23] <> GPIO_1[23]
GPIO_1[24] <> GPIO_1[24]
GPIO_1[25] <> GPIO_1[25]
GPIO_1[26] <> GPIO_1[26]
GPIO_1[27] <> GPIO_1[27]
GPIO_1[28] <> GPIO_1[28]
GPIO_1[29] <> GPIO_1[29]
GPIO_1[30] <> GPIO_1[30]
GPIO_1[31] <> GPIO_1[31]
GPIO_1[32] <> GPIO_1[32]
GPIO_1[33] <> GPIO_1[33]
GPIO_1[34] <> GPIO_1[34]
GPIO_1[35] <> GPIO_1[35]


|z80soc|T80se:z80_inst
RESET_n => T80:u0.RESET_n
RESET_n => DI_Reg[0].ACLR
RESET_n => DI_Reg[1].ACLR
RESET_n => DI_Reg[2].ACLR
RESET_n => DI_Reg[3].ACLR
RESET_n => DI_Reg[4].ACLR
RESET_n => DI_Reg[5].ACLR
RESET_n => DI_Reg[6].ACLR
RESET_n => DI_Reg[7].ACLR
RESET_n => MREQ_n~reg0.PRESET
RESET_n => IORQ_n~reg0.PRESET
RESET_n => WR_n~reg0.PRESET
RESET_n => RD_n~reg0.PRESET
CLK_n => T80:u0.CLK_n
CLK_n => DI_Reg[0].CLK
CLK_n => DI_Reg[1].CLK
CLK_n => DI_Reg[2].CLK
CLK_n => DI_Reg[3].CLK
CLK_n => DI_Reg[4].CLK
CLK_n => DI_Reg[5].CLK
CLK_n => DI_Reg[6].CLK
CLK_n => DI_Reg[7].CLK
CLK_n => MREQ_n~reg0.CLK
CLK_n => IORQ_n~reg0.CLK
CLK_n => WR_n~reg0.CLK
CLK_n => RD_n~reg0.CLK
CLKEN => T80:u0.CEN
CLKEN => DI_Reg[0].ENA
CLKEN => RD_n~reg0.ENA
CLKEN => WR_n~reg0.ENA
CLKEN => IORQ_n~reg0.ENA
CLKEN => MREQ_n~reg0.ENA
CLKEN => DI_Reg[7].ENA
CLKEN => DI_Reg[6].ENA
CLKEN => DI_Reg[5].ENA
CLKEN => DI_Reg[4].ENA
CLKEN => DI_Reg[3].ENA
CLKEN => DI_Reg[2].ENA
CLKEN => DI_Reg[1].ENA
WAIT_n => process_0.IN1
WAIT_n => T80:u0.WAIT_n
WAIT_n => process_0.IN1
INT_n => T80:u0.INT_n
NMI_n => T80:u0.NMI_n
BUSRQ_n => T80:u0.BUSRQ_n
M1_n <= T80:u0.M1_n
MREQ_n <= MREQ_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
IORQ_n <= IORQ_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD_n <= RD_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
WR_n <= WR_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
RFSH_n <= T80:u0.RFSH_n
HALT_n <= T80:u0.HALT_n
BUSAK_n <= T80:u0.BUSAK_n
A[0] <= T80:u0.A[0]
A[1] <= T80:u0.A[1]
A[2] <= T80:u0.A[2]
A[3] <= T80:u0.A[3]
A[4] <= T80:u0.A[4]
A[5] <= T80:u0.A[5]
A[6] <= T80:u0.A[6]
A[7] <= T80:u0.A[7]
A[8] <= T80:u0.A[8]
A[9] <= T80:u0.A[9]
A[10] <= T80:u0.A[10]
A[11] <= T80:u0.A[11]
A[12] <= T80:u0.A[12]
A[13] <= T80:u0.A[13]
A[14] <= T80:u0.A[14]
A[15] <= T80:u0.A[15]
DI[0] => DI_Reg.DATAB
DI[0] => T80:u0.DInst[0]
DI[1] => DI_Reg.DATAB
DI[1] => T80:u0.DInst[1]
DI[2] => DI_Reg.DATAB
DI[2] => T80:u0.DInst[2]
DI[3] => DI_Reg.DATAB
DI[3] => T80:u0.DInst[3]
DI[4] => DI_Reg.DATAB
DI[4] => T80:u0.DInst[4]
DI[5] => DI_Reg.DATAB
DI[5] => T80:u0.DInst[5]
DI[6] => DI_Reg.DATAB
DI[6] => T80:u0.DInst[6]
DI[7] => DI_Reg.DATAB
DI[7] => T80:u0.DInst[7]
DO[0] <= T80:u0.DO[0]
DO[1] <= T80:u0.DO[1]
DO[2] <= T80:u0.DO[2]
DO[3] <= T80:u0.DO[3]
DO[4] <= T80:u0.DO[4]
DO[5] <= T80:u0.DO[5]
DO[6] <= T80:u0.DO[6]
DO[7] <= T80:u0.DO[7]


|z80soc|T80se:z80_inst|T80:u0
RESET_n => XY_Ind.ACLR
RESET_n => PreserveC_r.ACLR
RESET_n => Save_ALU_r.ACLR
RESET_n => ALU_Op_r[0].ACLR
RESET_n => ALU_Op_r[1].ACLR
RESET_n => ALU_Op_r[2].ACLR
RESET_n => ALU_Op_r[3].ACLR
RESET_n => Z16_r.ACLR
RESET_n => BTR_r.ACLR
RESET_n => Arith16_r.ACLR
RESET_n => Read_To_Reg_r[0].ACLR
RESET_n => Read_To_Reg_r[1].ACLR
RESET_n => Read_To_Reg_r[2].ACLR
RESET_n => Read_To_Reg_r[3].ACLR
RESET_n => Read_To_Reg_r[4].ACLR
RESET_n => Alternate.ACLR
RESET_n => SP[0].PRESET
RESET_n => SP[1].PRESET
RESET_n => SP[2].PRESET
RESET_n => SP[3].PRESET
RESET_n => SP[4].PRESET
RESET_n => SP[5].PRESET
RESET_n => SP[6].PRESET
RESET_n => SP[7].PRESET
RESET_n => SP[8].PRESET
RESET_n => SP[9].PRESET
RESET_n => SP[10].PRESET
RESET_n => SP[11].PRESET
RESET_n => SP[12].PRESET
RESET_n => SP[13].PRESET
RESET_n => SP[14].PRESET
RESET_n => SP[15].PRESET
RESET_n => R[0].ACLR
RESET_n => R[1].ACLR
RESET_n => R[2].ACLR
RESET_n => R[3].ACLR
RESET_n => R[4].ACLR
RESET_n => R[5].ACLR
RESET_n => R[6].ACLR
RESET_n => R[7].ACLR
RESET_n => I[0].ACLR
RESET_n => I[1].ACLR
RESET_n => I[2].ACLR
RESET_n => I[3].ACLR
RESET_n => I[4].ACLR
RESET_n => I[5].ACLR
RESET_n => I[6].ACLR
RESET_n => I[7].ACLR
RESET_n => Fp[0].PRESET
RESET_n => Fp[1].PRESET
RESET_n => Fp[2].PRESET
RESET_n => Fp[3].PRESET
RESET_n => Fp[4].PRESET
RESET_n => Fp[5].PRESET
RESET_n => Fp[6].PRESET
RESET_n => Fp[7].PRESET
RESET_n => Ap[0].PRESET
RESET_n => Ap[1].PRESET
RESET_n => Ap[2].PRESET
RESET_n => Ap[3].PRESET
RESET_n => Ap[4].PRESET
RESET_n => Ap[5].PRESET
RESET_n => Ap[6].PRESET
RESET_n => Ap[7].PRESET
RESET_n => F[0].PRESET
RESET_n => F[1].PRESET
RESET_n => F[2].PRESET
RESET_n => F[3].PRESET
RESET_n => F[4].PRESET
RESET_n => F[5].PRESET
RESET_n => F[6].PRESET
RESET_n => F[7].PRESET
RESET_n => ACC[0].PRESET
RESET_n => ACC[1].PRESET
RESET_n => ACC[2].PRESET
RESET_n => ACC[3].PRESET
RESET_n => ACC[4].PRESET
RESET_n => ACC[5].PRESET
RESET_n => ACC[6].PRESET
RESET_n => ACC[7].PRESET
RESET_n => DO[0]~reg0.ACLR
RESET_n => DO[1]~reg0.ACLR
RESET_n => DO[2]~reg0.ACLR
RESET_n => DO[3]~reg0.ACLR
RESET_n => DO[4]~reg0.ACLR
RESET_n => DO[5]~reg0.ACLR
RESET_n => DO[6]~reg0.ACLR
RESET_n => DO[7]~reg0.ACLR
RESET_n => MCycles[0].ACLR
RESET_n => MCycles[1].ACLR
RESET_n => MCycles[2].ACLR
RESET_n => IStatus[0].ACLR
RESET_n => IStatus[1].ACLR
RESET_n => XY_State[0].ACLR
RESET_n => XY_State[1].ACLR
RESET_n => ISet[0].ACLR
RESET_n => ISet[1].ACLR
RESET_n => IR[0].ACLR
RESET_n => IR[1].ACLR
RESET_n => IR[2].ACLR
RESET_n => IR[3].ACLR
RESET_n => IR[4].ACLR
RESET_n => IR[5].ACLR
RESET_n => IR[6].ACLR
RESET_n => IR[7].ACLR
RESET_n => TmpAddr[0].ACLR
RESET_n => TmpAddr[1].ACLR
RESET_n => TmpAddr[2].ACLR
RESET_n => TmpAddr[3].ACLR
RESET_n => TmpAddr[4].ACLR
RESET_n => TmpAddr[5].ACLR
RESET_n => TmpAddr[6].ACLR
RESET_n => TmpAddr[7].ACLR
RESET_n => TmpAddr[8].ACLR
RESET_n => TmpAddr[9].ACLR
RESET_n => TmpAddr[10].ACLR
RESET_n => TmpAddr[11].ACLR
RESET_n => TmpAddr[12].ACLR
RESET_n => TmpAddr[13].ACLR
RESET_n => TmpAddr[14].ACLR
RESET_n => TmpAddr[15].ACLR
RESET_n => A[0]~reg0.ACLR
RESET_n => A[1]~reg0.ACLR
RESET_n => A[2]~reg0.ACLR
RESET_n => A[3]~reg0.ACLR
RESET_n => A[4]~reg0.ACLR
RESET_n => A[5]~reg0.ACLR
RESET_n => A[6]~reg0.ACLR
RESET_n => A[7]~reg0.ACLR
RESET_n => A[8]~reg0.ACLR
RESET_n => A[9]~reg0.ACLR
RESET_n => A[10]~reg0.ACLR
RESET_n => A[11]~reg0.ACLR
RESET_n => A[12]~reg0.ACLR
RESET_n => A[13]~reg0.ACLR
RESET_n => A[14]~reg0.ACLR
RESET_n => A[15]~reg0.ACLR
RESET_n => PC[0].ACLR
RESET_n => PC[1].ACLR
RESET_n => PC[2].ACLR
RESET_n => PC[3].ACLR
RESET_n => PC[4].ACLR
RESET_n => PC[5].ACLR
RESET_n => PC[6].ACLR
RESET_n => PC[7].ACLR
RESET_n => PC[8].ACLR
RESET_n => PC[9].ACLR
RESET_n => PC[10].ACLR
RESET_n => PC[11].ACLR
RESET_n => PC[12].ACLR
RESET_n => PC[13].ACLR
RESET_n => PC[14].ACLR
RESET_n => PC[15].ACLR
RESET_n => M1_n~reg0.PRESET
RESET_n => Auto_Wait_t2.ACLR
RESET_n => Auto_Wait_t1.ACLR
RESET_n => No_BTR.ACLR
RESET_n => IntE_FF2.ACLR
RESET_n => IntE_FF1.ACLR
RESET_n => IntCycle.ACLR
RESET_n => NMICycle.ACLR
RESET_n => BusAck.ACLR
RESET_n => Halt_FF.ACLR
RESET_n => Pre_XY_F_M[0].ACLR
RESET_n => Pre_XY_F_M[1].ACLR
RESET_n => Pre_XY_F_M[2].ACLR
RESET_n => TState[0].ACLR
RESET_n => TState[1].ACLR
RESET_n => TState[2].ACLR
RESET_n => MCycle[0].PRESET
RESET_n => MCycle[1].ACLR
RESET_n => MCycle[2].ACLR
RESET_n => RFSH_n~reg0.PRESET
RESET_n => NMI_s.ACLR
RESET_n => INT_s.ACLR
RESET_n => BusReq_s.ACLR
RESET_n => OldNMI_n.ACLR
CLK_n => T80_Reg:Regs.Clk
CLK_n => M1_n~reg0.CLK
CLK_n => Auto_Wait_t2.CLK
CLK_n => Auto_Wait_t1.CLK
CLK_n => No_BTR.CLK
CLK_n => IntE_FF2.CLK
CLK_n => IntE_FF1.CLK
CLK_n => IntCycle.CLK
CLK_n => NMICycle.CLK
CLK_n => BusAck.CLK
CLK_n => Halt_FF.CLK
CLK_n => Pre_XY_F_M[0].CLK
CLK_n => Pre_XY_F_M[1].CLK
CLK_n => Pre_XY_F_M[2].CLK
CLK_n => TState[0].CLK
CLK_n => TState[1].CLK
CLK_n => TState[2].CLK
CLK_n => MCycle[0].CLK
CLK_n => MCycle[1].CLK
CLK_n => MCycle[2].CLK
CLK_n => NMI_s.CLK
CLK_n => INT_s.CLK
CLK_n => BusReq_s.CLK
CLK_n => OldNMI_n.CLK
CLK_n => RFSH_n~reg0.CLK
CLK_n => BusA[0].CLK
CLK_n => BusA[1].CLK
CLK_n => BusA[2].CLK
CLK_n => BusA[3].CLK
CLK_n => BusA[4].CLK
CLK_n => BusA[5].CLK
CLK_n => BusA[6].CLK
CLK_n => BusA[7].CLK
CLK_n => BusB[0].CLK
CLK_n => BusB[1].CLK
CLK_n => BusB[2].CLK
CLK_n => BusB[3].CLK
CLK_n => BusB[4].CLK
CLK_n => BusB[5].CLK
CLK_n => BusB[6].CLK
CLK_n => BusB[7].CLK
CLK_n => RegBusA_r[0].CLK
CLK_n => RegBusA_r[1].CLK
CLK_n => RegBusA_r[2].CLK
CLK_n => RegBusA_r[3].CLK
CLK_n => RegBusA_r[4].CLK
CLK_n => RegBusA_r[5].CLK
CLK_n => RegBusA_r[6].CLK
CLK_n => RegBusA_r[7].CLK
CLK_n => RegBusA_r[8].CLK
CLK_n => RegBusA_r[9].CLK
CLK_n => RegBusA_r[10].CLK
CLK_n => RegBusA_r[11].CLK
CLK_n => RegBusA_r[12].CLK
CLK_n => RegBusA_r[13].CLK
CLK_n => RegBusA_r[14].CLK
CLK_n => RegBusA_r[15].CLK
CLK_n => IncDecZ.CLK
CLK_n => RegAddrC[0].CLK
CLK_n => RegAddrC[1].CLK
CLK_n => RegAddrC[2].CLK
CLK_n => RegAddrB_r[0].CLK
CLK_n => RegAddrB_r[1].CLK
CLK_n => RegAddrB_r[2].CLK
CLK_n => RegAddrA_r[0].CLK
CLK_n => RegAddrA_r[1].CLK
CLK_n => RegAddrA_r[2].CLK
CLK_n => XY_Ind.CLK
CLK_n => PreserveC_r.CLK
CLK_n => Save_ALU_r.CLK
CLK_n => ALU_Op_r[0].CLK
CLK_n => ALU_Op_r[1].CLK
CLK_n => ALU_Op_r[2].CLK
CLK_n => ALU_Op_r[3].CLK
CLK_n => Z16_r.CLK
CLK_n => BTR_r.CLK
CLK_n => Arith16_r.CLK
CLK_n => Read_To_Reg_r[0].CLK
CLK_n => Read_To_Reg_r[1].CLK
CLK_n => Read_To_Reg_r[2].CLK
CLK_n => Read_To_Reg_r[3].CLK
CLK_n => Read_To_Reg_r[4].CLK
CLK_n => Alternate.CLK
CLK_n => SP[0].CLK
CLK_n => SP[1].CLK
CLK_n => SP[2].CLK
CLK_n => SP[3].CLK
CLK_n => SP[4].CLK
CLK_n => SP[5].CLK
CLK_n => SP[6].CLK
CLK_n => SP[7].CLK
CLK_n => SP[8].CLK
CLK_n => SP[9].CLK
CLK_n => SP[10].CLK
CLK_n => SP[11].CLK
CLK_n => SP[12].CLK
CLK_n => SP[13].CLK
CLK_n => SP[14].CLK
CLK_n => SP[15].CLK
CLK_n => R[0].CLK
CLK_n => R[1].CLK
CLK_n => R[2].CLK
CLK_n => R[3].CLK
CLK_n => R[4].CLK
CLK_n => R[5].CLK
CLK_n => R[6].CLK
CLK_n => R[7].CLK
CLK_n => I[0].CLK
CLK_n => I[1].CLK
CLK_n => I[2].CLK
CLK_n => I[3].CLK
CLK_n => I[4].CLK
CLK_n => I[5].CLK
CLK_n => I[6].CLK
CLK_n => I[7].CLK
CLK_n => Fp[0].CLK
CLK_n => Fp[1].CLK
CLK_n => Fp[2].CLK
CLK_n => Fp[3].CLK
CLK_n => Fp[4].CLK
CLK_n => Fp[5].CLK
CLK_n => Fp[6].CLK
CLK_n => Fp[7].CLK
CLK_n => Ap[0].CLK
CLK_n => Ap[1].CLK
CLK_n => Ap[2].CLK
CLK_n => Ap[3].CLK
CLK_n => Ap[4].CLK
CLK_n => Ap[5].CLK
CLK_n => Ap[6].CLK
CLK_n => Ap[7].CLK
CLK_n => F[0].CLK
CLK_n => F[1].CLK
CLK_n => F[2].CLK
CLK_n => F[3].CLK
CLK_n => F[4].CLK
CLK_n => F[5].CLK
CLK_n => F[6].CLK
CLK_n => F[7].CLK
CLK_n => ACC[0].CLK
CLK_n => ACC[1].CLK
CLK_n => ACC[2].CLK
CLK_n => ACC[3].CLK
CLK_n => ACC[4].CLK
CLK_n => ACC[5].CLK
CLK_n => ACC[6].CLK
CLK_n => ACC[7].CLK
CLK_n => DO[0]~reg0.CLK
CLK_n => DO[1]~reg0.CLK
CLK_n => DO[2]~reg0.CLK
CLK_n => DO[3]~reg0.CLK
CLK_n => DO[4]~reg0.CLK
CLK_n => DO[5]~reg0.CLK
CLK_n => DO[6]~reg0.CLK
CLK_n => DO[7]~reg0.CLK
CLK_n => MCycles[0].CLK
CLK_n => MCycles[1].CLK
CLK_n => MCycles[2].CLK
CLK_n => IStatus[0].CLK
CLK_n => IStatus[1].CLK
CLK_n => XY_State[0].CLK
CLK_n => XY_State[1].CLK
CLK_n => ISet[0].CLK
CLK_n => ISet[1].CLK
CLK_n => IR[0].CLK
CLK_n => IR[1].CLK
CLK_n => IR[2].CLK
CLK_n => IR[3].CLK
CLK_n => IR[4].CLK
CLK_n => IR[5].CLK
CLK_n => IR[6].CLK
CLK_n => IR[7].CLK
CLK_n => TmpAddr[0].CLK
CLK_n => TmpAddr[1].CLK
CLK_n => TmpAddr[2].CLK
CLK_n => TmpAddr[3].CLK
CLK_n => TmpAddr[4].CLK
CLK_n => TmpAddr[5].CLK
CLK_n => TmpAddr[6].CLK
CLK_n => TmpAddr[7].CLK
CLK_n => TmpAddr[8].CLK
CLK_n => TmpAddr[9].CLK
CLK_n => TmpAddr[10].CLK
CLK_n => TmpAddr[11].CLK
CLK_n => TmpAddr[12].CLK
CLK_n => TmpAddr[13].CLK
CLK_n => TmpAddr[14].CLK
CLK_n => TmpAddr[15].CLK
CLK_n => A[0]~reg0.CLK
CLK_n => A[1]~reg0.CLK
CLK_n => A[2]~reg0.CLK
CLK_n => A[3]~reg0.CLK
CLK_n => A[4]~reg0.CLK
CLK_n => A[5]~reg0.CLK
CLK_n => A[6]~reg0.CLK
CLK_n => A[7]~reg0.CLK
CLK_n => A[8]~reg0.CLK
CLK_n => A[9]~reg0.CLK
CLK_n => A[10]~reg0.CLK
CLK_n => A[11]~reg0.CLK
CLK_n => A[12]~reg0.CLK
CLK_n => A[13]~reg0.CLK
CLK_n => A[14]~reg0.CLK
CLK_n => A[15]~reg0.CLK
CLK_n => PC[0].CLK
CLK_n => PC[1].CLK
CLK_n => PC[2].CLK
CLK_n => PC[3].CLK
CLK_n => PC[4].CLK
CLK_n => PC[5].CLK
CLK_n => PC[6].CLK
CLK_n => PC[7].CLK
CLK_n => PC[8].CLK
CLK_n => PC[9].CLK
CLK_n => PC[10].CLK
CLK_n => PC[11].CLK
CLK_n => PC[12].CLK
CLK_n => PC[13].CLK
CLK_n => PC[14].CLK
CLK_n => PC[15].CLK
CEN => ClkEn.IN1
CEN => RFSH_n~reg0.ENA
CEN => OldNMI_n.ENA
CEN => BusReq_s.ENA
CEN => INT_s.ENA
CEN => M1_n~reg0.ENA
CEN => NMI_s.ENA
CEN => MCycle[2].ENA
CEN => MCycle[1].ENA
CEN => MCycle[0].ENA
CEN => TState[2].ENA
CEN => TState[1].ENA
CEN => TState[0].ENA
CEN => Pre_XY_F_M[2].ENA
CEN => Pre_XY_F_M[1].ENA
CEN => Pre_XY_F_M[0].ENA
CEN => Halt_FF.ENA
CEN => BusAck.ENA
CEN => NMICycle.ENA
CEN => IntCycle.ENA
CEN => IntE_FF1.ENA
CEN => IntE_FF2.ENA
CEN => No_BTR.ENA
CEN => Auto_Wait_t1.ENA
CEN => Auto_Wait_t2.ENA
WAIT_n => process_2.IN1
WAIT_n => process_5.IN1
WAIT_n => process_7.IN1
WAIT_n => process_7.IN1
INT_n => INT_s.DATAIN
NMI_n => process_6.IN1
NMI_n => OldNMI_n.DATAIN
BUSRQ_n => BusReq_s.DATAIN
M1_n <= M1_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
IORQ <= T80_MCode:mcode.IORQ
NoRead <= T80_MCode:mcode.NoRead
Write <= T80_MCode:mcode.Write
RFSH_n <= RFSH_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
HALT_n <= Halt_FF.DB_MAX_OUTPUT_PORT_TYPE
BUSAK_n <= BusAck.DB_MAX_OUTPUT_PORT_TYPE
A[0] <= A[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[1] <= A[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[2] <= A[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[3] <= A[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[4] <= A[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[5] <= A[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[6] <= A[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[7] <= A[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[8] <= A[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[9] <= A[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[10] <= A[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[11] <= A[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[12] <= A[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[13] <= A[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[14] <= A[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[15] <= A[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DInst[0] => IR.DATAA
DInst[0] => IR.DATAB
DInst[1] => IR.DATAA
DInst[1] => IR.DATAB
DInst[2] => IR.DATAA
DInst[2] => IR.DATAB
DInst[3] => IR.DATAA
DInst[3] => IR.DATAB
DInst[4] => IR.DATAA
DInst[4] => IR.DATAB
DInst[5] => IR.DATAA
DInst[5] => IR.DATAB
DInst[6] => IR.DATAA
DInst[6] => IR.DATAB
DInst[7] => IR.DATAA
DInst[7] => IR.DATAB
DI[0] => Save_Mux.DATAB
DI[0] => A.DATAA
DI[0] => Mux15.IN7
DI[0] => A.DATAB
DI[0] => PC.DATAB
DI[0] => Add2.IN32
DI[0] => Add5.IN32
DI[0] => TmpAddr.DATAB
DI[0] => TmpAddr.DATAB
DI[0] => F.IN0
DI[0] => Mux91.IN15
DI[0] => Mux99.IN10
DI[0] => Equal18.IN7
DI[1] => Save_Mux.DATAB
DI[1] => A.DATAA
DI[1] => Mux14.IN7
DI[1] => A.DATAB
DI[1] => PC.DATAB
DI[1] => Add2.IN31
DI[1] => Add5.IN31
DI[1] => TmpAddr.DATAB
DI[1] => TmpAddr.DATAB
DI[1] => F.IN1
DI[1] => Mux90.IN15
DI[1] => Mux98.IN10
DI[1] => Equal18.IN6
DI[2] => Save_Mux.DATAB
DI[2] => A.DATAA
DI[2] => Mux13.IN7
DI[2] => A.DATAB
DI[2] => PC.DATAB
DI[2] => Add2.IN30
DI[2] => Add5.IN30
DI[2] => TmpAddr.DATAB
DI[2] => TmpAddr.DATAB
DI[2] => F.IN1
DI[2] => Mux89.IN15
DI[2] => Mux97.IN10
DI[2] => Equal18.IN5
DI[3] => Save_Mux.DATAB
DI[3] => A.DATAA
DI[3] => Mux12.IN7
DI[3] => A.DATAB
DI[3] => PC.DATAB
DI[3] => Add2.IN29
DI[3] => Add5.IN29
DI[3] => TmpAddr.DATAB
DI[3] => TmpAddr.DATAB
DI[3] => F.IN1
DI[3] => Mux88.IN15
DI[3] => Mux96.IN10
DI[3] => Equal18.IN4
DI[4] => Save_Mux.DATAB
DI[4] => A.DATAA
DI[4] => Mux11.IN7
DI[4] => A.DATAB
DI[4] => PC.DATAB
DI[4] => Add2.IN28
DI[4] => Add5.IN28
DI[4] => TmpAddr.DATAB
DI[4] => TmpAddr.DATAB
DI[4] => F.IN1
DI[4] => Mux87.IN15
DI[4] => Mux95.IN10
DI[4] => Equal18.IN3
DI[5] => Save_Mux.DATAB
DI[5] => A.DATAA
DI[5] => Mux10.IN7
DI[5] => A.DATAB
DI[5] => PC.DATAB
DI[5] => Add2.IN27
DI[5] => Add5.IN27
DI[5] => TmpAddr.DATAB
DI[5] => TmpAddr.DATAB
DI[5] => F.IN1
DI[5] => Mux86.IN15
DI[5] => Mux94.IN10
DI[5] => Equal18.IN2
DI[6] => Save_Mux.DATAB
DI[6] => A.DATAA
DI[6] => Mux9.IN7
DI[6] => A.DATAB
DI[6] => PC.DATAB
DI[6] => Add2.IN26
DI[6] => Add5.IN26
DI[6] => TmpAddr.DATAB
DI[6] => TmpAddr.DATAB
DI[6] => F.IN1
DI[6] => Mux85.IN15
DI[6] => Mux93.IN10
DI[6] => Equal18.IN1
DI[7] => Save_Mux.DATAB
DI[7] => A.DATAA
DI[7] => Mux8.IN7
DI[7] => A.DATAB
DI[7] => PC.DATAB
DI[7] => Add2.IN17
DI[7] => Add2.IN18
DI[7] => Add2.IN19
DI[7] => Add2.IN20
DI[7] => Add2.IN21
DI[7] => Add2.IN22
DI[7] => Add2.IN23
DI[7] => Add2.IN24
DI[7] => Add2.IN25
DI[7] => Add5.IN17
DI[7] => Add5.IN18
DI[7] => Add5.IN19
DI[7] => Add5.IN20
DI[7] => Add5.IN21
DI[7] => Add5.IN22
DI[7] => Add5.IN23
DI[7] => Add5.IN24
DI[7] => Add5.IN25
DI[7] => TmpAddr.DATAB
DI[7] => TmpAddr.DATAB
DI[7] => F.IN1
DI[7] => F.DATAB
DI[7] => Mux84.IN15
DI[7] => Mux92.IN10
DI[7] => Equal18.IN0
DO[0] <= DO[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[1] <= DO[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[2] <= DO[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[3] <= DO[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[4] <= DO[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[5] <= DO[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[6] <= DO[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO[7] <= DO[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MC[0] <= MCycle[0].DB_MAX_OUTPUT_PORT_TYPE
MC[1] <= MCycle[1].DB_MAX_OUTPUT_PORT_TYPE
MC[2] <= MCycle[2].DB_MAX_OUTPUT_PORT_TYPE
TS[0] <= TState[0].DB_MAX_OUTPUT_PORT_TYPE
TS[1] <= TState[1].DB_MAX_OUTPUT_PORT_TYPE
TS[2] <= TState[2].DB_MAX_OUTPUT_PORT_TYPE
IntCycle_n <= IntCycle.DB_MAX_OUTPUT_PORT_TYPE
IntE <= IntE_FF1.DB_MAX_OUTPUT_PORT_TYPE
Stop <= T80_MCode:mcode.I_DJNZ


|z80soc|T80se:z80_inst|T80:u0|T80_MCode:mcode
IR[0] => Mux5.IN7
IR[0] => Mux28.IN7
IR[0] => Set_BusB_To.DATAB
IR[0] => Mux61.IN263
IR[0] => Mux62.IN263
IR[0] => Mux63.IN263
IR[0] => Mux64.IN158
IR[0] => Mux64.IN159
IR[0] => Mux64.IN160
IR[0] => Mux64.IN161
IR[0] => Mux64.IN162
IR[0] => Mux64.IN163
IR[0] => Mux64.IN164
IR[0] => Mux64.IN165
IR[0] => Mux64.IN166
IR[0] => Mux64.IN167
IR[0] => Mux64.IN168
IR[0] => Mux64.IN169
IR[0] => Mux64.IN170
IR[0] => Mux64.IN171
IR[0] => Mux64.IN172
IR[0] => Mux64.IN173
IR[0] => Mux64.IN174
IR[0] => Mux64.IN175
IR[0] => Mux64.IN176
IR[0] => Mux64.IN177
IR[0] => Mux64.IN178
IR[0] => Mux64.IN179
IR[0] => Mux64.IN180
IR[0] => Mux64.IN181
IR[0] => Mux64.IN182
IR[0] => Mux64.IN183
IR[0] => Mux64.IN184
IR[0] => Mux64.IN185
IR[0] => Mux64.IN186
IR[0] => Mux64.IN187
IR[0] => Mux64.IN188
IR[0] => Mux64.IN189
IR[0] => Mux64.IN190
IR[0] => Mux64.IN191
IR[0] => Mux64.IN192
IR[0] => Mux64.IN193
IR[0] => Mux64.IN194
IR[0] => Mux64.IN195
IR[0] => Mux64.IN196
IR[0] => Mux64.IN197
IR[0] => Mux64.IN198
IR[0] => Mux64.IN199
IR[0] => Mux64.IN200
IR[0] => Mux64.IN201
IR[0] => Mux64.IN202
IR[0] => Mux64.IN203
IR[0] => Mux64.IN204
IR[0] => Mux64.IN205
IR[0] => Mux64.IN206
IR[0] => Mux64.IN207
IR[0] => Mux64.IN208
IR[0] => Mux64.IN209
IR[0] => Mux64.IN210
IR[0] => Mux64.IN211
IR[0] => Mux64.IN212
IR[0] => Mux64.IN213
IR[0] => Mux64.IN214
IR[0] => Mux64.IN215
IR[0] => Mux64.IN216
IR[0] => Mux64.IN217
IR[0] => Mux64.IN218
IR[0] => Mux64.IN219
IR[0] => Mux64.IN220
IR[0] => Mux64.IN221
IR[0] => Mux64.IN222
IR[0] => Mux64.IN223
IR[0] => Mux64.IN224
IR[0] => Mux64.IN225
IR[0] => Mux64.IN226
IR[0] => Mux64.IN227
IR[0] => Mux64.IN228
IR[0] => Mux64.IN229
IR[0] => Mux64.IN230
IR[0] => Mux64.IN231
IR[0] => Mux64.IN232
IR[0] => Mux64.IN233
IR[0] => Mux64.IN234
IR[0] => Mux64.IN235
IR[0] => Mux64.IN236
IR[0] => Mux64.IN237
IR[0] => Mux64.IN238
IR[0] => Mux64.IN239
IR[0] => Mux64.IN240
IR[0] => Mux64.IN241
IR[0] => Mux64.IN242
IR[0] => Mux64.IN243
IR[0] => Mux64.IN244
IR[0] => Mux64.IN245
IR[0] => Mux64.IN246
IR[0] => Mux64.IN247
IR[0] => Mux64.IN248
IR[0] => Mux64.IN249
IR[0] => Mux64.IN250
IR[0] => Mux64.IN251
IR[0] => Mux64.IN252
IR[0] => Mux64.IN253
IR[0] => Mux64.IN254
IR[0] => Mux64.IN255
IR[0] => Mux64.IN256
IR[0] => Mux64.IN257
IR[0] => Mux64.IN258
IR[0] => Mux64.IN259
IR[0] => Mux64.IN260
IR[0] => Mux64.IN261
IR[0] => Mux64.IN262
IR[0] => Mux64.IN263
IR[0] => Mux65.IN263
IR[0] => Mux66.IN69
IR[0] => Mux67.IN263
IR[0] => Mux68.IN263
IR[0] => Mux69.IN263
IR[0] => Mux70.IN263
IR[0] => Mux71.IN263
IR[0] => Mux72.IN262
IR[0] => Mux73.IN263
IR[0] => Mux74.IN263
IR[0] => Mux75.IN263
IR[0] => Mux76.IN263
IR[0] => Mux77.IN263
IR[0] => Mux78.IN263
IR[0] => Mux79.IN263
IR[0] => Mux80.IN263
IR[0] => Mux81.IN263
IR[0] => Mux82.IN263
IR[0] => Mux83.IN263
IR[0] => Mux84.IN263
IR[0] => Mux85.IN263
IR[0] => Mux86.IN263
IR[0] => Mux87.IN263
IR[0] => Mux88.IN263
IR[0] => Mux89.IN263
IR[0] => Mux90.IN263
IR[0] => Mux91.IN263
IR[0] => Mux92.IN263
IR[0] => Mux93.IN263
IR[0] => Mux94.IN263
IR[0] => Mux95.IN263
IR[0] => Mux96.IN263
IR[0] => Mux97.IN263
IR[0] => Mux98.IN263
IR[0] => Mux99.IN263
IR[0] => Mux100.IN263
IR[0] => Mux101.IN263
IR[0] => Mux102.IN263
IR[0] => Mux103.IN263
IR[0] => Mux104.IN263
IR[0] => Mux105.IN263
IR[0] => Mux106.IN263
IR[0] => Mux107.IN263
IR[0] => Mux108.IN69
IR[0] => Mux109.IN263
IR[0] => Mux110.IN263
IR[0] => Mux111.IN263
IR[0] => Mux112.IN263
IR[0] => Mux113.IN36
IR[0] => Mux114.IN263
IR[0] => Mux115.IN263
IR[0] => Mux116.IN263
IR[0] => Mux119.IN36
IR[0] => Mux120.IN36
IR[0] => Mux121.IN36
IR[0] => Mux122.IN36
IR[0] => Mux123.IN36
IR[0] => Mux124.IN10
IR[0] => Mux125.IN36
IR[0] => Mux126.IN36
IR[0] => Mux127.IN36
IR[0] => Mux128.IN36
IR[0] => Mux129.IN36
IR[0] => Mux130.IN36
IR[0] => Mux197.IN69
IR[0] => Mux198.IN134
IR[0] => Mux199.IN134
IR[0] => Mux200.IN263
IR[0] => Mux201.IN263
IR[0] => Mux202.IN263
IR[0] => Mux203.IN134
IR[0] => Mux204.IN36
IR[0] => Mux205.IN134
IR[0] => Mux206.IN69
IR[0] => Mux207.IN69
IR[0] => Mux208.IN263
IR[0] => Mux209.IN69
IR[0] => Mux210.IN263
IR[0] => Mux211.IN69
IR[0] => Mux212.IN263
IR[0] => Mux213.IN69
IR[0] => Mux214.IN263
IR[0] => Mux215.IN263
IR[0] => Mux216.IN263
IR[0] => Mux217.IN69
IR[0] => Mux218.IN134
IR[0] => Mux219.IN263
IR[0] => Mux220.IN263
IR[0] => Mux221.IN69
IR[0] => Mux222.IN263
IR[0] => Mux223.IN69
IR[0] => Mux224.IN69
IR[0] => Mux225.IN69
IR[0] => Mux226.IN69
IR[0] => Mux227.IN263
IR[0] => Mux228.IN263
IR[0] => Mux229.IN263
IR[0] => Mux230.IN263
IR[0] => Mux231.IN69
IR[0] => Mux232.IN263
IR[0] => Mux233.IN263
IR[0] => Mux234.IN69
IR[0] => Mux235.IN69
IR[0] => Mux236.IN36
IR[0] => Mux237.IN134
IR[0] => Mux238.IN263
IR[0] => Mux239.IN263
IR[0] => Mux240.IN263
IR[0] => Mux241.IN36
IR[0] => Mux242.IN69
IR[0] => Mux243.IN36
IR[0] => Mux244.IN69
IR[0] => Mux248.IN3
IR[0] => Mux253.IN3
IR[0] => Set_BusB_To.DATAB
IR[0] => Equal5.IN7
IR[0] => Equal7.IN3
IR[1] => Mux4.IN7
IR[1] => Mux27.IN7
IR[1] => Set_BusB_To.DATAB
IR[1] => Mux61.IN262
IR[1] => Mux62.IN262
IR[1] => Mux63.IN157
IR[1] => Mux63.IN158
IR[1] => Mux63.IN159
IR[1] => Mux63.IN160
IR[1] => Mux63.IN161
IR[1] => Mux63.IN162
IR[1] => Mux63.IN163
IR[1] => Mux63.IN164
IR[1] => Mux63.IN165
IR[1] => Mux63.IN166
IR[1] => Mux63.IN167
IR[1] => Mux63.IN168
IR[1] => Mux63.IN169
IR[1] => Mux63.IN170
IR[1] => Mux63.IN171
IR[1] => Mux63.IN172
IR[1] => Mux63.IN173
IR[1] => Mux63.IN174
IR[1] => Mux63.IN175
IR[1] => Mux63.IN176
IR[1] => Mux63.IN177
IR[1] => Mux63.IN178
IR[1] => Mux63.IN179
IR[1] => Mux63.IN180
IR[1] => Mux63.IN181
IR[1] => Mux63.IN182
IR[1] => Mux63.IN183
IR[1] => Mux63.IN184
IR[1] => Mux63.IN185
IR[1] => Mux63.IN186
IR[1] => Mux63.IN187
IR[1] => Mux63.IN188
IR[1] => Mux63.IN189
IR[1] => Mux63.IN190
IR[1] => Mux63.IN191
IR[1] => Mux63.IN192
IR[1] => Mux63.IN193
IR[1] => Mux63.IN194
IR[1] => Mux63.IN195
IR[1] => Mux63.IN196
IR[1] => Mux63.IN197
IR[1] => Mux63.IN198
IR[1] => Mux63.IN199
IR[1] => Mux63.IN200
IR[1] => Mux63.IN201
IR[1] => Mux63.IN202
IR[1] => Mux63.IN203
IR[1] => Mux63.IN204
IR[1] => Mux63.IN205
IR[1] => Mux63.IN206
IR[1] => Mux63.IN207
IR[1] => Mux63.IN208
IR[1] => Mux63.IN209
IR[1] => Mux63.IN210
IR[1] => Mux63.IN211
IR[1] => Mux63.IN212
IR[1] => Mux63.IN213
IR[1] => Mux63.IN214
IR[1] => Mux63.IN215
IR[1] => Mux63.IN216
IR[1] => Mux63.IN217
IR[1] => Mux63.IN218
IR[1] => Mux63.IN219
IR[1] => Mux63.IN220
IR[1] => Mux63.IN221
IR[1] => Mux63.IN222
IR[1] => Mux63.IN223
IR[1] => Mux63.IN224
IR[1] => Mux63.IN225
IR[1] => Mux63.IN226
IR[1] => Mux63.IN227
IR[1] => Mux63.IN228
IR[1] => Mux63.IN229
IR[1] => Mux63.IN230
IR[1] => Mux63.IN231
IR[1] => Mux63.IN232
IR[1] => Mux63.IN233
IR[1] => Mux63.IN234
IR[1] => Mux63.IN235
IR[1] => Mux63.IN236
IR[1] => Mux63.IN237
IR[1] => Mux63.IN238
IR[1] => Mux63.IN239
IR[1] => Mux63.IN240
IR[1] => Mux63.IN241
IR[1] => Mux63.IN242
IR[1] => Mux63.IN243
IR[1] => Mux63.IN244
IR[1] => Mux63.IN245
IR[1] => Mux63.IN246
IR[1] => Mux63.IN247
IR[1] => Mux63.IN248
IR[1] => Mux63.IN249
IR[1] => Mux63.IN250
IR[1] => Mux63.IN251
IR[1] => Mux63.IN252
IR[1] => Mux63.IN253
IR[1] => Mux63.IN254
IR[1] => Mux63.IN255
IR[1] => Mux63.IN256
IR[1] => Mux63.IN257
IR[1] => Mux63.IN258
IR[1] => Mux63.IN259
IR[1] => Mux63.IN260
IR[1] => Mux63.IN261
IR[1] => Mux63.IN262
IR[1] => Mux64.IN157
IR[1] => Mux65.IN262
IR[1] => Mux66.IN68
IR[1] => Mux67.IN262
IR[1] => Mux68.IN262
IR[1] => Mux69.IN262
IR[1] => Mux70.IN262
IR[1] => Mux71.IN262
IR[1] => Mux72.IN261
IR[1] => Mux73.IN262
IR[1] => Mux74.IN262
IR[1] => Mux75.IN262
IR[1] => Mux76.IN262
IR[1] => Mux77.IN262
IR[1] => Mux78.IN262
IR[1] => Mux79.IN262
IR[1] => Mux80.IN262
IR[1] => Mux81.IN262
IR[1] => Mux82.IN262
IR[1] => Mux83.IN262
IR[1] => Mux84.IN262
IR[1] => Mux85.IN262
IR[1] => Mux86.IN262
IR[1] => Mux87.IN262
IR[1] => Mux88.IN262
IR[1] => Mux89.IN262
IR[1] => Mux90.IN262
IR[1] => Mux91.IN262
IR[1] => Mux92.IN262
IR[1] => Mux93.IN262
IR[1] => Mux94.IN262
IR[1] => Mux95.IN262
IR[1] => Mux96.IN262
IR[1] => Mux97.IN262
IR[1] => Mux98.IN262
IR[1] => Mux99.IN262
IR[1] => Mux100.IN262
IR[1] => Mux101.IN262
IR[1] => Mux102.IN262
IR[1] => Mux103.IN262
IR[1] => Mux104.IN262
IR[1] => Mux105.IN262
IR[1] => Mux106.IN262
IR[1] => Mux107.IN262
IR[1] => Mux108.IN68
IR[1] => Mux109.IN262
IR[1] => Mux110.IN262
IR[1] => Mux111.IN262
IR[1] => Mux112.IN262
IR[1] => Mux113.IN35
IR[1] => Mux114.IN262
IR[1] => Mux115.IN262
IR[1] => Mux116.IN262
IR[1] => Mux119.IN35
IR[1] => Mux120.IN35
IR[1] => Mux121.IN35
IR[1] => Mux122.IN35
IR[1] => Mux123.IN35
IR[1] => Mux124.IN9
IR[1] => Mux125.IN35
IR[1] => Mux126.IN35
IR[1] => Mux127.IN35
IR[1] => Mux128.IN35
IR[1] => Mux129.IN35
IR[1] => Mux130.IN35
IR[1] => Mux197.IN68
IR[1] => Mux198.IN133
IR[1] => Mux199.IN133
IR[1] => Mux200.IN262
IR[1] => Mux201.IN262
IR[1] => Mux202.IN262
IR[1] => Mux203.IN133
IR[1] => Mux204.IN35
IR[1] => Mux205.IN133
IR[1] => Mux206.IN68
IR[1] => Mux207.IN68
IR[1] => Mux208.IN262
IR[1] => Mux209.IN68
IR[1] => Mux210.IN262
IR[1] => Mux211.IN68
IR[1] => Mux212.IN262
IR[1] => Mux213.IN68
IR[1] => Mux214.IN262
IR[1] => Mux215.IN262
IR[1] => Mux216.IN262
IR[1] => Mux217.IN68
IR[1] => Mux218.IN133
IR[1] => Mux219.IN262
IR[1] => Mux220.IN262
IR[1] => Mux221.IN68
IR[1] => Mux222.IN262
IR[1] => Mux223.IN68
IR[1] => Mux224.IN68
IR[1] => Mux225.IN68
IR[1] => Mux226.IN68
IR[1] => Mux227.IN262
IR[1] => Mux228.IN262
IR[1] => Mux229.IN262
IR[1] => Mux230.IN262
IR[1] => Mux231.IN68
IR[1] => Mux232.IN262
IR[1] => Mux233.IN262
IR[1] => Mux234.IN68
IR[1] => Mux235.IN68
IR[1] => Mux236.IN35
IR[1] => Mux237.IN133
IR[1] => Mux238.IN262
IR[1] => Mux239.IN262
IR[1] => Mux240.IN262
IR[1] => Mux241.IN35
IR[1] => Mux242.IN68
IR[1] => Mux243.IN35
IR[1] => Mux244.IN68
IR[1] => Mux247.IN3
IR[1] => Mux252.IN3
IR[1] => Set_BusB_To.DATAB
IR[1] => Equal5.IN6
IR[1] => Equal7.IN7
IR[2] => Mux3.IN7
IR[2] => Mux26.IN7
IR[2] => Set_BusB_To.DATAB
IR[2] => Mux61.IN261
IR[2] => Mux62.IN156
IR[2] => Mux62.IN157
IR[2] => Mux62.IN158
IR[2] => Mux62.IN159
IR[2] => Mux62.IN160
IR[2] => Mux62.IN161
IR[2] => Mux62.IN162
IR[2] => Mux62.IN163
IR[2] => Mux62.IN164
IR[2] => Mux62.IN165
IR[2] => Mux62.IN166
IR[2] => Mux62.IN167
IR[2] => Mux62.IN168
IR[2] => Mux62.IN169
IR[2] => Mux62.IN170
IR[2] => Mux62.IN171
IR[2] => Mux62.IN172
IR[2] => Mux62.IN173
IR[2] => Mux62.IN174
IR[2] => Mux62.IN175
IR[2] => Mux62.IN176
IR[2] => Mux62.IN177
IR[2] => Mux62.IN178
IR[2] => Mux62.IN179
IR[2] => Mux62.IN180
IR[2] => Mux62.IN181
IR[2] => Mux62.IN182
IR[2] => Mux62.IN183
IR[2] => Mux62.IN184
IR[2] => Mux62.IN185
IR[2] => Mux62.IN186
IR[2] => Mux62.IN187
IR[2] => Mux62.IN188
IR[2] => Mux62.IN189
IR[2] => Mux62.IN190
IR[2] => Mux62.IN191
IR[2] => Mux62.IN192
IR[2] => Mux62.IN193
IR[2] => Mux62.IN194
IR[2] => Mux62.IN195
IR[2] => Mux62.IN196
IR[2] => Mux62.IN197
IR[2] => Mux62.IN198
IR[2] => Mux62.IN199
IR[2] => Mux62.IN200
IR[2] => Mux62.IN201
IR[2] => Mux62.IN202
IR[2] => Mux62.IN203
IR[2] => Mux62.IN204
IR[2] => Mux62.IN205
IR[2] => Mux62.IN206
IR[2] => Mux62.IN207
IR[2] => Mux62.IN208
IR[2] => Mux62.IN209
IR[2] => Mux62.IN210
IR[2] => Mux62.IN211
IR[2] => Mux62.IN212
IR[2] => Mux62.IN213
IR[2] => Mux62.IN214
IR[2] => Mux62.IN215
IR[2] => Mux62.IN216
IR[2] => Mux62.IN217
IR[2] => Mux62.IN218
IR[2] => Mux62.IN219
IR[2] => Mux62.IN220
IR[2] => Mux62.IN221
IR[2] => Mux62.IN222
IR[2] => Mux62.IN223
IR[2] => Mux62.IN224
IR[2] => Mux62.IN225
IR[2] => Mux62.IN226
IR[2] => Mux62.IN227
IR[2] => Mux62.IN228
IR[2] => Mux62.IN229
IR[2] => Mux62.IN230
IR[2] => Mux62.IN231
IR[2] => Mux62.IN232
IR[2] => Mux62.IN233
IR[2] => Mux62.IN234
IR[2] => Mux62.IN235
IR[2] => Mux62.IN236
IR[2] => Mux62.IN237
IR[2] => Mux62.IN238
IR[2] => Mux62.IN239
IR[2] => Mux62.IN240
IR[2] => Mux62.IN241
IR[2] => Mux62.IN242
IR[2] => Mux62.IN243
IR[2] => Mux62.IN244
IR[2] => Mux62.IN245
IR[2] => Mux62.IN246
IR[2] => Mux62.IN247
IR[2] => Mux62.IN248
IR[2] => Mux62.IN249
IR[2] => Mux62.IN250
IR[2] => Mux62.IN251
IR[2] => Mux62.IN252
IR[2] => Mux62.IN253
IR[2] => Mux62.IN254
IR[2] => Mux62.IN255
IR[2] => Mux62.IN256
IR[2] => Mux62.IN257
IR[2] => Mux62.IN258
IR[2] => Mux62.IN259
IR[2] => Mux62.IN260
IR[2] => Mux62.IN261
IR[2] => Mux63.IN156
IR[2] => Mux64.IN156
IR[2] => Mux65.IN261
IR[2] => Mux66.IN67
IR[2] => Mux67.IN261
IR[2] => Mux68.IN261
IR[2] => Mux69.IN261
IR[2] => Mux70.IN261
IR[2] => Mux71.IN261
IR[2] => Mux72.IN260
IR[2] => Mux73.IN261
IR[2] => Mux74.IN261
IR[2] => Mux75.IN261
IR[2] => Mux76.IN261
IR[2] => Mux77.IN261
IR[2] => Mux78.IN261
IR[2] => Mux79.IN261
IR[2] => Mux80.IN261
IR[2] => Mux81.IN261
IR[2] => Mux82.IN261
IR[2] => Mux83.IN261
IR[2] => Mux84.IN261
IR[2] => Mux85.IN261
IR[2] => Mux86.IN261
IR[2] => Mux87.IN261
IR[2] => Mux88.IN261
IR[2] => Mux89.IN261
IR[2] => Mux90.IN261
IR[2] => Mux91.IN261
IR[2] => Mux92.IN261
IR[2] => Mux93.IN261
IR[2] => Mux94.IN261
IR[2] => Mux95.IN261
IR[2] => Mux96.IN261
IR[2] => Mux97.IN261
IR[2] => Mux98.IN261
IR[2] => Mux99.IN261
IR[2] => Mux100.IN261
IR[2] => Mux101.IN261
IR[2] => Mux102.IN261
IR[2] => Mux103.IN261
IR[2] => Mux104.IN261
IR[2] => Mux105.IN261
IR[2] => Mux106.IN261
IR[2] => Mux107.IN261
IR[2] => Mux108.IN67
IR[2] => Mux109.IN261
IR[2] => Mux110.IN261
IR[2] => Mux111.IN261
IR[2] => Mux112.IN261
IR[2] => Mux113.IN34
IR[2] => Mux114.IN261
IR[2] => Mux115.IN261
IR[2] => Mux116.IN261
IR[2] => Mux119.IN34
IR[2] => Mux120.IN34
IR[2] => Mux121.IN34
IR[2] => Mux122.IN34
IR[2] => Mux123.IN34
IR[2] => Mux124.IN8
IR[2] => Mux125.IN34
IR[2] => Mux126.IN34
IR[2] => Mux127.IN34
IR[2] => Mux128.IN34
IR[2] => Mux129.IN34
IR[2] => Mux130.IN34
IR[2] => Mux197.IN67
IR[2] => Mux198.IN132
IR[2] => Mux199.IN132
IR[2] => Mux200.IN261
IR[2] => Mux201.IN261
IR[2] => Mux202.IN261
IR[2] => Mux203.IN132
IR[2] => Mux204.IN34
IR[2] => Mux205.IN132
IR[2] => Mux206.IN67
IR[2] => Mux207.IN67
IR[2] => Mux208.IN261
IR[2] => Mux209.IN67
IR[2] => Mux210.IN261
IR[2] => Mux211.IN67
IR[2] => Mux212.IN261
IR[2] => Mux213.IN67
IR[2] => Mux214.IN261
IR[2] => Mux215.IN261
IR[2] => Mux216.IN261
IR[2] => Mux217.IN67
IR[2] => Mux218.IN132
IR[2] => Mux219.IN261
IR[2] => Mux220.IN261
IR[2] => Mux221.IN67
IR[2] => Mux222.IN261
IR[2] => Mux223.IN67
IR[2] => Mux224.IN67
IR[2] => Mux225.IN67
IR[2] => Mux226.IN67
IR[2] => Mux227.IN261
IR[2] => Mux228.IN261
IR[2] => Mux229.IN261
IR[2] => Mux230.IN261
IR[2] => Mux231.IN67
IR[2] => Mux232.IN261
IR[2] => Mux233.IN261
IR[2] => Mux234.IN67
IR[2] => Mux235.IN67
IR[2] => Mux236.IN34
IR[2] => Mux237.IN132
IR[2] => Mux238.IN261
IR[2] => Mux239.IN261
IR[2] => Mux240.IN261
IR[2] => Mux241.IN34
IR[2] => Mux242.IN67
IR[2] => Mux243.IN34
IR[2] => Mux244.IN67
IR[2] => Mux246.IN3
IR[2] => Mux251.IN3
IR[2] => Set_BusB_To.DATAB
IR[2] => Equal5.IN2
IR[2] => Equal7.IN6
IR[3] => Mux2.IN7
IR[3] => Mux34.IN2
IR[3] => Mux34.IN3
IR[3] => Mux34.IN4
IR[3] => Mux34.IN5
IR[3] => Mux34.IN6
IR[3] => Mux34.IN7
IR[3] => Mux45.IN6
IR[3] => Mux61.IN260
IR[3] => Mux62.IN155
IR[3] => Mux63.IN155
IR[3] => Mux64.IN155
IR[3] => Mux65.IN260
IR[3] => Mux66.IN66
IR[3] => Mux67.IN260
IR[3] => Mux68.IN260
IR[3] => Mux69.IN197
IR[3] => Mux69.IN198
IR[3] => Mux69.IN199
IR[3] => Mux69.IN200
IR[3] => Mux69.IN201
IR[3] => Mux69.IN202
IR[3] => Mux69.IN203
IR[3] => Mux69.IN204
IR[3] => Mux69.IN205
IR[3] => Mux69.IN206
IR[3] => Mux69.IN207
IR[3] => Mux69.IN208
IR[3] => Mux69.IN209
IR[3] => Mux69.IN210
IR[3] => Mux69.IN211
IR[3] => Mux69.IN212
IR[3] => Mux69.IN213
IR[3] => Mux69.IN214
IR[3] => Mux69.IN215
IR[3] => Mux69.IN216
IR[3] => Mux69.IN217
IR[3] => Mux69.IN218
IR[3] => Mux69.IN219
IR[3] => Mux69.IN220
IR[3] => Mux69.IN221
IR[3] => Mux69.IN222
IR[3] => Mux69.IN223
IR[3] => Mux69.IN224
IR[3] => Mux69.IN225
IR[3] => Mux69.IN226
IR[3] => Mux69.IN227
IR[3] => Mux69.IN228
IR[3] => Mux69.IN229
IR[3] => Mux69.IN230
IR[3] => Mux69.IN231
IR[3] => Mux69.IN232
IR[3] => Mux69.IN233
IR[3] => Mux69.IN234
IR[3] => Mux69.IN235
IR[3] => Mux69.IN236
IR[3] => Mux69.IN237
IR[3] => Mux69.IN238
IR[3] => Mux69.IN239
IR[3] => Mux69.IN240
IR[3] => Mux69.IN241
IR[3] => Mux69.IN242
IR[3] => Mux69.IN243
IR[3] => Mux69.IN244
IR[3] => Mux69.IN245
IR[3] => Mux69.IN246
IR[3] => Mux69.IN247
IR[3] => Mux69.IN248
IR[3] => Mux69.IN249
IR[3] => Mux69.IN250
IR[3] => Mux69.IN251
IR[3] => Mux69.IN252
IR[3] => Mux69.IN253
IR[3] => Mux69.IN254
IR[3] => Mux69.IN255
IR[3] => Mux69.IN256
IR[3] => Mux69.IN257
IR[3] => Mux69.IN258
IR[3] => Mux69.IN259
IR[3] => Mux69.IN260
IR[3] => Mux70.IN260
IR[3] => Mux71.IN260
IR[3] => Mux72.IN259
IR[3] => Mux73.IN260
IR[3] => Mux74.IN260
IR[3] => Mux75.IN260
IR[3] => Mux76.IN260
IR[3] => Mux77.IN260
IR[3] => Mux78.IN260
IR[3] => Mux79.IN260
IR[3] => Mux80.IN260
IR[3] => Mux81.IN260
IR[3] => Mux82.IN260
IR[3] => Mux83.IN260
IR[3] => Mux84.IN260
IR[3] => Mux85.IN260
IR[3] => Mux86.IN260
IR[3] => Mux87.IN260
IR[3] => Mux88.IN260
IR[3] => Mux89.IN260
IR[3] => Mux90.IN260
IR[3] => Mux91.IN260
IR[3] => Mux92.IN260
IR[3] => Mux93.IN260
IR[3] => Mux94.IN260
IR[3] => Mux95.IN260
IR[3] => Mux96.IN260
IR[3] => Mux97.IN260
IR[3] => Mux98.IN260
IR[3] => Mux99.IN30
IR[3] => Mux99.IN31
IR[3] => Mux99.IN32
IR[3] => Mux99.IN33
IR[3] => Mux99.IN34
IR[3] => Mux99.IN35
IR[3] => Mux99.IN36
IR[3] => Mux99.IN37
IR[3] => Mux99.IN38
IR[3] => Mux99.IN39
IR[3] => Mux99.IN40
IR[3] => Mux99.IN41
IR[3] => Mux99.IN42
IR[3] => Mux99.IN43
IR[3] => Mux99.IN44
IR[3] => Mux99.IN45
IR[3] => Mux99.IN46
IR[3] => Mux99.IN47
IR[3] => Mux99.IN48
IR[3] => Mux99.IN49
IR[3] => Mux99.IN50
IR[3] => Mux99.IN51
IR[3] => Mux99.IN52
IR[3] => Mux99.IN53
IR[3] => Mux99.IN54
IR[3] => Mux99.IN55
IR[3] => Mux99.IN56
IR[3] => Mux99.IN57
IR[3] => Mux99.IN58
IR[3] => Mux99.IN59
IR[3] => Mux99.IN60
IR[3] => Mux99.IN61
IR[3] => Mux99.IN62
IR[3] => Mux99.IN63
IR[3] => Mux99.IN64
IR[3] => Mux99.IN65
IR[3] => Mux99.IN66
IR[3] => Mux99.IN67
IR[3] => Mux99.IN68
IR[3] => Mux99.IN69
IR[3] => Mux99.IN70
IR[3] => Mux99.IN71
IR[3] => Mux99.IN72
IR[3] => Mux99.IN73
IR[3] => Mux99.IN74
IR[3] => Mux99.IN75
IR[3] => Mux99.IN76
IR[3] => Mux99.IN77
IR[3] => Mux99.IN78
IR[3] => Mux99.IN79
IR[3] => Mux99.IN80
IR[3] => Mux99.IN81
IR[3] => Mux99.IN82
IR[3] => Mux99.IN83
IR[3] => Mux99.IN84
IR[3] => Mux99.IN85
IR[3] => Mux99.IN86
IR[3] => Mux99.IN87
IR[3] => Mux99.IN88
IR[3] => Mux99.IN89
IR[3] => Mux99.IN90
IR[3] => Mux99.IN91
IR[3] => Mux99.IN92
IR[3] => Mux99.IN93
IR[3] => Mux99.IN94
IR[3] => Mux99.IN95
IR[3] => Mux99.IN96
IR[3] => Mux99.IN97
IR[3] => Mux99.IN98
IR[3] => Mux99.IN99
IR[3] => Mux99.IN100
IR[3] => Mux99.IN101
IR[3] => Mux99.IN102
IR[3] => Mux99.IN103
IR[3] => Mux99.IN104
IR[3] => Mux99.IN105
IR[3] => Mux99.IN106
IR[3] => Mux99.IN107
IR[3] => Mux99.IN108
IR[3] => Mux99.IN109
IR[3] => Mux99.IN110
IR[3] => Mux99.IN111
IR[3] => Mux99.IN112
IR[3] => Mux99.IN113
IR[3] => Mux99.IN114
IR[3] => Mux99.IN115
IR[3] => Mux99.IN116
IR[3] => Mux99.IN117
IR[3] => Mux99.IN118
IR[3] => Mux99.IN119
IR[3] => Mux99.IN120
IR[3] => Mux99.IN121
IR[3] => Mux99.IN122
IR[3] => Mux99.IN123
IR[3] => Mux99.IN124
IR[3] => Mux99.IN125
IR[3] => Mux99.IN126
IR[3] => Mux99.IN127
IR[3] => Mux99.IN128
IR[3] => Mux99.IN129
IR[3] => Mux99.IN130
IR[3] => Mux99.IN131
IR[3] => Mux99.IN132
IR[3] => Mux99.IN133
IR[3] => Mux99.IN134
IR[3] => Mux99.IN135
IR[3] => Mux99.IN136
IR[3] => Mux99.IN137
IR[3] => Mux99.IN138
IR[3] => Mux99.IN139
IR[3] => Mux99.IN140
IR[3] => Mux99.IN141
IR[3] => Mux99.IN142
IR[3] => Mux99.IN143
IR[3] => Mux99.IN144
IR[3] => Mux99.IN145
IR[3] => Mux99.IN146
IR[3] => Mux99.IN147
IR[3] => Mux99.IN148
IR[3] => Mux99.IN149
IR[3] => Mux99.IN150
IR[3] => Mux99.IN151
IR[3] => Mux99.IN152
IR[3] => Mux99.IN153
IR[3] => Mux99.IN154
IR[3] => Mux99.IN155
IR[3] => Mux99.IN156
IR[3] => Mux99.IN157
IR[3] => Mux99.IN158
IR[3] => Mux99.IN159
IR[3] => Mux99.IN160
IR[3] => Mux99.IN161
IR[3] => Mux99.IN162
IR[3] => Mux99.IN163
IR[3] => Mux99.IN164
IR[3] => Mux99.IN165
IR[3] => Mux99.IN166
IR[3] => Mux99.IN167
IR[3] => Mux99.IN168
IR[3] => Mux99.IN169
IR[3] => Mux99.IN170
IR[3] => Mux99.IN171
IR[3] => Mux99.IN172
IR[3] => Mux99.IN173
IR[3] => Mux99.IN174
IR[3] => Mux99.IN175
IR[3] => Mux99.IN176
IR[3] => Mux99.IN177
IR[3] => Mux99.IN178
IR[3] => Mux99.IN179
IR[3] => Mux99.IN180
IR[3] => Mux99.IN181
IR[3] => Mux99.IN182
IR[3] => Mux99.IN183
IR[3] => Mux99.IN184
IR[3] => Mux99.IN185
IR[3] => Mux99.IN186
IR[3] => Mux99.IN187
IR[3] => Mux99.IN188
IR[3] => Mux99.IN189
IR[3] => Mux99.IN190
IR[3] => Mux99.IN191
IR[3] => Mux99.IN192
IR[3] => Mux99.IN193
IR[3] => Mux99.IN194
IR[3] => Mux99.IN195
IR[3] => Mux99.IN196
IR[3] => Mux99.IN197
IR[3] => Mux99.IN198
IR[3] => Mux99.IN199
IR[3] => Mux99.IN200
IR[3] => Mux99.IN201
IR[3] => Mux99.IN202
IR[3] => Mux99.IN203
IR[3] => Mux99.IN204
IR[3] => Mux99.IN205
IR[3] => Mux99.IN206
IR[3] => Mux99.IN207
IR[3] => Mux99.IN208
IR[3] => Mux99.IN209
IR[3] => Mux99.IN210
IR[3] => Mux99.IN211
IR[3] => Mux99.IN212
IR[3] => Mux99.IN213
IR[3] => Mux99.IN214
IR[3] => Mux99.IN215
IR[3] => Mux99.IN216
IR[3] => Mux99.IN217
IR[3] => Mux99.IN218
IR[3] => Mux99.IN219
IR[3] => Mux99.IN220
IR[3] => Mux99.IN221
IR[3] => Mux99.IN222
IR[3] => Mux99.IN223
IR[3] => Mux99.IN224
IR[3] => Mux99.IN225
IR[3] => Mux99.IN226
IR[3] => Mux99.IN227
IR[3] => Mux99.IN228
IR[3] => Mux99.IN229
IR[3] => Mux99.IN230
IR[3] => Mux99.IN231
IR[3] => Mux99.IN232
IR[3] => Mux99.IN233
IR[3] => Mux99.IN234
IR[3] => Mux99.IN235
IR[3] => Mux99.IN236
IR[3] => Mux99.IN237
IR[3] => Mux99.IN238
IR[3] => Mux99.IN239
IR[3] => Mux99.IN240
IR[3] => Mux99.IN241
IR[3] => Mux99.IN242
IR[3] => Mux99.IN243
IR[3] => Mux99.IN244
IR[3] => Mux99.IN245
IR[3] => Mux99.IN246
IR[3] => Mux99.IN247
IR[3] => Mux99.IN248
IR[3] => Mux99.IN249
IR[3] => Mux99.IN250
IR[3] => Mux99.IN251
IR[3] => Mux99.IN252
IR[3] => Mux99.IN253
IR[3] => Mux99.IN254
IR[3] => Mux99.IN255
IR[3] => Mux99.IN256
IR[3] => Mux99.IN257
IR[3] => Mux99.IN258
IR[3] => Mux99.IN259
IR[3] => Mux99.IN260
IR[3] => Mux100.IN260
IR[3] => Mux101.IN260
IR[3] => Mux102.IN260
IR[3] => Mux103.IN260
IR[3] => Mux104.IN260
IR[3] => Mux105.IN260
IR[3] => Mux106.IN260
IR[3] => Mux107.IN260
IR[3] => Mux108.IN66
IR[3] => Mux109.IN260
IR[3] => Mux110.IN260
IR[3] => Mux111.IN260
IR[3] => Mux112.IN260
IR[3] => Mux114.IN260
IR[3] => Mux115.IN260
IR[3] => Mux116.IN260
IR[3] => ALU_Op.DATAA
IR[3] => ALU_Op.DATAA
IR[3] => Mux141.IN6
IR[3] => Mux141.IN7
IR[3] => Mux145.IN1
IR[3] => Mux145.IN2
IR[3] => Mux145.IN3
IR[3] => Mux145.IN4
IR[3] => Mux145.IN5
IR[3] => Mux145.IN6
IR[3] => Mux145.IN7
IR[3] => Mux147.IN7
IR[3] => Mux150.IN1
IR[3] => Mux150.IN2
IR[3] => Mux150.IN3
IR[3] => Mux150.IN4
IR[3] => Mux150.IN5
IR[3] => Mux150.IN6
IR[3] => Mux150.IN7
IR[3] => Mux158.IN1
IR[3] => Mux158.IN2
IR[3] => Mux158.IN3
IR[3] => Mux170.IN1
IR[3] => Mux170.IN2
IR[3] => Mux170.IN3
IR[3] => Mux170.IN4
IR[3] => Mux170.IN5
IR[3] => Mux170.IN6
IR[3] => Mux170.IN7
IR[3] => Mux175.IN1
IR[3] => Mux175.IN2
IR[3] => Mux175.IN3
IR[3] => Mux175.IN4
IR[3] => Mux175.IN5
IR[3] => Mux175.IN6
IR[3] => Mux175.IN7
IR[3] => Set_BusA_To.DATAB
IR[3] => Mux183.IN7
IR[3] => Mux194.IN1
IR[3] => Mux194.IN2
IR[3] => Mux194.IN3
IR[3] => Mux194.IN4
IR[3] => Mux194.IN5
IR[3] => Mux194.IN6
IR[3] => Mux194.IN7
IR[3] => Mux195.IN7
IR[3] => Mux199.IN131
IR[3] => Mux200.IN260
IR[3] => Mux201.IN260
IR[3] => Mux202.IN260
IR[3] => Mux206.IN66
IR[3] => Mux207.IN66
IR[3] => Mux208.IN260
IR[3] => Mux210.IN260
IR[3] => Mux211.IN66
IR[3] => Mux212.IN260
IR[3] => Mux213.IN66
IR[3] => Mux214.IN260
IR[3] => Mux215.IN260
IR[3] => Mux216.IN260
IR[3] => Mux217.IN66
IR[3] => Mux218.IN131
IR[3] => Mux219.IN260
IR[3] => Mux220.IN260
IR[3] => Mux221.IN66
IR[3] => Mux222.IN260
IR[3] => Mux227.IN260
IR[3] => Mux228.IN260
IR[3] => Mux229.IN260
IR[3] => Mux230.IN38
IR[3] => Mux230.IN39
IR[3] => Mux230.IN40
IR[3] => Mux230.IN41
IR[3] => Mux230.IN42
IR[3] => Mux230.IN43
IR[3] => Mux230.IN44
IR[3] => Mux230.IN45
IR[3] => Mux230.IN46
IR[3] => Mux230.IN47
IR[3] => Mux230.IN48
IR[3] => Mux230.IN49
IR[3] => Mux230.IN50
IR[3] => Mux230.IN51
IR[3] => Mux230.IN52
IR[3] => Mux230.IN53
IR[3] => Mux230.IN54
IR[3] => Mux230.IN55
IR[3] => Mux230.IN56
IR[3] => Mux230.IN57
IR[3] => Mux230.IN58
IR[3] => Mux230.IN59
IR[3] => Mux230.IN60
IR[3] => Mux230.IN61
IR[3] => Mux230.IN62
IR[3] => Mux230.IN63
IR[3] => Mux230.IN64
IR[3] => Mux230.IN65
IR[3] => Mux230.IN66
IR[3] => Mux230.IN67
IR[3] => Mux230.IN68
IR[3] => Mux230.IN69
IR[3] => Mux230.IN70
IR[3] => Mux230.IN71
IR[3] => Mux230.IN72
IR[3] => Mux230.IN73
IR[3] => Mux230.IN74
IR[3] => Mux230.IN75
IR[3] => Mux230.IN76
IR[3] => Mux230.IN77
IR[3] => Mux230.IN78
IR[3] => Mux230.IN79
IR[3] => Mux230.IN80
IR[3] => Mux230.IN81
IR[3] => Mux230.IN82
IR[3] => Mux230.IN83
IR[3] => Mux230.IN84
IR[3] => Mux230.IN85
IR[3] => Mux230.IN86
IR[3] => Mux230.IN87
IR[3] => Mux230.IN88
IR[3] => Mux230.IN89
IR[3] => Mux230.IN90
IR[3] => Mux230.IN91
IR[3] => Mux230.IN92
IR[3] => Mux230.IN93
IR[3] => Mux230.IN94
IR[3] => Mux230.IN95
IR[3] => Mux230.IN96
IR[3] => Mux230.IN97
IR[3] => Mux230.IN98
IR[3] => Mux230.IN99
IR[3] => Mux230.IN100
IR[3] => Mux230.IN101
IR[3] => Mux230.IN102
IR[3] => Mux230.IN103
IR[3] => Mux230.IN104
IR[3] => Mux230.IN105
IR[3] => Mux230.IN106
IR[3] => Mux230.IN107
IR[3] => Mux230.IN108
IR[3] => Mux230.IN109
IR[3] => Mux230.IN110
IR[3] => Mux230.IN111
IR[3] => Mux230.IN112
IR[3] => Mux230.IN113
IR[3] => Mux230.IN114
IR[3] => Mux230.IN115
IR[3] => Mux230.IN116
IR[3] => Mux230.IN117
IR[3] => Mux230.IN118
IR[3] => Mux230.IN119
IR[3] => Mux230.IN120
IR[3] => Mux230.IN121
IR[3] => Mux230.IN122
IR[3] => Mux230.IN123
IR[3] => Mux230.IN124
IR[3] => Mux230.IN125
IR[3] => Mux230.IN126
IR[3] => Mux230.IN127
IR[3] => Mux230.IN128
IR[3] => Mux230.IN129
IR[3] => Mux230.IN130
IR[3] => Mux230.IN131
IR[3] => Mux230.IN132
IR[3] => Mux230.IN133
IR[3] => Mux230.IN134
IR[3] => Mux230.IN135
IR[3] => Mux230.IN136
IR[3] => Mux230.IN137
IR[3] => Mux230.IN138
IR[3] => Mux230.IN139
IR[3] => Mux230.IN140
IR[3] => Mux230.IN141
IR[3] => Mux230.IN142
IR[3] => Mux230.IN143
IR[3] => Mux230.IN144
IR[3] => Mux230.IN145
IR[3] => Mux230.IN146
IR[3] => Mux230.IN147
IR[3] => Mux230.IN148
IR[3] => Mux230.IN149
IR[3] => Mux230.IN150
IR[3] => Mux230.IN151
IR[3] => Mux230.IN152
IR[3] => Mux230.IN153
IR[3] => Mux230.IN154
IR[3] => Mux230.IN155
IR[3] => Mux230.IN156
IR[3] => Mux230.IN157
IR[3] => Mux230.IN158
IR[3] => Mux230.IN159
IR[3] => Mux230.IN160
IR[3] => Mux230.IN161
IR[3] => Mux230.IN162
IR[3] => Mux230.IN163
IR[3] => Mux230.IN164
IR[3] => Mux230.IN165
IR[3] => Mux230.IN166
IR[3] => Mux230.IN167
IR[3] => Mux230.IN168
IR[3] => Mux230.IN169
IR[3] => Mux230.IN170
IR[3] => Mux230.IN171
IR[3] => Mux230.IN172
IR[3] => Mux230.IN173
IR[3] => Mux230.IN174
IR[3] => Mux230.IN175
IR[3] => Mux230.IN176
IR[3] => Mux230.IN177
IR[3] => Mux230.IN178
IR[3] => Mux230.IN179
IR[3] => Mux230.IN180
IR[3] => Mux230.IN181
IR[3] => Mux230.IN182
IR[3] => Mux230.IN183
IR[3] => Mux230.IN184
IR[3] => Mux230.IN185
IR[3] => Mux230.IN186
IR[3] => Mux230.IN187
IR[3] => Mux230.IN188
IR[3] => Mux230.IN189
IR[3] => Mux230.IN190
IR[3] => Mux230.IN191
IR[3] => Mux230.IN192
IR[3] => Mux230.IN193
IR[3] => Mux230.IN194
IR[3] => Mux230.IN195
IR[3] => Mux230.IN196
IR[3] => Mux230.IN197
IR[3] => Mux230.IN198
IR[3] => Mux230.IN199
IR[3] => Mux230.IN200
IR[3] => Mux230.IN201
IR[3] => Mux230.IN202
IR[3] => Mux230.IN203
IR[3] => Mux230.IN204
IR[3] => Mux230.IN205
IR[3] => Mux230.IN206
IR[3] => Mux230.IN207
IR[3] => Mux230.IN208
IR[3] => Mux230.IN209
IR[3] => Mux230.IN210
IR[3] => Mux230.IN211
IR[3] => Mux230.IN212
IR[3] => Mux230.IN213
IR[3] => Mux230.IN214
IR[3] => Mux230.IN215
IR[3] => Mux230.IN216
IR[3] => Mux230.IN217
IR[3] => Mux230.IN218
IR[3] => Mux230.IN219
IR[3] => Mux230.IN220
IR[3] => Mux230.IN221
IR[3] => Mux230.IN222
IR[3] => Mux230.IN223
IR[3] => Mux230.IN224
IR[3] => Mux230.IN225
IR[3] => Mux230.IN226
IR[3] => Mux230.IN227
IR[3] => Mux230.IN228
IR[3] => Mux230.IN229
IR[3] => Mux230.IN230
IR[3] => Mux230.IN231
IR[3] => Mux230.IN232
IR[3] => Mux230.IN233
IR[3] => Mux230.IN234
IR[3] => Mux230.IN235
IR[3] => Mux230.IN236
IR[3] => Mux230.IN237
IR[3] => Mux230.IN238
IR[3] => Mux230.IN239
IR[3] => Mux230.IN240
IR[3] => Mux230.IN241
IR[3] => Mux230.IN242
IR[3] => Mux230.IN243
IR[3] => Mux230.IN244
IR[3] => Mux230.IN245
IR[3] => Mux230.IN246
IR[3] => Mux230.IN247
IR[3] => Mux230.IN248
IR[3] => Mux230.IN249
IR[3] => Mux230.IN250
IR[3] => Mux230.IN251
IR[3] => Mux230.IN252
IR[3] => Mux230.IN253
IR[3] => Mux230.IN254
IR[3] => Mux230.IN255
IR[3] => Mux230.IN256
IR[3] => Mux230.IN257
IR[3] => Mux230.IN258
IR[3] => Mux230.IN259
IR[3] => Mux230.IN260
IR[3] => Mux232.IN260
IR[3] => Mux233.IN260
IR[3] => Mux237.IN131
IR[3] => Mux238.IN260
IR[3] => Mux239.IN260
IR[3] => Mux240.IN260
IR[3] => Equal3.IN0
IR[3] => Equal5.IN5
IR[3] => Equal7.IN2
IR[4] => Mux1.IN7
IR[4] => Set_BusA_To.DATAA
IR[4] => Mux45.IN5
IR[4] => Mux61.IN259
IR[4] => Mux62.IN154
IR[4] => Mux63.IN154
IR[4] => Mux64.IN154
IR[4] => Mux65.IN259
IR[4] => Mux67.IN259
IR[4] => Mux68.IN196
IR[4] => Mux68.IN197
IR[4] => Mux68.IN198
IR[4] => Mux68.IN199
IR[4] => Mux68.IN200
IR[4] => Mux68.IN201
IR[4] => Mux68.IN202
IR[4] => Mux68.IN203
IR[4] => Mux68.IN204
IR[4] => Mux68.IN205
IR[4] => Mux68.IN206
IR[4] => Mux68.IN207
IR[4] => Mux68.IN208
IR[4] => Mux68.IN209
IR[4] => Mux68.IN210
IR[4] => Mux68.IN211
IR[4] => Mux68.IN212
IR[4] => Mux68.IN213
IR[4] => Mux68.IN214
IR[4] => Mux68.IN215
IR[4] => Mux68.IN216
IR[4] => Mux68.IN217
IR[4] => Mux68.IN218
IR[4] => Mux68.IN219
IR[4] => Mux68.IN220
IR[4] => Mux68.IN221
IR[4] => Mux68.IN222
IR[4] => Mux68.IN223
IR[4] => Mux68.IN224
IR[4] => Mux68.IN225
IR[4] => Mux68.IN226
IR[4] => Mux68.IN227
IR[4] => Mux68.IN228
IR[4] => Mux68.IN229
IR[4] => Mux68.IN230
IR[4] => Mux68.IN231
IR[4] => Mux68.IN232
IR[4] => Mux68.IN233
IR[4] => Mux68.IN234
IR[4] => Mux68.IN235
IR[4] => Mux68.IN236
IR[4] => Mux68.IN237
IR[4] => Mux68.IN238
IR[4] => Mux68.IN239
IR[4] => Mux68.IN240
IR[4] => Mux68.IN241
IR[4] => Mux68.IN242
IR[4] => Mux68.IN243
IR[4] => Mux68.IN244
IR[4] => Mux68.IN245
IR[4] => Mux68.IN246
IR[4] => Mux68.IN247
IR[4] => Mux68.IN248
IR[4] => Mux68.IN249
IR[4] => Mux68.IN250
IR[4] => Mux68.IN251
IR[4] => Mux68.IN252
IR[4] => Mux68.IN253
IR[4] => Mux68.IN254
IR[4] => Mux68.IN255
IR[4] => Mux68.IN256
IR[4] => Mux68.IN257
IR[4] => Mux68.IN258
IR[4] => Mux68.IN259
IR[4] => Mux69.IN196
IR[4] => Mux70.IN259
IR[4] => Mux71.IN259
IR[4] => Mux72.IN258
IR[4] => Mux73.IN259
IR[4] => Mux74.IN259
IR[4] => Mux75.IN259
IR[4] => Mux76.IN259
IR[4] => Mux77.IN259
IR[4] => Mux78.IN259
IR[4] => Mux79.IN259
IR[4] => Mux80.IN259
IR[4] => Mux81.IN259
IR[4] => Mux82.IN259
IR[4] => Mux83.IN259
IR[4] => Mux84.IN259
IR[4] => Mux85.IN259
IR[4] => Mux86.IN259
IR[4] => Mux87.IN259
IR[4] => Mux88.IN259
IR[4] => Mux89.IN259
IR[4] => Mux90.IN251
IR[4] => Mux90.IN252
IR[4] => Mux90.IN253
IR[4] => Mux90.IN254
IR[4] => Mux90.IN255
IR[4] => Mux90.IN256
IR[4] => Mux90.IN257
IR[4] => Mux90.IN258
IR[4] => Mux90.IN259
IR[4] => Mux91.IN259
IR[4] => Mux92.IN259
IR[4] => Mux93.IN259
IR[4] => Mux94.IN259
IR[4] => Mux95.IN259
IR[4] => Mux96.IN259
IR[4] => Mux97.IN259
IR[4] => Mux98.IN29
IR[4] => Mux98.IN30
IR[4] => Mux98.IN31
IR[4] => Mux98.IN32
IR[4] => Mux98.IN33
IR[4] => Mux98.IN34
IR[4] => Mux98.IN35
IR[4] => Mux98.IN36
IR[4] => Mux98.IN37
IR[4] => Mux98.IN38
IR[4] => Mux98.IN39
IR[4] => Mux98.IN40
IR[4] => Mux98.IN41
IR[4] => Mux98.IN42
IR[4] => Mux98.IN43
IR[4] => Mux98.IN44
IR[4] => Mux98.IN45
IR[4] => Mux98.IN46
IR[4] => Mux98.IN47
IR[4] => Mux98.IN48
IR[4] => Mux98.IN49
IR[4] => Mux98.IN50
IR[4] => Mux98.IN51
IR[4] => Mux98.IN52
IR[4] => Mux98.IN53
IR[4] => Mux98.IN54
IR[4] => Mux98.IN55
IR[4] => Mux98.IN56
IR[4] => Mux98.IN57
IR[4] => Mux98.IN58
IR[4] => Mux98.IN59
IR[4] => Mux98.IN60
IR[4] => Mux98.IN61
IR[4] => Mux98.IN62
IR[4] => Mux98.IN63
IR[4] => Mux98.IN64
IR[4] => Mux98.IN65
IR[4] => Mux98.IN66
IR[4] => Mux98.IN67
IR[4] => Mux98.IN68
IR[4] => Mux98.IN69
IR[4] => Mux98.IN70
IR[4] => Mux98.IN71
IR[4] => Mux98.IN72
IR[4] => Mux98.IN73
IR[4] => Mux98.IN74
IR[4] => Mux98.IN75
IR[4] => Mux98.IN76
IR[4] => Mux98.IN77
IR[4] => Mux98.IN78
IR[4] => Mux98.IN79
IR[4] => Mux98.IN80
IR[4] => Mux98.IN81
IR[4] => Mux98.IN82
IR[4] => Mux98.IN83
IR[4] => Mux98.IN84
IR[4] => Mux98.IN85
IR[4] => Mux98.IN86
IR[4] => Mux98.IN87
IR[4] => Mux98.IN88
IR[4] => Mux98.IN89
IR[4] => Mux98.IN90
IR[4] => Mux98.IN91
IR[4] => Mux98.IN92
IR[4] => Mux98.IN93
IR[4] => Mux98.IN94
IR[4] => Mux98.IN95
IR[4] => Mux98.IN96
IR[4] => Mux98.IN97
IR[4] => Mux98.IN98
IR[4] => Mux98.IN99
IR[4] => Mux98.IN100
IR[4] => Mux98.IN101
IR[4] => Mux98.IN102
IR[4] => Mux98.IN103
IR[4] => Mux98.IN104
IR[4] => Mux98.IN105
IR[4] => Mux98.IN106
IR[4] => Mux98.IN107
IR[4] => Mux98.IN108
IR[4] => Mux98.IN109
IR[4] => Mux98.IN110
IR[4] => Mux98.IN111
IR[4] => Mux98.IN112
IR[4] => Mux98.IN113
IR[4] => Mux98.IN114
IR[4] => Mux98.IN115
IR[4] => Mux98.IN116
IR[4] => Mux98.IN117
IR[4] => Mux98.IN118
IR[4] => Mux98.IN119
IR[4] => Mux98.IN120
IR[4] => Mux98.IN121
IR[4] => Mux98.IN122
IR[4] => Mux98.IN123
IR[4] => Mux98.IN124
IR[4] => Mux98.IN125
IR[4] => Mux98.IN126
IR[4] => Mux98.IN127
IR[4] => Mux98.IN128
IR[4] => Mux98.IN129
IR[4] => Mux98.IN130
IR[4] => Mux98.IN131
IR[4] => Mux98.IN132
IR[4] => Mux98.IN133
IR[4] => Mux98.IN134
IR[4] => Mux98.IN135
IR[4] => Mux98.IN136
IR[4] => Mux98.IN137
IR[4] => Mux98.IN138
IR[4] => Mux98.IN139
IR[4] => Mux98.IN140
IR[4] => Mux98.IN141
IR[4] => Mux98.IN142
IR[4] => Mux98.IN143
IR[4] => Mux98.IN144
IR[4] => Mux98.IN145
IR[4] => Mux98.IN146
IR[4] => Mux98.IN147
IR[4] => Mux98.IN148
IR[4] => Mux98.IN149
IR[4] => Mux98.IN150
IR[4] => Mux98.IN151
IR[4] => Mux98.IN152
IR[4] => Mux98.IN153
IR[4] => Mux98.IN154
IR[4] => Mux98.IN155
IR[4] => Mux98.IN156
IR[4] => Mux98.IN157
IR[4] => Mux98.IN158
IR[4] => Mux98.IN159
IR[4] => Mux98.IN160
IR[4] => Mux98.IN161
IR[4] => Mux98.IN162
IR[4] => Mux98.IN163
IR[4] => Mux98.IN164
IR[4] => Mux98.IN165
IR[4] => Mux98.IN166
IR[4] => Mux98.IN167
IR[4] => Mux98.IN168
IR[4] => Mux98.IN169
IR[4] => Mux98.IN170
IR[4] => Mux98.IN171
IR[4] => Mux98.IN172
IR[4] => Mux98.IN173
IR[4] => Mux98.IN174
IR[4] => Mux98.IN175
IR[4] => Mux98.IN176
IR[4] => Mux98.IN177
IR[4] => Mux98.IN178
IR[4] => Mux98.IN179
IR[4] => Mux98.IN180
IR[4] => Mux98.IN181
IR[4] => Mux98.IN182
IR[4] => Mux98.IN183
IR[4] => Mux98.IN184
IR[4] => Mux98.IN185
IR[4] => Mux98.IN186
IR[4] => Mux98.IN187
IR[4] => Mux98.IN188
IR[4] => Mux98.IN189
IR[4] => Mux98.IN190
IR[4] => Mux98.IN191
IR[4] => Mux98.IN192
IR[4] => Mux98.IN193
IR[4] => Mux98.IN194
IR[4] => Mux98.IN195
IR[4] => Mux98.IN196
IR[4] => Mux98.IN197
IR[4] => Mux98.IN198
IR[4] => Mux98.IN199
IR[4] => Mux98.IN200
IR[4] => Mux98.IN201
IR[4] => Mux98.IN202
IR[4] => Mux98.IN203
IR[4] => Mux98.IN204
IR[4] => Mux98.IN205
IR[4] => Mux98.IN206
IR[4] => Mux98.IN207
IR[4] => Mux98.IN208
IR[4] => Mux98.IN209
IR[4] => Mux98.IN210
IR[4] => Mux98.IN211
IR[4] => Mux98.IN212
IR[4] => Mux98.IN213
IR[4] => Mux98.IN214
IR[4] => Mux98.IN215
IR[4] => Mux98.IN216
IR[4] => Mux98.IN217
IR[4] => Mux98.IN218
IR[4] => Mux98.IN219
IR[4] => Mux98.IN220
IR[4] => Mux98.IN221
IR[4] => Mux98.IN222
IR[4] => Mux98.IN223
IR[4] => Mux98.IN224
IR[4] => Mux98.IN225
IR[4] => Mux98.IN226
IR[4] => Mux98.IN227
IR[4] => Mux98.IN228
IR[4] => Mux98.IN229
IR[4] => Mux98.IN230
IR[4] => Mux98.IN231
IR[4] => Mux98.IN232
IR[4] => Mux98.IN233
IR[4] => Mux98.IN234
IR[4] => Mux98.IN235
IR[4] => Mux98.IN236
IR[4] => Mux98.IN237
IR[4] => Mux98.IN238
IR[4] => Mux98.IN239
IR[4] => Mux98.IN240
IR[4] => Mux98.IN241
IR[4] => Mux98.IN242
IR[4] => Mux98.IN243
IR[4] => Mux98.IN244
IR[4] => Mux98.IN245
IR[4] => Mux98.IN246
IR[4] => Mux98.IN247
IR[4] => Mux98.IN248
IR[4] => Mux98.IN249
IR[4] => Mux98.IN250
IR[4] => Mux98.IN251
IR[4] => Mux98.IN252
IR[4] => Mux98.IN253
IR[4] => Mux98.IN254
IR[4] => Mux98.IN255
IR[4] => Mux98.IN256
IR[4] => Mux98.IN257
IR[4] => Mux98.IN258
IR[4] => Mux98.IN259
IR[4] => Mux99.IN29
IR[4] => Mux100.IN259
IR[4] => Mux101.IN259
IR[4] => Mux102.IN259
IR[4] => Mux103.IN259
IR[4] => Mux104.IN259
IR[4] => Mux105.IN259
IR[4] => Mux106.IN259
IR[4] => Mux107.IN259
IR[4] => Mux109.IN259
IR[4] => Mux110.IN259
IR[4] => Mux111.IN259
IR[4] => Mux112.IN259
IR[4] => Mux114.IN259
IR[4] => Mux115.IN259
IR[4] => Mux116.IN259
IR[4] => ALU_Op.DATAA
IR[4] => ALU_Op.DATAA
IR[4] => Set_BusA_To.DATAA
IR[4] => Mux144.IN1
IR[4] => Mux144.IN2
IR[4] => Mux144.IN3
IR[4] => Mux144.IN4
IR[4] => Mux144.IN5
IR[4] => Mux144.IN6
IR[4] => Mux144.IN7
IR[4] => Mux149.IN1
IR[4] => Mux149.IN2
IR[4] => Mux149.IN3
IR[4] => Mux149.IN4
IR[4] => Mux149.IN5
IR[4] => Mux149.IN6
IR[4] => Mux149.IN7
IR[4] => Mux152.IN5
IR[4] => Mux153.IN5
IR[4] => Mux154.IN5
IR[4] => Mux155.IN2
IR[4] => Mux155.IN3
IR[4] => Mux155.IN4
IR[4] => Mux155.IN5
IR[4] => Mux157.IN1
IR[4] => Mux157.IN2
IR[4] => Mux157.IN3
IR[4] => Mux166.IN1
IR[4] => Mux166.IN2
IR[4] => Mux166.IN3
IR[4] => Mux169.IN1
IR[4] => Mux169.IN2
IR[4] => Mux169.IN3
IR[4] => Mux169.IN4
IR[4] => Mux169.IN5
IR[4] => Mux169.IN6
IR[4] => Mux169.IN7
IR[4] => Mux174.IN1
IR[4] => Mux174.IN2
IR[4] => Mux174.IN3
IR[4] => Mux174.IN4
IR[4] => Mux174.IN5
IR[4] => Mux174.IN6
IR[4] => Mux174.IN7
IR[4] => Set_BusA_To.DATAB
IR[4] => Mux182.IN7
IR[4] => Mux193.IN1
IR[4] => Mux193.IN2
IR[4] => Mux193.IN3
IR[4] => Mux193.IN4
IR[4] => Mux193.IN5
IR[4] => Mux193.IN6
IR[4] => Mux193.IN7
IR[4] => Mux198.IN131
IR[4] => Mux200.IN259
IR[4] => Mux201.IN259
IR[4] => Mux202.IN259
IR[4] => Mux203.IN131
IR[4] => Mux205.IN131
IR[4] => Mux208.IN259
IR[4] => Mux210.IN259
IR[4] => Mux212.IN259
IR[4] => Mux214.IN259
IR[4] => Mux215.IN259
IR[4] => Mux216.IN259
IR[4] => Mux219.IN259
IR[4] => Mux220.IN259
IR[4] => Mux222.IN259
IR[4] => Mux227.IN259
IR[4] => Mux228.IN259
IR[4] => Mux229.IN37
IR[4] => Mux229.IN38
IR[4] => Mux229.IN39
IR[4] => Mux229.IN40
IR[4] => Mux229.IN41
IR[4] => Mux229.IN42
IR[4] => Mux229.IN43
IR[4] => Mux229.IN44
IR[4] => Mux229.IN45
IR[4] => Mux229.IN46
IR[4] => Mux229.IN47
IR[4] => Mux229.IN48
IR[4] => Mux229.IN49
IR[4] => Mux229.IN50
IR[4] => Mux229.IN51
IR[4] => Mux229.IN52
IR[4] => Mux229.IN53
IR[4] => Mux229.IN54
IR[4] => Mux229.IN55
IR[4] => Mux229.IN56
IR[4] => Mux229.IN57
IR[4] => Mux229.IN58
IR[4] => Mux229.IN59
IR[4] => Mux229.IN60
IR[4] => Mux229.IN61
IR[4] => Mux229.IN62
IR[4] => Mux229.IN63
IR[4] => Mux229.IN64
IR[4] => Mux229.IN65
IR[4] => Mux229.IN66
IR[4] => Mux229.IN67
IR[4] => Mux229.IN68
IR[4] => Mux229.IN69
IR[4] => Mux229.IN70
IR[4] => Mux229.IN71
IR[4] => Mux229.IN72
IR[4] => Mux229.IN73
IR[4] => Mux229.IN74
IR[4] => Mux229.IN75
IR[4] => Mux229.IN76
IR[4] => Mux229.IN77
IR[4] => Mux229.IN78
IR[4] => Mux229.IN79
IR[4] => Mux229.IN80
IR[4] => Mux229.IN81
IR[4] => Mux229.IN82
IR[4] => Mux229.IN83
IR[4] => Mux229.IN84
IR[4] => Mux229.IN85
IR[4] => Mux229.IN86
IR[4] => Mux229.IN87
IR[4] => Mux229.IN88
IR[4] => Mux229.IN89
IR[4] => Mux229.IN90
IR[4] => Mux229.IN91
IR[4] => Mux229.IN92
IR[4] => Mux229.IN93
IR[4] => Mux229.IN94
IR[4] => Mux229.IN95
IR[4] => Mux229.IN96
IR[4] => Mux229.IN97
IR[4] => Mux229.IN98
IR[4] => Mux229.IN99
IR[4] => Mux229.IN100
IR[4] => Mux229.IN101
IR[4] => Mux229.IN102
IR[4] => Mux229.IN103
IR[4] => Mux229.IN104
IR[4] => Mux229.IN105
IR[4] => Mux229.IN106
IR[4] => Mux229.IN107
IR[4] => Mux229.IN108
IR[4] => Mux229.IN109
IR[4] => Mux229.IN110
IR[4] => Mux229.IN111
IR[4] => Mux229.IN112
IR[4] => Mux229.IN113
IR[4] => Mux229.IN114
IR[4] => Mux229.IN115
IR[4] => Mux229.IN116
IR[4] => Mux229.IN117
IR[4] => Mux229.IN118
IR[4] => Mux229.IN119
IR[4] => Mux229.IN120
IR[4] => Mux229.IN121
IR[4] => Mux229.IN122
IR[4] => Mux229.IN123
IR[4] => Mux229.IN124
IR[4] => Mux229.IN125
IR[4] => Mux229.IN126
IR[4] => Mux229.IN127
IR[4] => Mux229.IN128
IR[4] => Mux229.IN129
IR[4] => Mux229.IN130
IR[4] => Mux229.IN131
IR[4] => Mux229.IN132
IR[4] => Mux229.IN133
IR[4] => Mux229.IN134
IR[4] => Mux229.IN135
IR[4] => Mux229.IN136
IR[4] => Mux229.IN137
IR[4] => Mux229.IN138
IR[4] => Mux229.IN139
IR[4] => Mux229.IN140
IR[4] => Mux229.IN141
IR[4] => Mux229.IN142
IR[4] => Mux229.IN143
IR[4] => Mux229.IN144
IR[4] => Mux229.IN145
IR[4] => Mux229.IN146
IR[4] => Mux229.IN147
IR[4] => Mux229.IN148
IR[4] => Mux229.IN149
IR[4] => Mux229.IN150
IR[4] => Mux229.IN151
IR[4] => Mux229.IN152
IR[4] => Mux229.IN153
IR[4] => Mux229.IN154
IR[4] => Mux229.IN155
IR[4] => Mux229.IN156
IR[4] => Mux229.IN157
IR[4] => Mux229.IN158
IR[4] => Mux229.IN159
IR[4] => Mux229.IN160
IR[4] => Mux229.IN161
IR[4] => Mux229.IN162
IR[4] => Mux229.IN163
IR[4] => Mux229.IN164
IR[4] => Mux229.IN165
IR[4] => Mux229.IN166
IR[4] => Mux229.IN167
IR[4] => Mux229.IN168
IR[4] => Mux229.IN169
IR[4] => Mux229.IN170
IR[4] => Mux229.IN171
IR[4] => Mux229.IN172
IR[4] => Mux229.IN173
IR[4] => Mux229.IN174
IR[4] => Mux229.IN175
IR[4] => Mux229.IN176
IR[4] => Mux229.IN177
IR[4] => Mux229.IN178
IR[4] => Mux229.IN179
IR[4] => Mux229.IN180
IR[4] => Mux229.IN181
IR[4] => Mux229.IN182
IR[4] => Mux229.IN183
IR[4] => Mux229.IN184
IR[4] => Mux229.IN185
IR[4] => Mux229.IN186
IR[4] => Mux229.IN187
IR[4] => Mux229.IN188
IR[4] => Mux229.IN189
IR[4] => Mux229.IN190
IR[4] => Mux229.IN191
IR[4] => Mux229.IN192
IR[4] => Mux229.IN193
IR[4] => Mux229.IN194
IR[4] => Mux229.IN195
IR[4] => Mux229.IN196
IR[4] => Mux229.IN197
IR[4] => Mux229.IN198
IR[4] => Mux229.IN199
IR[4] => Mux229.IN200
IR[4] => Mux229.IN201
IR[4] => Mux229.IN202
IR[4] => Mux229.IN203
IR[4] => Mux229.IN204
IR[4] => Mux229.IN205
IR[4] => Mux229.IN206
IR[4] => Mux229.IN207
IR[4] => Mux229.IN208
IR[4] => Mux229.IN209
IR[4] => Mux229.IN210
IR[4] => Mux229.IN211
IR[4] => Mux229.IN212
IR[4] => Mux229.IN213
IR[4] => Mux229.IN214
IR[4] => Mux229.IN215
IR[4] => Mux229.IN216
IR[4] => Mux229.IN217
IR[4] => Mux229.IN218
IR[4] => Mux229.IN219
IR[4] => Mux229.IN220
IR[4] => Mux229.IN221
IR[4] => Mux229.IN222
IR[4] => Mux229.IN223
IR[4] => Mux229.IN224
IR[4] => Mux229.IN225
IR[4] => Mux229.IN226
IR[4] => Mux229.IN227
IR[4] => Mux229.IN228
IR[4] => Mux229.IN229
IR[4] => Mux229.IN230
IR[4] => Mux229.IN231
IR[4] => Mux229.IN232
IR[4] => Mux229.IN233
IR[4] => Mux229.IN234
IR[4] => Mux229.IN235
IR[4] => Mux229.IN236
IR[4] => Mux229.IN237
IR[4] => Mux229.IN238
IR[4] => Mux229.IN239
IR[4] => Mux229.IN240
IR[4] => Mux229.IN241
IR[4] => Mux229.IN242
IR[4] => Mux229.IN243
IR[4] => Mux229.IN244
IR[4] => Mux229.IN245
IR[4] => Mux229.IN246
IR[4] => Mux229.IN247
IR[4] => Mux229.IN248
IR[4] => Mux229.IN249
IR[4] => Mux229.IN250
IR[4] => Mux229.IN251
IR[4] => Mux229.IN252
IR[4] => Mux229.IN253
IR[4] => Mux229.IN254
IR[4] => Mux229.IN255
IR[4] => Mux229.IN256
IR[4] => Mux229.IN257
IR[4] => Mux229.IN258
IR[4] => Mux229.IN259
IR[4] => Mux230.IN37
IR[4] => Mux232.IN259
IR[4] => Mux233.IN259
IR[4] => Mux237.IN130
IR[4] => Mux238.IN259
IR[4] => Mux239.IN259
IR[4] => Mux240.IN259
IR[4] => Equal2.IN1
IR[4] => Equal3.IN2
IR[4] => Equal5.IN1
IR[4] => Equal7.IN5
IR[5] => Mux0.IN7
IR[5] => Set_BusA_To.DATAA
IR[5] => Mux45.IN4
IR[5] => Mux61.IN258
IR[5] => Mux62.IN153
IR[5] => Mux63.IN153
IR[5] => Mux64.IN153
IR[5] => Mux65.IN258
IR[5] => Mux67.IN195
IR[5] => Mux67.IN196
IR[5] => Mux67.IN197
IR[5] => Mux67.IN198
IR[5] => Mux67.IN199
IR[5] => Mux67.IN200
IR[5] => Mux67.IN201
IR[5] => Mux67.IN202
IR[5] => Mux67.IN203
IR[5] => Mux67.IN204
IR[5] => Mux67.IN205
IR[5] => Mux67.IN206
IR[5] => Mux67.IN207
IR[5] => Mux67.IN208
IR[5] => Mux67.IN209
IR[5] => Mux67.IN210
IR[5] => Mux67.IN211
IR[5] => Mux67.IN212
IR[5] => Mux67.IN213
IR[5] => Mux67.IN214
IR[5] => Mux67.IN215
IR[5] => Mux67.IN216
IR[5] => Mux67.IN217
IR[5] => Mux67.IN218
IR[5] => Mux67.IN219
IR[5] => Mux67.IN220
IR[5] => Mux67.IN221
IR[5] => Mux67.IN222
IR[5] => Mux67.IN223
IR[5] => Mux67.IN224
IR[5] => Mux67.IN225
IR[5] => Mux67.IN226
IR[5] => Mux67.IN227
IR[5] => Mux67.IN228
IR[5] => Mux67.IN229
IR[5] => Mux67.IN230
IR[5] => Mux67.IN231
IR[5] => Mux67.IN232
IR[5] => Mux67.IN233
IR[5] => Mux67.IN234
IR[5] => Mux67.IN235
IR[5] => Mux67.IN236
IR[5] => Mux67.IN237
IR[5] => Mux67.IN238
IR[5] => Mux67.IN239
IR[5] => Mux67.IN240
IR[5] => Mux67.IN241
IR[5] => Mux67.IN242
IR[5] => Mux67.IN243
IR[5] => Mux67.IN244
IR[5] => Mux67.IN245
IR[5] => Mux67.IN246
IR[5] => Mux67.IN247
IR[5] => Mux67.IN248
IR[5] => Mux67.IN249
IR[5] => Mux67.IN250
IR[5] => Mux67.IN251
IR[5] => Mux67.IN252
IR[5] => Mux67.IN253
IR[5] => Mux67.IN254
IR[5] => Mux67.IN255
IR[5] => Mux67.IN256
IR[5] => Mux67.IN257
IR[5] => Mux67.IN258
IR[5] => Mux68.IN195
IR[5] => Mux69.IN195
IR[5] => Mux70.IN258
IR[5] => Mux71.IN258
IR[5] => Mux72.IN257
IR[5] => Mux73.IN258
IR[5] => Mux74.IN258
IR[5] => Mux75.IN258
IR[5] => Mux76.IN258
IR[5] => Mux77.IN258
IR[5] => Mux78.IN258
IR[5] => Mux79.IN258
IR[5] => Mux80.IN258
IR[5] => Mux81.IN258
IR[5] => Mux82.IN258
IR[5] => Mux83.IN258
IR[5] => Mux84.IN258
IR[5] => Mux85.IN258
IR[5] => Mux86.IN258
IR[5] => Mux87.IN258
IR[5] => Mux88.IN258
IR[5] => Mux89.IN250
IR[5] => Mux89.IN251
IR[5] => Mux89.IN252
IR[5] => Mux89.IN253
IR[5] => Mux89.IN254
IR[5] => Mux89.IN255
IR[5] => Mux89.IN256
IR[5] => Mux89.IN257
IR[5] => Mux89.IN258
IR[5] => Mux90.IN250
IR[5] => Mux91.IN258
IR[5] => Mux92.IN258
IR[5] => Mux93.IN258
IR[5] => Mux94.IN258
IR[5] => Mux95.IN258
IR[5] => Mux96.IN258
IR[5] => Mux97.IN28
IR[5] => Mux97.IN29
IR[5] => Mux97.IN30
IR[5] => Mux97.IN31
IR[5] => Mux97.IN32
IR[5] => Mux97.IN33
IR[5] => Mux97.IN34
IR[5] => Mux97.IN35
IR[5] => Mux97.IN36
IR[5] => Mux97.IN37
IR[5] => Mux97.IN38
IR[5] => Mux97.IN39
IR[5] => Mux97.IN40
IR[5] => Mux97.IN41
IR[5] => Mux97.IN42
IR[5] => Mux97.IN43
IR[5] => Mux97.IN44
IR[5] => Mux97.IN45
IR[5] => Mux97.IN46
IR[5] => Mux97.IN47
IR[5] => Mux97.IN48
IR[5] => Mux97.IN49
IR[5] => Mux97.IN50
IR[5] => Mux97.IN51
IR[5] => Mux97.IN52
IR[5] => Mux97.IN53
IR[5] => Mux97.IN54
IR[5] => Mux97.IN55
IR[5] => Mux97.IN56
IR[5] => Mux97.IN57
IR[5] => Mux97.IN58
IR[5] => Mux97.IN59
IR[5] => Mux97.IN60
IR[5] => Mux97.IN61
IR[5] => Mux97.IN62
IR[5] => Mux97.IN63
IR[5] => Mux97.IN64
IR[5] => Mux97.IN65
IR[5] => Mux97.IN66
IR[5] => Mux97.IN67
IR[5] => Mux97.IN68
IR[5] => Mux97.IN69
IR[5] => Mux97.IN70
IR[5] => Mux97.IN71
IR[5] => Mux97.IN72
IR[5] => Mux97.IN73
IR[5] => Mux97.IN74
IR[5] => Mux97.IN75
IR[5] => Mux97.IN76
IR[5] => Mux97.IN77
IR[5] => Mux97.IN78
IR[5] => Mux97.IN79
IR[5] => Mux97.IN80
IR[5] => Mux97.IN81
IR[5] => Mux97.IN82
IR[5] => Mux97.IN83
IR[5] => Mux97.IN84
IR[5] => Mux97.IN85
IR[5] => Mux97.IN86
IR[5] => Mux97.IN87
IR[5] => Mux97.IN88
IR[5] => Mux97.IN89
IR[5] => Mux97.IN90
IR[5] => Mux97.IN91
IR[5] => Mux97.IN92
IR[5] => Mux97.IN93
IR[5] => Mux97.IN94
IR[5] => Mux97.IN95
IR[5] => Mux97.IN96
IR[5] => Mux97.IN97
IR[5] => Mux97.IN98
IR[5] => Mux97.IN99
IR[5] => Mux97.IN100
IR[5] => Mux97.IN101
IR[5] => Mux97.IN102
IR[5] => Mux97.IN103
IR[5] => Mux97.IN104
IR[5] => Mux97.IN105
IR[5] => Mux97.IN106
IR[5] => Mux97.IN107
IR[5] => Mux97.IN108
IR[5] => Mux97.IN109
IR[5] => Mux97.IN110
IR[5] => Mux97.IN111
IR[5] => Mux97.IN112
IR[5] => Mux97.IN113
IR[5] => Mux97.IN114
IR[5] => Mux97.IN115
IR[5] => Mux97.IN116
IR[5] => Mux97.IN117
IR[5] => Mux97.IN118
IR[5] => Mux97.IN119
IR[5] => Mux97.IN120
IR[5] => Mux97.IN121
IR[5] => Mux97.IN122
IR[5] => Mux97.IN123
IR[5] => Mux97.IN124
IR[5] => Mux97.IN125
IR[5] => Mux97.IN126
IR[5] => Mux97.IN127
IR[5] => Mux97.IN128
IR[5] => Mux97.IN129
IR[5] => Mux97.IN130
IR[5] => Mux97.IN131
IR[5] => Mux97.IN132
IR[5] => Mux97.IN133
IR[5] => Mux97.IN134
IR[5] => Mux97.IN135
IR[5] => Mux97.IN136
IR[5] => Mux97.IN137
IR[5] => Mux97.IN138
IR[5] => Mux97.IN139
IR[5] => Mux97.IN140
IR[5] => Mux97.IN141
IR[5] => Mux97.IN142
IR[5] => Mux97.IN143
IR[5] => Mux97.IN144
IR[5] => Mux97.IN145
IR[5] => Mux97.IN146
IR[5] => Mux97.IN147
IR[5] => Mux97.IN148
IR[5] => Mux97.IN149
IR[5] => Mux97.IN150
IR[5] => Mux97.IN151
IR[5] => Mux97.IN152
IR[5] => Mux97.IN153
IR[5] => Mux97.IN154
IR[5] => Mux97.IN155
IR[5] => Mux97.IN156
IR[5] => Mux97.IN157
IR[5] => Mux97.IN158
IR[5] => Mux97.IN159
IR[5] => Mux97.IN160
IR[5] => Mux97.IN161
IR[5] => Mux97.IN162
IR[5] => Mux97.IN163
IR[5] => Mux97.IN164
IR[5] => Mux97.IN165
IR[5] => Mux97.IN166
IR[5] => Mux97.IN167
IR[5] => Mux97.IN168
IR[5] => Mux97.IN169
IR[5] => Mux97.IN170
IR[5] => Mux97.IN171
IR[5] => Mux97.IN172
IR[5] => Mux97.IN173
IR[5] => Mux97.IN174
IR[5] => Mux97.IN175
IR[5] => Mux97.IN176
IR[5] => Mux97.IN177
IR[5] => Mux97.IN178
IR[5] => Mux97.IN179
IR[5] => Mux97.IN180
IR[5] => Mux97.IN181
IR[5] => Mux97.IN182
IR[5] => Mux97.IN183
IR[5] => Mux97.IN184
IR[5] => Mux97.IN185
IR[5] => Mux97.IN186
IR[5] => Mux97.IN187
IR[5] => Mux97.IN188
IR[5] => Mux97.IN189
IR[5] => Mux97.IN190
IR[5] => Mux97.IN191
IR[5] => Mux97.IN192
IR[5] => Mux97.IN193
IR[5] => Mux97.IN194
IR[5] => Mux97.IN195
IR[5] => Mux97.IN196
IR[5] => Mux97.IN197
IR[5] => Mux97.IN198
IR[5] => Mux97.IN199
IR[5] => Mux97.IN200
IR[5] => Mux97.IN201
IR[5] => Mux97.IN202
IR[5] => Mux97.IN203
IR[5] => Mux97.IN204
IR[5] => Mux97.IN205
IR[5] => Mux97.IN206
IR[5] => Mux97.IN207
IR[5] => Mux97.IN208
IR[5] => Mux97.IN209
IR[5] => Mux97.IN210
IR[5] => Mux97.IN211
IR[5] => Mux97.IN212
IR[5] => Mux97.IN213
IR[5] => Mux97.IN214
IR[5] => Mux97.IN215
IR[5] => Mux97.IN216
IR[5] => Mux97.IN217
IR[5] => Mux97.IN218
IR[5] => Mux97.IN219
IR[5] => Mux97.IN220
IR[5] => Mux97.IN221
IR[5] => Mux97.IN222
IR[5] => Mux97.IN223
IR[5] => Mux97.IN224
IR[5] => Mux97.IN225
IR[5] => Mux97.IN226
IR[5] => Mux97.IN227
IR[5] => Mux97.IN228
IR[5] => Mux97.IN229
IR[5] => Mux97.IN230
IR[5] => Mux97.IN231
IR[5] => Mux97.IN232
IR[5] => Mux97.IN233
IR[5] => Mux97.IN234
IR[5] => Mux97.IN235
IR[5] => Mux97.IN236
IR[5] => Mux97.IN237
IR[5] => Mux97.IN238
IR[5] => Mux97.IN239
IR[5] => Mux97.IN240
IR[5] => Mux97.IN241
IR[5] => Mux97.IN242
IR[5] => Mux97.IN243
IR[5] => Mux97.IN244
IR[5] => Mux97.IN245
IR[5] => Mux97.IN246
IR[5] => Mux97.IN247
IR[5] => Mux97.IN248
IR[5] => Mux97.IN249
IR[5] => Mux97.IN250
IR[5] => Mux97.IN251
IR[5] => Mux97.IN252
IR[5] => Mux97.IN253
IR[5] => Mux97.IN254
IR[5] => Mux97.IN255
IR[5] => Mux97.IN256
IR[5] => Mux97.IN257
IR[5] => Mux97.IN258
IR[5] => Mux98.IN28
IR[5] => Mux99.IN28
IR[5] => Mux100.IN258
IR[5] => Mux101.IN258
IR[5] => Mux102.IN258
IR[5] => Mux103.IN258
IR[5] => Mux104.IN258
IR[5] => Mux105.IN258
IR[5] => Mux106.IN258
IR[5] => Mux107.IN258
IR[5] => Mux109.IN258
IR[5] => Mux110.IN258
IR[5] => Mux111.IN258
IR[5] => Mux112.IN258
IR[5] => Mux114.IN258
IR[5] => Mux115.IN258
IR[5] => Mux116.IN258
IR[5] => ALU_Op.DATAA
IR[5] => Set_BusA_To.DATAA
IR[5] => Mux143.IN1
IR[5] => Mux143.IN2
IR[5] => Mux143.IN3
IR[5] => Mux143.IN4
IR[5] => Mux143.IN5
IR[5] => Mux143.IN6
IR[5] => Mux143.IN7
IR[5] => Mux148.IN1
IR[5] => Mux148.IN2
IR[5] => Mux148.IN3
IR[5] => Mux148.IN4
IR[5] => Mux148.IN5
IR[5] => Mux148.IN6
IR[5] => Mux148.IN7
IR[5] => Mux152.IN4
IR[5] => Mux153.IN4
IR[5] => Mux154.IN1
IR[5] => Mux154.IN2
IR[5] => Mux154.IN3
IR[5] => Mux154.IN4
IR[5] => Mux155.IN1
IR[5] => Mux156.IN1
IR[5] => Mux156.IN2
IR[5] => Mux156.IN3
IR[5] => Mux168.IN1
IR[5] => Mux168.IN2
IR[5] => Mux168.IN3
IR[5] => Mux168.IN4
IR[5] => Mux168.IN5
IR[5] => Mux168.IN6
IR[5] => Mux168.IN7
IR[5] => Set_BusA_To.DATAB
IR[5] => Mux181.IN7
IR[5] => Mux192.IN1
IR[5] => Mux192.IN2
IR[5] => Mux192.IN3
IR[5] => Mux192.IN4
IR[5] => Mux192.IN5
IR[5] => Mux192.IN6
IR[5] => Mux192.IN7
IR[5] => Mux197.IN66
IR[5] => Mux198.IN130
IR[5] => Mux199.IN130
IR[5] => Mux200.IN258
IR[5] => Mux201.IN258
IR[5] => Mux202.IN258
IR[5] => Mux203.IN130
IR[5] => Mux205.IN130
IR[5] => Mux208.IN258
IR[5] => Mux209.IN66
IR[5] => Mux210.IN258
IR[5] => Mux212.IN258
IR[5] => Mux214.IN258
IR[5] => Mux215.IN258
IR[5] => Mux216.IN258
IR[5] => Mux218.IN130
IR[5] => Mux219.IN258
IR[5] => Mux220.IN258
IR[5] => Mux222.IN258
IR[5] => Mux223.IN66
IR[5] => Mux224.IN66
IR[5] => Mux225.IN66
IR[5] => Mux226.IN66
IR[5] => Mux227.IN258
IR[5] => Mux228.IN36
IR[5] => Mux228.IN37
IR[5] => Mux228.IN38
IR[5] => Mux228.IN39
IR[5] => Mux228.IN40
IR[5] => Mux228.IN41
IR[5] => Mux228.IN42
IR[5] => Mux228.IN43
IR[5] => Mux228.IN44
IR[5] => Mux228.IN45
IR[5] => Mux228.IN46
IR[5] => Mux228.IN47
IR[5] => Mux228.IN48
IR[5] => Mux228.IN49
IR[5] => Mux228.IN50
IR[5] => Mux228.IN51
IR[5] => Mux228.IN52
IR[5] => Mux228.IN53
IR[5] => Mux228.IN54
IR[5] => Mux228.IN55
IR[5] => Mux228.IN56
IR[5] => Mux228.IN57
IR[5] => Mux228.IN58
IR[5] => Mux228.IN59
IR[5] => Mux228.IN60
IR[5] => Mux228.IN61
IR[5] => Mux228.IN62
IR[5] => Mux228.IN63
IR[5] => Mux228.IN64
IR[5] => Mux228.IN65
IR[5] => Mux228.IN66
IR[5] => Mux228.IN67
IR[5] => Mux228.IN68
IR[5] => Mux228.IN69
IR[5] => Mux228.IN70
IR[5] => Mux228.IN71
IR[5] => Mux228.IN72
IR[5] => Mux228.IN73
IR[5] => Mux228.IN74
IR[5] => Mux228.IN75
IR[5] => Mux228.IN76
IR[5] => Mux228.IN77
IR[5] => Mux228.IN78
IR[5] => Mux228.IN79
IR[5] => Mux228.IN80
IR[5] => Mux228.IN81
IR[5] => Mux228.IN82
IR[5] => Mux228.IN83
IR[5] => Mux228.IN84
IR[5] => Mux228.IN85
IR[5] => Mux228.IN86
IR[5] => Mux228.IN87
IR[5] => Mux228.IN88
IR[5] => Mux228.IN89
IR[5] => Mux228.IN90
IR[5] => Mux228.IN91
IR[5] => Mux228.IN92
IR[5] => Mux228.IN93
IR[5] => Mux228.IN94
IR[5] => Mux228.IN95
IR[5] => Mux228.IN96
IR[5] => Mux228.IN97
IR[5] => Mux228.IN98
IR[5] => Mux228.IN99
IR[5] => Mux228.IN100
IR[5] => Mux228.IN101
IR[5] => Mux228.IN102
IR[5] => Mux228.IN103
IR[5] => Mux228.IN104
IR[5] => Mux228.IN105
IR[5] => Mux228.IN106
IR[5] => Mux228.IN107
IR[5] => Mux228.IN108
IR[5] => Mux228.IN109
IR[5] => Mux228.IN110
IR[5] => Mux228.IN111
IR[5] => Mux228.IN112
IR[5] => Mux228.IN113
IR[5] => Mux228.IN114
IR[5] => Mux228.IN115
IR[5] => Mux228.IN116
IR[5] => Mux228.IN117
IR[5] => Mux228.IN118
IR[5] => Mux228.IN119
IR[5] => Mux228.IN120
IR[5] => Mux228.IN121
IR[5] => Mux228.IN122
IR[5] => Mux228.IN123
IR[5] => Mux228.IN124
IR[5] => Mux228.IN125
IR[5] => Mux228.IN126
IR[5] => Mux228.IN127
IR[5] => Mux228.IN128
IR[5] => Mux228.IN129
IR[5] => Mux228.IN130
IR[5] => Mux228.IN131
IR[5] => Mux228.IN132
IR[5] => Mux228.IN133
IR[5] => Mux228.IN134
IR[5] => Mux228.IN135
IR[5] => Mux228.IN136
IR[5] => Mux228.IN137
IR[5] => Mux228.IN138
IR[5] => Mux228.IN139
IR[5] => Mux228.IN140
IR[5] => Mux228.IN141
IR[5] => Mux228.IN142
IR[5] => Mux228.IN143
IR[5] => Mux228.IN144
IR[5] => Mux228.IN145
IR[5] => Mux228.IN146
IR[5] => Mux228.IN147
IR[5] => Mux228.IN148
IR[5] => Mux228.IN149
IR[5] => Mux228.IN150
IR[5] => Mux228.IN151
IR[5] => Mux228.IN152
IR[5] => Mux228.IN153
IR[5] => Mux228.IN154
IR[5] => Mux228.IN155
IR[5] => Mux228.IN156
IR[5] => Mux228.IN157
IR[5] => Mux228.IN158
IR[5] => Mux228.IN159
IR[5] => Mux228.IN160
IR[5] => Mux228.IN161
IR[5] => Mux228.IN162
IR[5] => Mux228.IN163
IR[5] => Mux228.IN164
IR[5] => Mux228.IN165
IR[5] => Mux228.IN166
IR[5] => Mux228.IN167
IR[5] => Mux228.IN168
IR[5] => Mux228.IN169
IR[5] => Mux228.IN170
IR[5] => Mux228.IN171
IR[5] => Mux228.IN172
IR[5] => Mux228.IN173
IR[5] => Mux228.IN174
IR[5] => Mux228.IN175
IR[5] => Mux228.IN176
IR[5] => Mux228.IN177
IR[5] => Mux228.IN178
IR[5] => Mux228.IN179
IR[5] => Mux228.IN180
IR[5] => Mux228.IN181
IR[5] => Mux228.IN182
IR[5] => Mux228.IN183
IR[5] => Mux228.IN184
IR[5] => Mux228.IN185
IR[5] => Mux228.IN186
IR[5] => Mux228.IN187
IR[5] => Mux228.IN188
IR[5] => Mux228.IN189
IR[5] => Mux228.IN190
IR[5] => Mux228.IN191
IR[5] => Mux228.IN192
IR[5] => Mux228.IN193
IR[5] => Mux228.IN194
IR[5] => Mux228.IN195
IR[5] => Mux228.IN196
IR[5] => Mux228.IN197
IR[5] => Mux228.IN198
IR[5] => Mux228.IN199
IR[5] => Mux228.IN200
IR[5] => Mux228.IN201
IR[5] => Mux228.IN202
IR[5] => Mux228.IN203
IR[5] => Mux228.IN204
IR[5] => Mux228.IN205
IR[5] => Mux228.IN206
IR[5] => Mux228.IN207
IR[5] => Mux228.IN208
IR[5] => Mux228.IN209
IR[5] => Mux228.IN210
IR[5] => Mux228.IN211
IR[5] => Mux228.IN212
IR[5] => Mux228.IN213
IR[5] => Mux228.IN214
IR[5] => Mux228.IN215
IR[5] => Mux228.IN216
IR[5] => Mux228.IN217
IR[5] => Mux228.IN218
IR[5] => Mux228.IN219
IR[5] => Mux228.IN220
IR[5] => Mux228.IN221
IR[5] => Mux228.IN222
IR[5] => Mux228.IN223
IR[5] => Mux228.IN224
IR[5] => Mux228.IN225
IR[5] => Mux228.IN226
IR[5] => Mux228.IN227
IR[5] => Mux228.IN228
IR[5] => Mux228.IN229
IR[5] => Mux228.IN230
IR[5] => Mux228.IN231
IR[5] => Mux228.IN232
IR[5] => Mux228.IN233
IR[5] => Mux228.IN234
IR[5] => Mux228.IN235
IR[5] => Mux228.IN236
IR[5] => Mux228.IN237
IR[5] => Mux228.IN238
IR[5] => Mux228.IN239
IR[5] => Mux228.IN240
IR[5] => Mux228.IN241
IR[5] => Mux228.IN242
IR[5] => Mux228.IN243
IR[5] => Mux228.IN244
IR[5] => Mux228.IN245
IR[5] => Mux228.IN246
IR[5] => Mux228.IN247
IR[5] => Mux228.IN248
IR[5] => Mux228.IN249
IR[5] => Mux228.IN250
IR[5] => Mux228.IN251
IR[5] => Mux228.IN252
IR[5] => Mux228.IN253
IR[5] => Mux228.IN254
IR[5] => Mux228.IN255
IR[5] => Mux228.IN256
IR[5] => Mux228.IN257
IR[5] => Mux228.IN258
IR[5] => Mux229.IN36
IR[5] => Mux230.IN36
IR[5] => Mux231.IN66
IR[5] => Mux232.IN258
IR[5] => Mux233.IN258
IR[5] => Mux234.IN66
IR[5] => Mux235.IN66
IR[5] => Mux238.IN258
IR[5] => Mux239.IN258
IR[5] => Mux240.IN258
IR[5] => Mux242.IN66
IR[5] => Mux244.IN66
IR[5] => Equal2.IN0
IR[5] => Equal3.IN1
IR[5] => Equal5.IN0
IR[5] => Equal7.IN4
IR[6] => Mux61.IN257
IR[6] => Mux62.IN152
IR[6] => Mux63.IN152
IR[6] => Mux64.IN152
IR[6] => Mux65.IN257
IR[6] => Mux66.IN65
IR[6] => Mux67.IN194
IR[6] => Mux68.IN194
IR[6] => Mux69.IN194
IR[6] => Mux70.IN257
IR[6] => Mux71.IN257
IR[6] => Mux72.IN256
IR[6] => Mux73.IN257
IR[6] => Mux74.IN257
IR[6] => Mux75.IN257
IR[6] => Mux76.IN257
IR[6] => Mux77.IN257
IR[6] => Mux78.IN257
IR[6] => Mux79.IN257
IR[6] => Mux80.IN257
IR[6] => Mux81.IN257
IR[6] => Mux82.IN257
IR[6] => Mux83.IN257
IR[6] => Mux84.IN257
IR[6] => Mux85.IN257
IR[6] => Mux86.IN257
IR[6] => Mux87.IN257
IR[6] => Mux88.IN257
IR[6] => Mux89.IN249
IR[6] => Mux90.IN249
IR[6] => Mux91.IN257
IR[6] => Mux92.IN257
IR[6] => Mux93.IN257
IR[6] => Mux94.IN257
IR[6] => Mux95.IN257
IR[6] => Mux96.IN257
IR[6] => Mux97.IN27
IR[6] => Mux98.IN27
IR[6] => Mux99.IN27
IR[6] => Mux100.IN257
IR[6] => Mux101.IN257
IR[6] => Mux102.IN257
IR[6] => Mux103.IN257
IR[6] => Mux104.IN257
IR[6] => Mux105.IN257
IR[6] => Mux106.IN257
IR[6] => Mux107.IN257
IR[6] => Mux108.IN65
IR[6] => Mux109.IN257
IR[6] => Mux110.IN257
IR[6] => Mux111.IN257
IR[6] => Mux112.IN257
IR[6] => Mux113.IN33
IR[6] => Mux114.IN257
IR[6] => Mux115.IN257
IR[6] => Mux116.IN257
IR[6] => Mux119.IN33
IR[6] => Mux120.IN33
IR[6] => Mux121.IN33
IR[6] => Mux122.IN33
IR[6] => Mux123.IN33
IR[6] => Mux125.IN33
IR[6] => Mux126.IN33
IR[6] => Mux127.IN33
IR[6] => Mux128.IN33
IR[6] => Mux129.IN33
IR[6] => Mux130.IN33
IR[6] => Mux197.IN65
IR[6] => Mux198.IN129
IR[6] => Mux199.IN129
IR[6] => Mux200.IN257
IR[6] => Mux201.IN257
IR[6] => Mux202.IN257
IR[6] => Mux203.IN129
IR[6] => Mux204.IN33
IR[6] => Mux205.IN129
IR[6] => Mux206.IN65
IR[6] => Mux207.IN65
IR[6] => Mux208.IN257
IR[6] => Mux209.IN65
IR[6] => Mux210.IN257
IR[6] => Mux211.IN65
IR[6] => Mux212.IN257
IR[6] => Mux213.IN65
IR[6] => Mux214.IN257
IR[6] => Mux215.IN257
IR[6] => Mux216.IN257
IR[6] => Mux217.IN65
IR[6] => Mux218.IN129
IR[6] => Mux219.IN257
IR[6] => Mux220.IN257
IR[6] => Mux221.IN65
IR[6] => Mux222.IN257
IR[6] => Mux223.IN65
IR[6] => Mux224.IN65
IR[6] => Mux225.IN65
IR[6] => Mux226.IN65
IR[6] => Mux227.IN257
IR[6] => Mux228.IN35
IR[6] => Mux229.IN35
IR[6] => Mux230.IN35
IR[6] => Mux231.IN65
IR[6] => Mux232.IN257
IR[6] => Mux233.IN257
IR[6] => Mux234.IN65
IR[6] => Mux235.IN65
IR[6] => Mux236.IN33
IR[6] => Mux237.IN129
IR[6] => Mux238.IN257
IR[6] => Mux239.IN257
IR[6] => Mux240.IN257
IR[6] => Mux241.IN33
IR[6] => Mux242.IN65
IR[6] => Mux243.IN33
IR[6] => Mux244.IN65
IR[6] => Equal5.IN4
IR[6] => Equal7.IN1
IR[7] => Mux61.IN256
IR[7] => Mux62.IN151
IR[7] => Mux63.IN151
IR[7] => Mux64.IN151
IR[7] => Mux65.IN256
IR[7] => Mux66.IN64
IR[7] => Mux67.IN193
IR[7] => Mux68.IN193
IR[7] => Mux69.IN193
IR[7] => Mux70.IN256
IR[7] => Mux71.IN256
IR[7] => Mux72.IN255
IR[7] => Mux73.IN256
IR[7] => Mux74.IN256
IR[7] => Mux75.IN256
IR[7] => Mux76.IN256
IR[7] => Mux77.IN256
IR[7] => Mux78.IN256
IR[7] => Mux79.IN256
IR[7] => Mux80.IN256
IR[7] => Mux81.IN256
IR[7] => Mux82.IN256
IR[7] => Mux83.IN256
IR[7] => Mux84.IN256
IR[7] => Mux85.IN256
IR[7] => Mux86.IN256
IR[7] => Mux87.IN256
IR[7] => Mux88.IN256
IR[7] => Mux89.IN248
IR[7] => Mux90.IN248
IR[7] => Mux91.IN256
IR[7] => Mux92.IN256
IR[7] => Mux93.IN256
IR[7] => Mux94.IN256
IR[7] => Mux95.IN256
IR[7] => Mux96.IN256
IR[7] => Mux97.IN26
IR[7] => Mux98.IN26
IR[7] => Mux99.IN26
IR[7] => Mux100.IN256
IR[7] => Mux101.IN256
IR[7] => Mux102.IN256
IR[7] => Mux103.IN256
IR[7] => Mux104.IN256
IR[7] => Mux105.IN256
IR[7] => Mux106.IN256
IR[7] => Mux107.IN256
IR[7] => Mux108.IN64
IR[7] => Mux109.IN256
IR[7] => Mux110.IN256
IR[7] => Mux111.IN256
IR[7] => Mux112.IN256
IR[7] => Mux113.IN32
IR[7] => Mux114.IN256
IR[7] => Mux115.IN256
IR[7] => Mux116.IN256
IR[7] => Mux119.IN32
IR[7] => Mux120.IN32
IR[7] => Mux121.IN32
IR[7] => Mux122.IN32
IR[7] => Mux123.IN32
IR[7] => Mux125.IN32
IR[7] => Mux126.IN32
IR[7] => Mux127.IN32
IR[7] => Mux128.IN32
IR[7] => Mux129.IN32
IR[7] => Mux130.IN32
IR[7] => Mux197.IN64
IR[7] => Mux198.IN128
IR[7] => Mux199.IN128
IR[7] => Mux200.IN256
IR[7] => Mux201.IN256
IR[7] => Mux202.IN256
IR[7] => Mux203.IN128
IR[7] => Mux204.IN32
IR[7] => Mux205.IN128
IR[7] => Mux206.IN64
IR[7] => Mux207.IN64
IR[7] => Mux208.IN256
IR[7] => Mux209.IN64
IR[7] => Mux210.IN256
IR[7] => Mux211.IN64
IR[7] => Mux212.IN256
IR[7] => Mux213.IN64
IR[7] => Mux214.IN256
IR[7] => Mux215.IN256
IR[7] => Mux216.IN256
IR[7] => Mux217.IN64
IR[7] => Mux218.IN128
IR[7] => Mux219.IN256
IR[7] => Mux220.IN256
IR[7] => Mux221.IN64
IR[7] => Mux222.IN256
IR[7] => Mux223.IN64
IR[7] => Mux224.IN64
IR[7] => Mux225.IN64
IR[7] => Mux226.IN64
IR[7] => Mux227.IN256
IR[7] => Mux228.IN34
IR[7] => Mux229.IN34
IR[7] => Mux230.IN34
IR[7] => Mux231.IN64
IR[7] => Mux232.IN256
IR[7] => Mux233.IN256
IR[7] => Mux234.IN64
IR[7] => Mux235.IN64
IR[7] => Mux236.IN32
IR[7] => Mux237.IN128
IR[7] => Mux238.IN256
IR[7] => Mux239.IN256
IR[7] => Mux240.IN256
IR[7] => Mux241.IN32
IR[7] => Mux242.IN64
IR[7] => Mux243.IN32
IR[7] => Mux244.IN64
IR[7] => Equal5.IN3
IR[7] => Equal7.IN0
ISet[0] => Mux245.IN5
ISet[0] => Mux246.IN5
ISet[0] => Mux247.IN5
ISet[0] => Mux248.IN5
ISet[0] => Mux249.IN5
ISet[0] => Mux250.IN5
ISet[0] => Mux251.IN5
ISet[0] => Mux252.IN5
ISet[0] => Mux253.IN5
ISet[0] => Mux254.IN5
ISet[0] => Mux255.IN5
ISet[0] => Mux256.IN5
ISet[0] => Mux257.IN5
ISet[0] => Mux258.IN5
ISet[0] => Mux259.IN5
ISet[0] => Mux260.IN5
ISet[0] => Mux261.IN5
ISet[0] => Mux262.IN5
ISet[0] => Mux263.IN5
ISet[0] => Mux264.IN5
ISet[0] => Mux265.IN5
ISet[0] => Mux266.IN5
ISet[0] => Mux267.IN5
ISet[0] => Mux268.IN5
ISet[0] => Mux269.IN5
ISet[0] => Mux270.IN5
ISet[0] => Mux271.IN5
ISet[0] => Mux272.IN5
ISet[0] => Mux273.IN5
ISet[0] => Mux274.IN5
ISet[0] => Mux275.IN5
ISet[0] => Mux276.IN5
ISet[0] => Mux277.IN5
ISet[0] => Mux278.IN5
ISet[0] => Mux279.IN5
ISet[0] => Mux280.IN5
ISet[0] => Mux281.IN5
ISet[0] => Mux282.IN5
ISet[0] => Mux283.IN5
ISet[0] => Mux284.IN5
ISet[0] => Mux285.IN5
ISet[0] => Mux286.IN5
ISet[0] => Mux287.IN5
ISet[0] => Mux288.IN5
ISet[0] => Mux289.IN5
ISet[0] => Mux290.IN5
ISet[0] => Mux291.IN5
ISet[0] => Mux292.IN5
ISet[0] => Mux293.IN5
ISet[0] => Mux294.IN5
ISet[0] => Mux295.IN5
ISet[0] => Mux296.IN5
ISet[0] => Mux297.IN5
ISet[0] => Mux298.IN5
ISet[0] => Mux299.IN5
ISet[0] => Mux300.IN5
ISet[0] => Equal8.IN1
ISet[1] => Mux245.IN4
ISet[1] => Mux246.IN4
ISet[1] => Mux247.IN4
ISet[1] => Mux248.IN4
ISet[1] => Mux249.IN4
ISet[1] => Mux250.IN4
ISet[1] => Mux251.IN4
ISet[1] => Mux252.IN4
ISet[1] => Mux253.IN4
ISet[1] => Mux254.IN4
ISet[1] => Mux255.IN4
ISet[1] => Mux256.IN4
ISet[1] => Mux257.IN4
ISet[1] => Mux258.IN4
ISet[1] => Mux259.IN4
ISet[1] => Mux260.IN4
ISet[1] => Mux261.IN4
ISet[1] => Mux262.IN4
ISet[1] => Mux263.IN4
ISet[1] => Mux264.IN4
ISet[1] => Mux265.IN4
ISet[1] => Mux266.IN4
ISet[1] => Mux267.IN4
ISet[1] => Mux268.IN4
ISet[1] => Mux269.IN4
ISet[1] => Mux270.IN4
ISet[1] => Mux271.IN4
ISet[1] => Mux272.IN4
ISet[1] => Mux273.IN4
ISet[1] => Mux274.IN4
ISet[1] => Mux275.IN4
ISet[1] => Mux276.IN4
ISet[1] => Mux277.IN4
ISet[1] => Mux278.IN4
ISet[1] => Mux279.IN4
ISet[1] => Mux280.IN4
ISet[1] => Mux281.IN4
ISet[1] => Mux282.IN4
ISet[1] => Mux283.IN4
ISet[1] => Mux284.IN4
ISet[1] => Mux285.IN4
ISet[1] => Mux286.IN4
ISet[1] => Mux287.IN4
ISet[1] => Mux288.IN4
ISet[1] => Mux289.IN4
ISet[1] => Mux290.IN4
ISet[1] => Mux291.IN4
ISet[1] => Mux292.IN4
ISet[1] => Mux293.IN4
ISet[1] => Mux294.IN4
ISet[1] => Mux295.IN4
ISet[1] => Mux296.IN4
ISet[1] => Mux297.IN4
ISet[1] => Mux298.IN4
ISet[1] => Mux299.IN4
ISet[1] => Mux300.IN4
ISet[1] => Special_LD.OUTPUTSELECT
ISet[1] => Special_LD.OUTPUTSELECT
ISet[1] => Special_LD.OUTPUTSELECT
ISet[1] => I_BT.OUTPUTSELECT
ISet[1] => I_BC.OUTPUTSELECT
ISet[1] => IMode.OUTPUTSELECT
ISet[1] => IMode.OUTPUTSELECT
ISet[1] => I_RLD.OUTPUTSELECT
ISet[1] => I_RRD.OUTPUTSELECT
ISet[1] => I_RETN.OUTPUTSELECT
ISet[1] => I_INRC.OUTPUTSELECT
ISet[1] => I_BTR.OUTPUTSELECT
ISet[1] => Equal8.IN0
MCycle[0] => Mux0.IN10
MCycle[0] => Mux1.IN10
MCycle[0] => Mux2.IN10
MCycle[0] => Mux3.IN10
MCycle[0] => Mux4.IN10
MCycle[0] => Mux5.IN10
MCycle[0] => Mux6.IN10
MCycle[0] => Mux7.IN10
MCycle[0] => Mux8.IN10
MCycle[0] => Mux9.IN10
MCycle[0] => Mux10.IN10
MCycle[0] => Mux11.IN10
MCycle[0] => Mux12.IN10
MCycle[0] => Mux13.IN10
MCycle[0] => Mux14.IN10
MCycle[0] => Mux15.IN10
MCycle[0] => Mux16.IN10
MCycle[0] => Mux17.IN10
MCycle[0] => Mux18.IN10
MCycle[0] => Mux19.IN10
MCycle[0] => Mux20.IN10
MCycle[0] => Mux21.IN10
MCycle[0] => Mux22.IN10
MCycle[0] => Mux23.IN10
MCycle[0] => Mux24.IN10
MCycle[0] => Mux25.IN10
MCycle[0] => Mux26.IN10
MCycle[0] => Mux27.IN10
MCycle[0] => Mux28.IN10
MCycle[0] => Mux29.IN10
MCycle[0] => Mux30.IN10
MCycle[0] => Mux31.IN10
MCycle[0] => Mux32.IN10
MCycle[0] => Mux33.IN10
MCycle[0] => Mux34.IN10
MCycle[0] => Mux35.IN9
MCycle[0] => Mux36.IN10
MCycle[0] => Mux37.IN10
MCycle[0] => Mux38.IN9
MCycle[0] => Mux39.IN10
MCycle[0] => Mux40.IN5
MCycle[0] => Mux41.IN5
MCycle[0] => Mux42.IN5
MCycle[0] => Mux43.IN10
MCycle[0] => Mux44.IN10
MCycle[0] => Mux46.IN10
MCycle[0] => Mux47.IN10
MCycle[0] => Mux48.IN10
MCycle[0] => Mux49.IN10
MCycle[0] => Mux50.IN10
MCycle[0] => Mux51.IN10
MCycle[0] => Mux52.IN10
MCycle[0] => Mux53.IN10
MCycle[0] => Mux54.IN10
MCycle[0] => Mux55.IN10
MCycle[0] => Mux56.IN10
MCycle[0] => Mux57.IN10
MCycle[0] => Mux58.IN10
MCycle[0] => Mux59.IN10
MCycle[0] => Mux60.IN10
MCycle[0] => Mux117.IN10
MCycle[0] => Mux118.IN10
MCycle[0] => Mux133.IN10
MCycle[0] => Mux134.IN10
MCycle[0] => Mux135.IN10
MCycle[0] => Mux136.IN10
MCycle[0] => Mux137.IN10
MCycle[0] => Mux138.IN10
MCycle[0] => Mux139.IN10
MCycle[0] => Mux140.IN10
MCycle[0] => Mux141.IN10
MCycle[0] => Mux142.IN10
MCycle[0] => Mux143.IN10
MCycle[0] => Mux144.IN10
MCycle[0] => Mux145.IN10
MCycle[0] => Mux146.IN10
MCycle[0] => Mux147.IN10
MCycle[0] => Mux148.IN10
MCycle[0] => Mux149.IN10
MCycle[0] => Mux150.IN10
MCycle[0] => Mux151.IN10
MCycle[0] => Mux159.IN10
MCycle[0] => Mux160.IN10
MCycle[0] => Mux161.IN10
MCycle[0] => Mux162.IN10
MCycle[0] => Mux163.IN10
MCycle[0] => Mux164.IN10
MCycle[0] => Mux165.IN10
MCycle[0] => Mux168.IN10
MCycle[0] => Mux169.IN10
MCycle[0] => Mux170.IN10
MCycle[0] => Mux171.IN10
MCycle[0] => Mux172.IN10
MCycle[0] => Mux173.IN10
MCycle[0] => Mux174.IN10
MCycle[0] => Mux175.IN10
MCycle[0] => Mux176.IN10
MCycle[0] => Mux177.IN10
MCycle[0] => Mux178.IN10
MCycle[0] => Mux179.IN10
MCycle[0] => Mux180.IN10
MCycle[0] => Mux181.IN10
MCycle[0] => Mux182.IN10
MCycle[0] => Mux183.IN10
MCycle[0] => Mux184.IN10
MCycle[0] => Mux185.IN10
MCycle[0] => Mux186.IN10
MCycle[0] => Mux187.IN10
MCycle[0] => Mux188.IN10
MCycle[0] => Mux189.IN10
MCycle[0] => Mux190.IN10
MCycle[0] => Mux191.IN10
MCycle[0] => Mux192.IN10
MCycle[0] => Mux193.IN10
MCycle[0] => Mux194.IN10
MCycle[0] => Mux195.IN10
MCycle[0] => Mux196.IN10
MCycle[0] => Equal0.IN2
MCycle[0] => Equal1.IN1
MCycle[0] => Equal4.IN0
MCycle[0] => Equal6.IN2
MCycle[1] => Mux0.IN9
MCycle[1] => Mux1.IN9
MCycle[1] => Mux2.IN9
MCycle[1] => Mux3.IN9
MCycle[1] => Mux4.IN9
MCycle[1] => Mux5.IN9
MCycle[1] => Mux6.IN9
MCycle[1] => Mux7.IN9
MCycle[1] => Mux8.IN9
MCycle[1] => Mux9.IN9
MCycle[1] => Mux10.IN9
MCycle[1] => Mux11.IN9
MCycle[1] => Mux12.IN9
MCycle[1] => Mux13.IN9
MCycle[1] => Mux14.IN9
MCycle[1] => Mux15.IN9
MCycle[1] => Mux16.IN9
MCycle[1] => Mux17.IN9
MCycle[1] => Mux18.IN9
MCycle[1] => Mux19.IN9
MCycle[1] => Mux20.IN9
MCycle[1] => Mux21.IN9
MCycle[1] => Mux22.IN9
MCycle[1] => Mux23.IN9
MCycle[1] => Mux24.IN9
MCycle[1] => Mux25.IN9
MCycle[1] => Mux26.IN9
MCycle[1] => Mux27.IN9
MCycle[1] => Mux28.IN9
MCycle[1] => Mux29.IN9
MCycle[1] => Mux30.IN9
MCycle[1] => Mux31.IN9
MCycle[1] => Mux32.IN9
MCycle[1] => Mux33.IN9
MCycle[1] => Mux34.IN9
MCycle[1] => Mux35.IN8
MCycle[1] => Mux36.IN9
MCycle[1] => Mux37.IN9
MCycle[1] => Mux38.IN8
MCycle[1] => Mux39.IN9
MCycle[1] => Mux43.IN9
MCycle[1] => Mux44.IN9
MCycle[1] => Mux46.IN9
MCycle[1] => Mux47.IN9
MCycle[1] => Mux48.IN9
MCycle[1] => Mux49.IN9
MCycle[1] => Mux50.IN9
MCycle[1] => Mux51.IN9
MCycle[1] => Mux52.IN9
MCycle[1] => Mux53.IN9
MCycle[1] => Mux54.IN9
MCycle[1] => Mux55.IN9
MCycle[1] => Mux56.IN9
MCycle[1] => Mux57.IN9
MCycle[1] => Mux58.IN9
MCycle[1] => Mux59.IN9
MCycle[1] => Mux60.IN9
MCycle[1] => Mux117.IN9
MCycle[1] => Mux118.IN9
MCycle[1] => Mux131.IN5
MCycle[1] => Mux132.IN5
MCycle[1] => Mux133.IN9
MCycle[1] => Mux134.IN9
MCycle[1] => Mux135.IN9
MCycle[1] => Mux136.IN9
MCycle[1] => Mux137.IN9
MCycle[1] => Mux138.IN9
MCycle[1] => Mux139.IN9
MCycle[1] => Mux140.IN9
MCycle[1] => Mux141.IN9
MCycle[1] => Mux142.IN9
MCycle[1] => Mux143.IN9
MCycle[1] => Mux144.IN9
MCycle[1] => Mux145.IN9
MCycle[1] => Mux146.IN9
MCycle[1] => Mux147.IN9
MCycle[1] => Mux148.IN9
MCycle[1] => Mux149.IN9
MCycle[1] => Mux150.IN9
MCycle[1] => Mux151.IN9
MCycle[1] => Mux156.IN5
MCycle[1] => Mux157.IN5
MCycle[1] => Mux158.IN5
MCycle[1] => Mux159.IN9
MCycle[1] => Mux160.IN9
MCycle[1] => Mux161.IN9
MCycle[1] => Mux162.IN9
MCycle[1] => Mux163.IN9
MCycle[1] => Mux164.IN9
MCycle[1] => Mux165.IN9
MCycle[1] => Mux166.IN5
MCycle[1] => Mux167.IN5
MCycle[1] => Mux168.IN9
MCycle[1] => Mux169.IN9
MCycle[1] => Mux170.IN9
MCycle[1] => Mux171.IN9
MCycle[1] => Mux172.IN9
MCycle[1] => Mux173.IN9
MCycle[1] => Mux174.IN9
MCycle[1] => Mux175.IN9
MCycle[1] => Mux176.IN9
MCycle[1] => Mux177.IN9
MCycle[1] => Mux178.IN9
MCycle[1] => Mux179.IN9
MCycle[1] => Mux180.IN9
MCycle[1] => Mux181.IN9
MCycle[1] => Mux182.IN9
MCycle[1] => Mux183.IN9
MCycle[1] => Mux184.IN9
MCycle[1] => Mux185.IN9
MCycle[1] => Mux186.IN9
MCycle[1] => Mux187.IN9
MCycle[1] => Mux188.IN9
MCycle[1] => Mux189.IN9
MCycle[1] => Mux190.IN9
MCycle[1] => Mux191.IN9
MCycle[1] => Mux192.IN9
MCycle[1] => Mux193.IN9
MCycle[1] => Mux194.IN9
MCycle[1] => Mux195.IN9
MCycle[1] => Mux196.IN9
MCycle[1] => Equal0.IN1
MCycle[1] => Equal1.IN2
MCycle[1] => Equal4.IN2
MCycle[1] => Equal6.IN1
MCycle[2] => Mux0.IN8
MCycle[2] => Mux1.IN8
MCycle[2] => Mux2.IN8
MCycle[2] => Mux3.IN8
MCycle[2] => Mux4.IN8
MCycle[2] => Mux5.IN8
MCycle[2] => Mux6.IN8
MCycle[2] => Mux7.IN8
MCycle[2] => Mux8.IN8
MCycle[2] => Mux9.IN8
MCycle[2] => Mux10.IN8
MCycle[2] => Mux11.IN8
MCycle[2] => Mux12.IN8
MCycle[2] => Mux13.IN8
MCycle[2] => Mux14.IN8
MCycle[2] => Mux15.IN8
MCycle[2] => Mux16.IN8
MCycle[2] => Mux17.IN8
MCycle[2] => Mux18.IN8
MCycle[2] => Mux19.IN8
MCycle[2] => Mux20.IN8
MCycle[2] => Mux21.IN8
MCycle[2] => Mux22.IN8
MCycle[2] => Mux23.IN8
MCycle[2] => Mux24.IN8
MCycle[2] => Mux25.IN8
MCycle[2] => Mux26.IN8
MCycle[2] => Mux27.IN8
MCycle[2] => Mux28.IN8
MCycle[2] => Mux29.IN8
MCycle[2] => Mux30.IN8
MCycle[2] => Mux31.IN8
MCycle[2] => Mux32.IN8
MCycle[2] => Mux33.IN8
MCycle[2] => Mux34.IN8
MCycle[2] => Mux35.IN7
MCycle[2] => Mux36.IN8
MCycle[2] => Mux37.IN8
MCycle[2] => Mux38.IN7
MCycle[2] => Mux39.IN8
MCycle[2] => Mux40.IN4
MCycle[2] => Mux41.IN4
MCycle[2] => Mux42.IN4
MCycle[2] => Mux43.IN8
MCycle[2] => Mux44.IN8
MCycle[2] => Mux46.IN8
MCycle[2] => Mux47.IN8
MCycle[2] => Mux48.IN8
MCycle[2] => Mux49.IN8
MCycle[2] => Mux50.IN8
MCycle[2] => Mux51.IN8
MCycle[2] => Mux52.IN8
MCycle[2] => Mux53.IN8
MCycle[2] => Mux54.IN8
MCycle[2] => Mux55.IN8
MCycle[2] => Mux56.IN8
MCycle[2] => Mux57.IN8
MCycle[2] => Mux58.IN8
MCycle[2] => Mux59.IN8
MCycle[2] => Mux60.IN8
MCycle[2] => Mux117.IN8
MCycle[2] => Mux118.IN8
MCycle[2] => Mux131.IN4
MCycle[2] => Mux132.IN4
MCycle[2] => Mux133.IN8
MCycle[2] => Mux134.IN8
MCycle[2] => Mux135.IN8
MCycle[2] => Mux136.IN8
MCycle[2] => Mux137.IN8
MCycle[2] => Mux138.IN8
MCycle[2] => Mux139.IN8
MCycle[2] => Mux140.IN8
MCycle[2] => Mux141.IN8
MCycle[2] => Mux142.IN8
MCycle[2] => Mux143.IN8
MCycle[2] => Mux144.IN8
MCycle[2] => Mux145.IN8
MCycle[2] => Mux146.IN8
MCycle[2] => Mux147.IN8
MCycle[2] => Mux148.IN8
MCycle[2] => Mux149.IN8
MCycle[2] => Mux150.IN8
MCycle[2] => Mux151.IN8
MCycle[2] => Mux156.IN4
MCycle[2] => Mux157.IN4
MCycle[2] => Mux158.IN4
MCycle[2] => Mux159.IN8
MCycle[2] => Mux160.IN8
MCycle[2] => Mux161.IN8
MCycle[2] => Mux162.IN8
MCycle[2] => Mux163.IN8
MCycle[2] => Mux164.IN8
MCycle[2] => Mux165.IN8
MCycle[2] => Mux166.IN4
MCycle[2] => Mux167.IN4
MCycle[2] => Mux168.IN8
MCycle[2] => Mux169.IN8
MCycle[2] => Mux170.IN8
MCycle[2] => Mux171.IN8
MCycle[2] => Mux172.IN8
MCycle[2] => Mux173.IN8
MCycle[2] => Mux174.IN8
MCycle[2] => Mux175.IN8
MCycle[2] => Mux176.IN8
MCycle[2] => Mux177.IN8
MCycle[2] => Mux178.IN8
MCycle[2] => Mux179.IN8
MCycle[2] => Mux180.IN8
MCycle[2] => Mux181.IN8
MCycle[2] => Mux182.IN8
MCycle[2] => Mux183.IN8
MCycle[2] => Mux184.IN8
MCycle[2] => Mux185.IN8
MCycle[2] => Mux186.IN8
MCycle[2] => Mux187.IN8
MCycle[2] => Mux188.IN8
MCycle[2] => Mux189.IN8
MCycle[2] => Mux190.IN8
MCycle[2] => Mux191.IN8
MCycle[2] => Mux192.IN8
MCycle[2] => Mux193.IN8
MCycle[2] => Mux194.IN8
MCycle[2] => Mux195.IN8
MCycle[2] => Mux196.IN8
MCycle[2] => Equal0.IN0
MCycle[2] => Equal1.IN0
MCycle[2] => Equal4.IN1
MCycle[2] => Equal6.IN0
F[0] => Mux35.IN10
F[0] => Mux45.IN10
F[0] => Mux45.IN1
F[0] => Mux37.IN7
F[1] => ~NO_FANOUT~
F[2] => Mux45.IN9
F[2] => Mux45.IN2
F[3] => ~NO_FANOUT~
F[4] => ~NO_FANOUT~
F[5] => ~NO_FANOUT~
F[6] => Mux38.IN10
F[6] => Mux45.IN8
F[6] => Mux45.IN0
F[6] => Mux39.IN7
F[7] => Mux45.IN7
F[7] => Mux45.IN3
NMICycle => MCycles.OUTPUTSELECT
NMICycle => TStates.OUTPUTSELECT
NMICycle => TStates.OUTPUTSELECT
NMICycle => TStates.OUTPUTSELECT
NMICycle => IncDec_16.OUTPUTSELECT
NMICycle => Set_Addr_To.OUTPUTSELECT
NMICycle => Set_BusB_To.OUTPUTSELECT
NMICycle => Write.OUTPUTSELECT
NMICycle => LDZ.OUTPUTSELECT
NMICycle => Inc_PC.OUTPUTSELECT
NMICycle => Jump.OUTPUTSELECT
NMICycle => Mux72.IN263
IntCycle => MCycles.DATAA
IntCycle => TStates.OUTPUTSELECT
IntCycle => TStates.OUTPUTSELECT
IntCycle => TStates.OUTPUTSELECT
IntCycle => IncDec_16.OUTPUTSELECT
IntCycle => Set_Addr_To.OUTPUTSELECT
IntCycle => Set_BusB_To.OUTPUTSELECT
IntCycle => Write.OUTPUTSELECT
IntCycle => LDZ.OUTPUTSELECT
IntCycle => Inc_PC.OUTPUTSELECT
IntCycle => Jump.OUTPUTSELECT
MCycles[0] <= Mux257.DB_MAX_OUTPUT_PORT_TYPE
MCycles[1] <= Mux256.DB_MAX_OUTPUT_PORT_TYPE
MCycles[2] <= Mux255.DB_MAX_OUTPUT_PORT_TYPE
TStates[0] <= TStates.DB_MAX_OUTPUT_PORT_TYPE
TStates[1] <= TStates.DB_MAX_OUTPUT_PORT_TYPE
TStates[2] <= TStates.DB_MAX_OUTPUT_PORT_TYPE
Prefix[0] <= Mux300.DB_MAX_OUTPUT_PORT_TYPE
Prefix[1] <= Mux299.DB_MAX_OUTPUT_PORT_TYPE
Inc_PC <= Inc_PC.DB_MAX_OUTPUT_PORT_TYPE
Inc_WZ <= Mux266.DB_MAX_OUTPUT_PORT_TYPE
IncDec_16[0] <= Mux274.DB_MAX_OUTPUT_PORT_TYPE
IncDec_16[1] <= Mux273.DB_MAX_OUTPUT_PORT_TYPE
IncDec_16[2] <= Mux272.DB_MAX_OUTPUT_PORT_TYPE
IncDec_16[3] <= Mux271.DB_MAX_OUTPUT_PORT_TYPE
Read_To_Reg <= Mux254.DB_MAX_OUTPUT_PORT_TYPE
Read_To_Acc <= Mux263.DB_MAX_OUTPUT_PORT_TYPE
Set_BusA_To[0] <= Mux253.DB_MAX_OUTPUT_PORT_TYPE
Set_BusA_To[1] <= Mux252.DB_MAX_OUTPUT_PORT_TYPE
Set_BusA_To[2] <= Mux251.DB_MAX_OUTPUT_PORT_TYPE
Set_BusA_To[3] <= Mux250.DB_MAX_OUTPUT_PORT_TYPE
Set_BusB_To[0] <= Set_BusB_To.DB_MAX_OUTPUT_PORT_TYPE
Set_BusB_To[1] <= Set_BusB_To.DB_MAX_OUTPUT_PORT_TYPE
Set_BusB_To[2] <= Set_BusB_To.DB_MAX_OUTPUT_PORT_TYPE
Set_BusB_To[3] <= Set_BusB_To.DB_MAX_OUTPUT_PORT_TYPE
ALU_Op[0] <= Mux283.DB_MAX_OUTPUT_PORT_TYPE
ALU_Op[1] <= Mux282.DB_MAX_OUTPUT_PORT_TYPE
ALU_Op[2] <= Mux281.DB_MAX_OUTPUT_PORT_TYPE
ALU_Op[3] <= Mux280.DB_MAX_OUTPUT_PORT_TYPE
Save_ALU <= Mux278.DB_MAX_OUTPUT_PORT_TYPE
PreserveC <= Mux279.DB_MAX_OUTPUT_PORT_TYPE
Arith16 <= Mux292.DB_MAX_OUTPUT_PORT_TYPE
Set_Addr_To[0] <= Set_Addr_To.DB_MAX_OUTPUT_PORT_TYPE
Set_Addr_To[1] <= Set_Addr_To.DB_MAX_OUTPUT_PORT_TYPE
Set_Addr_To[2] <= Set_Addr_To.DB_MAX_OUTPUT_PORT_TYPE
IORQ <= Mux298.DB_MAX_OUTPUT_PORT_TYPE
Jump <= Mux287.DB_MAX_OUTPUT_PORT_TYPE
JumpE <= Mux293.DB_MAX_OUTPUT_PORT_TYPE
JumpXY <= Mux294.DB_MAX_OUTPUT_PORT_TYPE
Call <= Mux296.DB_MAX_OUTPUT_PORT_TYPE
RstP <= Mux297.DB_MAX_OUTPUT_PORT_TYPE
LDZ <= Mux264.DB_MAX_OUTPUT_PORT_TYPE
LDW <= Mux265.DB_MAX_OUTPUT_PORT_TYPE
LDSPHL <= Mux270.DB_MAX_OUTPUT_PORT_TYPE
Special_LD[0] <= Special_LD.DB_MAX_OUTPUT_PORT_TYPE
Special_LD[1] <= Special_LD.DB_MAX_OUTPUT_PORT_TYPE
Special_LD[2] <= Special_LD.DB_MAX_OUTPUT_PORT_TYPE
ExchangeDH <= Mux275.DB_MAX_OUTPUT_PORT_TYPE
ExchangeRp <= Mux249.DB_MAX_OUTPUT_PORT_TYPE
ExchangeAF <= Mux276.DB_MAX_OUTPUT_PORT_TYPE
ExchangeRS <= Mux277.DB_MAX_OUTPUT_PORT_TYPE
I_DJNZ <= Mux295.DB_MAX_OUTPUT_PORT_TYPE
I_CPL <= Mux284.DB_MAX_OUTPUT_PORT_TYPE
I_CCF <= Mux285.DB_MAX_OUTPUT_PORT_TYPE
I_SCF <= Mux286.DB_MAX_OUTPUT_PORT_TYPE
I_RETN <= I_RETN.DB_MAX_OUTPUT_PORT_TYPE
I_BT <= I_BT.DB_MAX_OUTPUT_PORT_TYPE
I_BC <= I_BC.DB_MAX_OUTPUT_PORT_TYPE
I_BTR <= I_BTR.DB_MAX_OUTPUT_PORT_TYPE
I_RLD <= I_RLD.DB_MAX_OUTPUT_PORT_TYPE
I_RRD <= I_RRD.DB_MAX_OUTPUT_PORT_TYPE
I_INRC <= I_INRC.DB_MAX_OUTPUT_PORT_TYPE
SetDI <= Mux289.DB_MAX_OUTPUT_PORT_TYPE
SetEI <= Mux290.DB_MAX_OUTPUT_PORT_TYPE
IMode[0] <= IMode.DB_MAX_OUTPUT_PORT_TYPE
IMode[1] <= IMode.DB_MAX_OUTPUT_PORT_TYPE
Halt <= Mux288.DB_MAX_OUTPUT_PORT_TYPE
NoRead <= NoRead.DB_MAX_OUTPUT_PORT_TYPE
Write <= Mux262.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|T80se:z80_inst|T80:u0|T80_ALU:alu
Arith16 => F_Out.OUTPUTSELECT
Arith16 => F_Out.OUTPUTSELECT
Arith16 => F_Out.OUTPUTSELECT
Z16 => F_Out.OUTPUTSELECT
ALU_Op[0] => UseCarry.IN0
ALU_Op[0] => Mux8.IN5
ALU_Op[0] => Mux9.IN5
ALU_Op[0] => Mux10.IN5
ALU_Op[0] => Mux11.IN5
ALU_Op[0] => Mux12.IN5
ALU_Op[0] => Mux13.IN5
ALU_Op[0] => Mux14.IN5
ALU_Op[0] => Mux15.IN5
ALU_Op[0] => Mux16.IN8
ALU_Op[0] => Mux17.IN2
ALU_Op[0] => Mux18.IN10
ALU_Op[0] => Mux19.IN8
ALU_Op[0] => Mux20.IN10
ALU_Op[0] => Q_t.OUTPUTSELECT
ALU_Op[0] => Q_t.OUTPUTSELECT
ALU_Op[0] => Q_t.OUTPUTSELECT
ALU_Op[0] => Q_t.OUTPUTSELECT
ALU_Op[0] => Mux23.IN13
ALU_Op[0] => Mux24.IN16
ALU_Op[0] => Mux25.IN13
ALU_Op[0] => Mux26.IN16
ALU_Op[0] => Mux27.IN15
ALU_Op[0] => Mux28.IN16
ALU_Op[0] => Mux29.IN15
ALU_Op[0] => Mux30.IN13
ALU_Op[0] => Mux31.IN16
ALU_Op[0] => Mux32.IN16
ALU_Op[0] => Mux33.IN16
ALU_Op[0] => Mux34.IN16
ALU_Op[0] => Mux35.IN18
ALU_Op[0] => Mux36.IN18
ALU_Op[0] => Mux37.IN18
ALU_Op[0] => Mux38.IN18
ALU_Op[0] => Equal0.IN2
ALU_Op[1] => comb.IN1
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => B_i.OUTPUTSELECT
ALU_Op[1] => Mux8.IN4
ALU_Op[1] => Mux9.IN4
ALU_Op[1] => Mux10.IN4
ALU_Op[1] => Mux11.IN4
ALU_Op[1] => Mux12.IN4
ALU_Op[1] => Mux13.IN4
ALU_Op[1] => Mux14.IN4
ALU_Op[1] => Mux15.IN4
ALU_Op[1] => Mux16.IN7
ALU_Op[1] => Mux17.IN1
ALU_Op[1] => Mux18.IN9
ALU_Op[1] => Mux19.IN7
ALU_Op[1] => Mux20.IN9
ALU_Op[1] => Mux23.IN12
ALU_Op[1] => Mux24.IN15
ALU_Op[1] => Mux25.IN12
ALU_Op[1] => Mux26.IN15
ALU_Op[1] => Mux27.IN14
ALU_Op[1] => Mux28.IN15
ALU_Op[1] => Mux29.IN14
ALU_Op[1] => Mux30.IN12
ALU_Op[1] => Mux31.IN15
ALU_Op[1] => Mux32.IN15
ALU_Op[1] => Mux33.IN15
ALU_Op[1] => Mux34.IN15
ALU_Op[1] => Mux35.IN17
ALU_Op[1] => Mux36.IN17
ALU_Op[1] => Mux37.IN17
ALU_Op[1] => Mux38.IN17
ALU_Op[1] => Equal0.IN1
ALU_Op[2] => Mux8.IN3
ALU_Op[2] => Mux9.IN3
ALU_Op[2] => Mux10.IN3
ALU_Op[2] => Mux11.IN3
ALU_Op[2] => Mux12.IN3
ALU_Op[2] => Mux13.IN3
ALU_Op[2] => Mux14.IN3
ALU_Op[2] => Mux15.IN3
ALU_Op[2] => Mux16.IN6
ALU_Op[2] => Mux17.IN0
ALU_Op[2] => Mux18.IN8
ALU_Op[2] => Mux19.IN6
ALU_Op[2] => Mux20.IN8
ALU_Op[2] => Mux23.IN11
ALU_Op[2] => Mux24.IN14
ALU_Op[2] => Mux25.IN11
ALU_Op[2] => Mux26.IN14
ALU_Op[2] => Mux27.IN13
ALU_Op[2] => Mux28.IN14
ALU_Op[2] => Mux29.IN13
ALU_Op[2] => Mux30.IN11
ALU_Op[2] => Mux31.IN14
ALU_Op[2] => Mux32.IN14
ALU_Op[2] => Mux33.IN14
ALU_Op[2] => Mux34.IN14
ALU_Op[2] => Mux35.IN16
ALU_Op[2] => Mux36.IN16
ALU_Op[2] => Mux37.IN16
ALU_Op[2] => Mux38.IN16
ALU_Op[2] => UseCarry.IN1
ALU_Op[2] => Equal0.IN0
ALU_Op[3] => Mux23.IN10
ALU_Op[3] => Mux24.IN13
ALU_Op[3] => Mux25.IN10
ALU_Op[3] => Mux26.IN13
ALU_Op[3] => Mux27.IN12
ALU_Op[3] => Mux28.IN13
ALU_Op[3] => Mux29.IN12
ALU_Op[3] => Mux30.IN10
ALU_Op[3] => Mux31.IN13
ALU_Op[3] => Mux32.IN13
ALU_Op[3] => Mux33.IN13
ALU_Op[3] => Mux34.IN13
ALU_Op[3] => Mux35.IN15
ALU_Op[3] => Mux36.IN15
ALU_Op[3] => Mux37.IN15
ALU_Op[3] => Mux38.IN15
IR[0] => Equal5.IN0
IR[1] => Equal5.IN2
IR[2] => Equal5.IN1
IR[3] => Mux0.IN10
IR[3] => Mux1.IN10
IR[3] => Mux2.IN10
IR[3] => Mux3.IN10
IR[3] => Mux4.IN10
IR[3] => Mux5.IN10
IR[3] => Mux6.IN10
IR[3] => Mux7.IN10
IR[3] => Mux21.IN3
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Q_t.OUTPUTSELECT
IR[3] => Mux22.IN4
IR[3] => F_Out.OUTPUTSELECT
IR[4] => Mux0.IN9
IR[4] => Mux1.IN9
IR[4] => Mux2.IN9
IR[4] => Mux3.IN9
IR[4] => Mux4.IN9
IR[4] => Mux5.IN9
IR[4] => Mux6.IN9
IR[4] => Mux7.IN9
IR[4] => Mux21.IN2
IR[4] => Mux22.IN3
IR[5] => Mux0.IN8
IR[5] => Mux1.IN8
IR[5] => Mux2.IN8
IR[5] => Mux3.IN8
IR[5] => Mux4.IN8
IR[5] => Mux5.IN8
IR[5] => Mux6.IN8
IR[5] => Mux7.IN8
IR[5] => Mux21.IN1
IR[5] => Mux22.IN2
ISet[0] => Equal7.IN1
ISet[1] => Equal7.IN0
BusA[0] => Add0.IN10
BusA[0] => Q_t.IN0
BusA[0] => Q_t.IN0
BusA[0] => Q_t.IN0
BusA[0] => LessThan1.IN8
BusA[0] => LessThan2.IN8
BusA[0] => LessThan3.IN16
BusA[0] => Equal2.IN8
BusA[0] => F_Out.IN1
BusA[0] => Mux21.IN9
BusA[0] => Q_t.DATAA
BusA[0] => F_Out.DATAB
BusA[0] => Mux38.IN19
BusA[1] => Add0.IN9
BusA[1] => Q_t.IN0
BusA[1] => Q_t.IN0
BusA[1] => Q_t.IN0
BusA[1] => Add3.IN14
BusA[1] => DAA_Q.DATAA
BusA[1] => LessThan1.IN7
BusA[1] => LessThan2.IN7
BusA[1] => Add5.IN14
BusA[1] => DAA_Q.DATAA
BusA[1] => LessThan3.IN15
BusA[1] => Q_t.DATAA
BusA[1] => Mux22.IN6
BusA[1] => Mux22.IN7
BusA[1] => Mux22.IN8
BusA[1] => Mux22.IN9
BusA[2] => Add0.IN8
BusA[2] => Q_t.IN0
BusA[2] => Q_t.IN0
BusA[2] => Q_t.IN0
BusA[2] => Add3.IN13
BusA[2] => DAA_Q.DATAA
BusA[2] => LessThan1.IN6
BusA[2] => LessThan2.IN6
BusA[2] => Add5.IN13
BusA[2] => DAA_Q.DATAA
BusA[2] => LessThan3.IN14
BusA[2] => Q_t.DATAA
BusA[2] => Q_t.DATAB
BusA[3] => Add0.IN7
BusA[3] => Q_t.IN0
BusA[3] => Q_t.IN0
BusA[3] => Q_t.IN0
BusA[3] => Add3.IN12
BusA[3] => DAA_Q.DATAA
BusA[3] => LessThan1.IN5
BusA[3] => LessThan2.IN5
BusA[3] => Add5.IN12
BusA[3] => DAA_Q.DATAA
BusA[3] => LessThan3.IN13
BusA[3] => Q_t.DATAA
BusA[3] => Q_t.DATAB
BusA[4] => Add1.IN7
BusA[4] => Q_t.IN0
BusA[4] => Q_t.IN0
BusA[4] => Q_t.IN0
BusA[4] => Add3.IN11
BusA[4] => DAA_Q.DATAA
BusA[4] => Add5.IN11
BusA[4] => DAA_Q.DATAA
BusA[4] => LessThan3.IN12
BusA[4] => F_Out.IN1
BusA[4] => Q_t.DATAA
BusA[4] => Q_t.DATAB
BusA[4] => Mux34.IN17
BusA[4] => Mux34.IN18
BusA[4] => Equal3.IN3
BusA[5] => Add1.IN6
BusA[5] => Q_t.IN0
BusA[5] => Q_t.IN0
BusA[5] => Q_t.IN0
BusA[5] => Add3.IN10
BusA[5] => DAA_Q.DATAA
BusA[5] => Add5.IN10
BusA[5] => DAA_Q.DATAA
BusA[5] => LessThan3.IN11
BusA[5] => F_Out.IN1
BusA[5] => Q_t.DATAA
BusA[5] => Q_t.DATAB
BusA[5] => Mux25.IN14
BusA[5] => Mux25.IN15
BusA[5] => Mux33.IN17
BusA[5] => Mux33.IN18
BusA[5] => Equal3.IN2
BusA[6] => Add1.IN5
BusA[6] => Q_t.IN0
BusA[6] => Q_t.IN0
BusA[6] => Q_t.IN0
BusA[6] => Add3.IN9
BusA[6] => DAA_Q.DATAA
BusA[6] => Add5.IN9
BusA[6] => DAA_Q.DATAA
BusA[6] => LessThan3.IN10
BusA[6] => F_Out.IN1
BusA[6] => Mux21.IN5
BusA[6] => Mux21.IN6
BusA[6] => Mux21.IN7
BusA[6] => Mux21.IN8
BusA[6] => Q_t.DATAB
BusA[6] => Mux32.IN17
BusA[6] => Mux32.IN18
BusA[6] => Equal3.IN1
BusA[7] => Add2.IN3
BusA[7] => Q_t.IN0
BusA[7] => Q_t.IN0
BusA[7] => Q_t.IN0
BusA[7] => Add3.IN8
BusA[7] => DAA_Q.DATAA
BusA[7] => Add5.IN8
BusA[7] => DAA_Q.DATAA
BusA[7] => LessThan3.IN9
BusA[7] => F_Out.IN1
BusA[7] => Mux21.IN4
BusA[7] => Q_t.DATAB
BusA[7] => Mux22.IN5
BusA[7] => F_Out.DATAA
BusA[7] => Mux23.IN14
BusA[7] => Mux23.IN15
BusA[7] => Mux31.IN17
BusA[7] => Mux31.IN18
BusA[7] => Equal3.IN0
BusB[0] => B_i.DATAA
BusB[0] => Q_t.IN1
BusB[0] => Q_t.IN1
BusB[0] => Q_t.IN1
BusB[0] => Q_t.DATAA
BusB[0] => Q_t.IN1
BusB[0] => Q_t.IN1
BusB[0] => Q_t.IN1
BusB[0] => B_i.DATAB
BusB[1] => B_i.DATAA
BusB[1] => Q_t.IN1
BusB[1] => Q_t.IN1
BusB[1] => Q_t.IN1
BusB[1] => Q_t.DATAA
BusB[1] => Q_t.IN1
BusB[1] => Q_t.IN1
BusB[1] => Q_t.IN1
BusB[1] => B_i.DATAB
BusB[2] => B_i.DATAA
BusB[2] => Q_t.IN1
BusB[2] => Q_t.IN1
BusB[2] => Q_t.IN1
BusB[2] => Q_t.DATAA
BusB[2] => Q_t.IN1
BusB[2] => Q_t.IN1
BusB[2] => Q_t.IN1
BusB[2] => B_i.DATAB
BusB[3] => B_i.DATAA
BusB[3] => Q_t.IN1
BusB[3] => Q_t.IN1
BusB[3] => Q_t.IN1
BusB[3] => F_Out.DATAB
BusB[3] => Q_t.DATAA
BusB[3] => Q_t.IN1
BusB[3] => F_Out.DATAB
BusB[3] => Q_t.IN1
BusB[3] => Q_t.IN1
BusB[3] => B_i.DATAB
BusB[4] => B_i.DATAA
BusB[4] => Q_t.IN1
BusB[4] => Q_t.IN1
BusB[4] => Q_t.IN1
BusB[4] => Q_t.DATAB
BusB[4] => Q_t.IN1
BusB[4] => Q_t.IN1
BusB[4] => Q_t.IN1
BusB[4] => B_i.DATAB
BusB[5] => B_i.DATAA
BusB[5] => Q_t.IN1
BusB[5] => Q_t.IN1
BusB[5] => Q_t.IN1
BusB[5] => F_Out.DATAB
BusB[5] => Q_t.DATAB
BusB[5] => Q_t.IN1
BusB[5] => F_Out.DATAB
BusB[5] => Q_t.IN1
BusB[5] => Q_t.IN1
BusB[5] => B_i.DATAB
BusB[6] => B_i.DATAA
BusB[6] => Q_t.IN1
BusB[6] => Q_t.IN1
BusB[6] => Q_t.IN1
BusB[6] => Q_t.DATAB
BusB[6] => Q_t.IN1
BusB[6] => Q_t.IN1
BusB[6] => Q_t.IN1
BusB[6] => B_i.DATAB
BusB[7] => B_i.DATAA
BusB[7] => Q_t.IN1
BusB[7] => Q_t.IN1
BusB[7] => Q_t.IN1
BusB[7] => Q_t.DATAB
BusB[7] => Q_t.IN1
BusB[7] => Q_t.IN1
BusB[7] => Q_t.IN1
BusB[7] => B_i.DATAB
F_In[0] => comb.IN1
F_In[0] => process_1.IN1
F_In[0] => process_1.IN1
F_In[0] => F_Out.IN1
F_In[0] => Mux21.IN10
F_In[0] => Mux22.IN10
F_In[0] => Mux30.IN14
F_In[0] => Mux30.IN15
F_In[0] => Mux30.IN16
F_In[0] => Mux30.IN17
F_In[0] => Mux30.IN18
F_In[0] => Mux30.IN19
F_In[1] => Mux29.IN16
F_In[1] => Mux29.IN17
F_In[1] => Mux29.IN18
F_In[1] => Mux29.IN19
F_In[1] => F_Out.OUTPUTSELECT
F_In[1] => DAA_Q[8].OUTPUTSELECT
F_In[1] => DAA_Q[7].OUTPUTSELECT
F_In[1] => DAA_Q[6].OUTPUTSELECT
F_In[1] => DAA_Q[5].OUTPUTSELECT
F_In[1] => DAA_Q[4].OUTPUTSELECT
F_In[1] => DAA_Q[3].OUTPUTSELECT
F_In[1] => DAA_Q[2].OUTPUTSELECT
F_In[1] => DAA_Q[1].OUTPUTSELECT
F_In[2] => Mux17.IN3
F_In[2] => Mux17.IN4
F_In[2] => Mux17.IN5
F_In[2] => F_Out.DATAB
F_In[2] => F_Out.DATAB
F_In[2] => Mux28.IN17
F_In[2] => Mux28.IN18
F_In[2] => Mux28.IN19
F_In[3] => Mux27.IN16
F_In[3] => Mux27.IN17
F_In[3] => Mux27.IN18
F_In[4] => F_Out.DATAA
F_In[4] => process_1.IN1
F_In[4] => F_Out.DATAA
F_In[4] => F_Out.DATAA
F_In[4] => Mux26.IN17
F_In[4] => Mux26.IN18
F_In[4] => Mux26.IN19
F_In[5] => Mux25.IN16
F_In[5] => Mux25.IN17
F_In[5] => Mux25.IN18
F_In[6] => F_Out.DATAB
F_In[6] => F_Out.DATAB
F_In[6] => F_Out.DATAB
F_In[6] => Mux24.IN17
F_In[6] => Mux24.IN18
F_In[6] => Mux24.IN19
F_In[7] => F_Out.DATAB
F_In[7] => F_Out.DATAB
F_In[7] => Mux23.IN16
F_In[7] => Mux23.IN17
F_In[7] => Mux23.IN18
Q[0] <= Mux38.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Mux37.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Mux36.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Mux35.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Mux34.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Mux33.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Mux32.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
F_Out[0] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
F_Out[1] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
F_Out[2] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
F_Out[3] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
F_Out[4] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
F_Out[5] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
F_Out[6] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
F_Out[7] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|T80se:z80_inst|T80:u0|T80_Reg:Regs
Clk => RegsL[7][0].CLK
Clk => RegsL[7][1].CLK
Clk => RegsL[7][2].CLK
Clk => RegsL[7][3].CLK
Clk => RegsL[7][4].CLK
Clk => RegsL[7][5].CLK
Clk => RegsL[7][6].CLK
Clk => RegsL[7][7].CLK
Clk => RegsL[6][0].CLK
Clk => RegsL[6][1].CLK
Clk => RegsL[6][2].CLK
Clk => RegsL[6][3].CLK
Clk => RegsL[6][4].CLK
Clk => RegsL[6][5].CLK
Clk => RegsL[6][6].CLK
Clk => RegsL[6][7].CLK
Clk => RegsL[5][0].CLK
Clk => RegsL[5][1].CLK
Clk => RegsL[5][2].CLK
Clk => RegsL[5][3].CLK
Clk => RegsL[5][4].CLK
Clk => RegsL[5][5].CLK
Clk => RegsL[5][6].CLK
Clk => RegsL[5][7].CLK
Clk => RegsL[4][0].CLK
Clk => RegsL[4][1].CLK
Clk => RegsL[4][2].CLK
Clk => RegsL[4][3].CLK
Clk => RegsL[4][4].CLK
Clk => RegsL[4][5].CLK
Clk => RegsL[4][6].CLK
Clk => RegsL[4][7].CLK
Clk => RegsL[3][0].CLK
Clk => RegsL[3][1].CLK
Clk => RegsL[3][2].CLK
Clk => RegsL[3][3].CLK
Clk => RegsL[3][4].CLK
Clk => RegsL[3][5].CLK
Clk => RegsL[3][6].CLK
Clk => RegsL[3][7].CLK
Clk => RegsL[2][0].CLK
Clk => RegsL[2][1].CLK
Clk => RegsL[2][2].CLK
Clk => RegsL[2][3].CLK
Clk => RegsL[2][4].CLK
Clk => RegsL[2][5].CLK
Clk => RegsL[2][6].CLK
Clk => RegsL[2][7].CLK
Clk => RegsL[1][0].CLK
Clk => RegsL[1][1].CLK
Clk => RegsL[1][2].CLK
Clk => RegsL[1][3].CLK
Clk => RegsL[1][4].CLK
Clk => RegsL[1][5].CLK
Clk => RegsL[1][6].CLK
Clk => RegsL[1][7].CLK
Clk => RegsL[0][0].CLK
Clk => RegsL[0][1].CLK
Clk => RegsL[0][2].CLK
Clk => RegsL[0][3].CLK
Clk => RegsL[0][4].CLK
Clk => RegsL[0][5].CLK
Clk => RegsL[0][6].CLK
Clk => RegsL[0][7].CLK
Clk => RegsH[7][0].CLK
Clk => RegsH[7][1].CLK
Clk => RegsH[7][2].CLK
Clk => RegsH[7][3].CLK
Clk => RegsH[7][4].CLK
Clk => RegsH[7][5].CLK
Clk => RegsH[7][6].CLK
Clk => RegsH[7][7].CLK
Clk => RegsH[6][0].CLK
Clk => RegsH[6][1].CLK
Clk => RegsH[6][2].CLK
Clk => RegsH[6][3].CLK
Clk => RegsH[6][4].CLK
Clk => RegsH[6][5].CLK
Clk => RegsH[6][6].CLK
Clk => RegsH[6][7].CLK
Clk => RegsH[5][0].CLK
Clk => RegsH[5][1].CLK
Clk => RegsH[5][2].CLK
Clk => RegsH[5][3].CLK
Clk => RegsH[5][4].CLK
Clk => RegsH[5][5].CLK
Clk => RegsH[5][6].CLK
Clk => RegsH[5][7].CLK
Clk => RegsH[4][0].CLK
Clk => RegsH[4][1].CLK
Clk => RegsH[4][2].CLK
Clk => RegsH[4][3].CLK
Clk => RegsH[4][4].CLK
Clk => RegsH[4][5].CLK
Clk => RegsH[4][6].CLK
Clk => RegsH[4][7].CLK
Clk => RegsH[3][0].CLK
Clk => RegsH[3][1].CLK
Clk => RegsH[3][2].CLK
Clk => RegsH[3][3].CLK
Clk => RegsH[3][4].CLK
Clk => RegsH[3][5].CLK
Clk => RegsH[3][6].CLK
Clk => RegsH[3][7].CLK
Clk => RegsH[2][0].CLK
Clk => RegsH[2][1].CLK
Clk => RegsH[2][2].CLK
Clk => RegsH[2][3].CLK
Clk => RegsH[2][4].CLK
Clk => RegsH[2][5].CLK
Clk => RegsH[2][6].CLK
Clk => RegsH[2][7].CLK
Clk => RegsH[1][0].CLK
Clk => RegsH[1][1].CLK
Clk => RegsH[1][2].CLK
Clk => RegsH[1][3].CLK
Clk => RegsH[1][4].CLK
Clk => RegsH[1][5].CLK
Clk => RegsH[1][6].CLK
Clk => RegsH[1][7].CLK
Clk => RegsH[0][0].CLK
Clk => RegsH[0][1].CLK
Clk => RegsH[0][2].CLK
Clk => RegsH[0][3].CLK
Clk => RegsH[0][4].CLK
Clk => RegsH[0][5].CLK
Clk => RegsH[0][6].CLK
Clk => RegsH[0][7].CLK
CEN => RegsL[7][0].ENA
CEN => RegsL[7][1].ENA
CEN => RegsL[7][2].ENA
CEN => RegsL[7][3].ENA
CEN => RegsL[7][4].ENA
CEN => RegsL[7][5].ENA
CEN => RegsL[7][6].ENA
CEN => RegsL[7][7].ENA
CEN => RegsL[6][0].ENA
CEN => RegsL[6][1].ENA
CEN => RegsL[6][2].ENA
CEN => RegsL[6][3].ENA
CEN => RegsL[6][4].ENA
CEN => RegsL[6][5].ENA
CEN => RegsL[6][6].ENA
CEN => RegsL[6][7].ENA
CEN => RegsL[5][0].ENA
CEN => RegsL[5][1].ENA
CEN => RegsL[5][2].ENA
CEN => RegsL[5][3].ENA
CEN => RegsL[5][4].ENA
CEN => RegsL[5][5].ENA
CEN => RegsL[5][6].ENA
CEN => RegsL[5][7].ENA
CEN => RegsL[4][0].ENA
CEN => RegsL[4][1].ENA
CEN => RegsL[4][2].ENA
CEN => RegsL[4][3].ENA
CEN => RegsL[4][4].ENA
CEN => RegsL[4][5].ENA
CEN => RegsL[4][6].ENA
CEN => RegsL[4][7].ENA
CEN => RegsL[3][0].ENA
CEN => RegsL[3][1].ENA
CEN => RegsL[3][2].ENA
CEN => RegsL[3][3].ENA
CEN => RegsL[3][4].ENA
CEN => RegsL[3][5].ENA
CEN => RegsL[3][6].ENA
CEN => RegsL[3][7].ENA
CEN => RegsL[2][0].ENA
CEN => RegsL[2][1].ENA
CEN => RegsL[2][2].ENA
CEN => RegsL[2][3].ENA
CEN => RegsL[2][4].ENA
CEN => RegsL[2][5].ENA
CEN => RegsL[2][6].ENA
CEN => RegsL[2][7].ENA
CEN => RegsL[1][0].ENA
CEN => RegsL[1][1].ENA
CEN => RegsL[1][2].ENA
CEN => RegsL[1][3].ENA
CEN => RegsL[1][4].ENA
CEN => RegsL[1][5].ENA
CEN => RegsL[1][6].ENA
CEN => RegsL[1][7].ENA
CEN => RegsL[0][0].ENA
CEN => RegsL[0][1].ENA
CEN => RegsL[0][2].ENA
CEN => RegsL[0][3].ENA
CEN => RegsL[0][4].ENA
CEN => RegsL[0][5].ENA
CEN => RegsL[0][6].ENA
CEN => RegsL[0][7].ENA
CEN => RegsH[7][0].ENA
CEN => RegsH[7][1].ENA
CEN => RegsH[7][2].ENA
CEN => RegsH[7][3].ENA
CEN => RegsH[7][4].ENA
CEN => RegsH[7][5].ENA
CEN => RegsH[7][6].ENA
CEN => RegsH[7][7].ENA
CEN => RegsH[6][0].ENA
CEN => RegsH[6][1].ENA
CEN => RegsH[6][2].ENA
CEN => RegsH[6][3].ENA
CEN => RegsH[6][4].ENA
CEN => RegsH[6][5].ENA
CEN => RegsH[6][6].ENA
CEN => RegsH[6][7].ENA
CEN => RegsH[5][0].ENA
CEN => RegsH[5][1].ENA
CEN => RegsH[5][2].ENA
CEN => RegsH[5][3].ENA
CEN => RegsH[5][4].ENA
CEN => RegsH[5][5].ENA
CEN => RegsH[5][6].ENA
CEN => RegsH[5][7].ENA
CEN => RegsH[4][0].ENA
CEN => RegsH[4][1].ENA
CEN => RegsH[4][2].ENA
CEN => RegsH[4][3].ENA
CEN => RegsH[4][4].ENA
CEN => RegsH[4][5].ENA
CEN => RegsH[4][6].ENA
CEN => RegsH[4][7].ENA
CEN => RegsH[3][0].ENA
CEN => RegsH[3][1].ENA
CEN => RegsH[3][2].ENA
CEN => RegsH[3][3].ENA
CEN => RegsH[3][4].ENA
CEN => RegsH[3][5].ENA
CEN => RegsH[3][6].ENA
CEN => RegsH[3][7].ENA
CEN => RegsH[2][0].ENA
CEN => RegsH[2][1].ENA
CEN => RegsH[2][2].ENA
CEN => RegsH[2][3].ENA
CEN => RegsH[2][4].ENA
CEN => RegsH[2][5].ENA
CEN => RegsH[2][6].ENA
CEN => RegsH[2][7].ENA
CEN => RegsH[1][0].ENA
CEN => RegsH[1][1].ENA
CEN => RegsH[1][2].ENA
CEN => RegsH[1][3].ENA
CEN => RegsH[1][4].ENA
CEN => RegsH[1][5].ENA
CEN => RegsH[1][6].ENA
CEN => RegsH[1][7].ENA
CEN => RegsH[0][0].ENA
CEN => RegsH[0][1].ENA
CEN => RegsH[0][2].ENA
CEN => RegsH[0][3].ENA
CEN => RegsH[0][4].ENA
CEN => RegsH[0][5].ENA
CEN => RegsH[0][6].ENA
CEN => RegsH[0][7].ENA
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEH => RegsH.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
WEL => RegsL.OUTPUTSELECT
AddrA[0] => Decoder0.IN2
AddrA[0] => Mux0.IN2
AddrA[0] => Mux1.IN2
AddrA[0] => Mux2.IN2
AddrA[0] => Mux3.IN2
AddrA[0] => Mux4.IN2
AddrA[0] => Mux5.IN2
AddrA[0] => Mux6.IN2
AddrA[0] => Mux7.IN2
AddrA[0] => Mux8.IN2
AddrA[0] => Mux9.IN2
AddrA[0] => Mux10.IN2
AddrA[0] => Mux11.IN2
AddrA[0] => Mux12.IN2
AddrA[0] => Mux13.IN2
AddrA[0] => Mux14.IN2
AddrA[0] => Mux15.IN2
AddrA[1] => Decoder0.IN1
AddrA[1] => Mux0.IN1
AddrA[1] => Mux1.IN1
AddrA[1] => Mux2.IN1
AddrA[1] => Mux3.IN1
AddrA[1] => Mux4.IN1
AddrA[1] => Mux5.IN1
AddrA[1] => Mux6.IN1
AddrA[1] => Mux7.IN1
AddrA[1] => Mux8.IN1
AddrA[1] => Mux9.IN1
AddrA[1] => Mux10.IN1
AddrA[1] => Mux11.IN1
AddrA[1] => Mux12.IN1
AddrA[1] => Mux13.IN1
AddrA[1] => Mux14.IN1
AddrA[1] => Mux15.IN1
AddrA[2] => Decoder0.IN0
AddrA[2] => Mux0.IN0
AddrA[2] => Mux1.IN0
AddrA[2] => Mux2.IN0
AddrA[2] => Mux3.IN0
AddrA[2] => Mux4.IN0
AddrA[2] => Mux5.IN0
AddrA[2] => Mux6.IN0
AddrA[2] => Mux7.IN0
AddrA[2] => Mux8.IN0
AddrA[2] => Mux9.IN0
AddrA[2] => Mux10.IN0
AddrA[2] => Mux11.IN0
AddrA[2] => Mux12.IN0
AddrA[2] => Mux13.IN0
AddrA[2] => Mux14.IN0
AddrA[2] => Mux15.IN0
AddrB[0] => Mux16.IN2
AddrB[0] => Mux17.IN2
AddrB[0] => Mux18.IN2
AddrB[0] => Mux19.IN2
AddrB[0] => Mux20.IN2
AddrB[0] => Mux21.IN2
AddrB[0] => Mux22.IN2
AddrB[0] => Mux23.IN2
AddrB[0] => Mux24.IN2
AddrB[0] => Mux25.IN2
AddrB[0] => Mux26.IN2
AddrB[0] => Mux27.IN2
AddrB[0] => Mux28.IN2
AddrB[0] => Mux29.IN2
AddrB[0] => Mux30.IN2
AddrB[0] => Mux31.IN2
AddrB[1] => Mux16.IN1
AddrB[1] => Mux17.IN1
AddrB[1] => Mux18.IN1
AddrB[1] => Mux19.IN1
AddrB[1] => Mux20.IN1
AddrB[1] => Mux21.IN1
AddrB[1] => Mux22.IN1
AddrB[1] => Mux23.IN1
AddrB[1] => Mux24.IN1
AddrB[1] => Mux25.IN1
AddrB[1] => Mux26.IN1
AddrB[1] => Mux27.IN1
AddrB[1] => Mux28.IN1
AddrB[1] => Mux29.IN1
AddrB[1] => Mux30.IN1
AddrB[1] => Mux31.IN1
AddrB[2] => Mux16.IN0
AddrB[2] => Mux17.IN0
AddrB[2] => Mux18.IN0
AddrB[2] => Mux19.IN0
AddrB[2] => Mux20.IN0
AddrB[2] => Mux21.IN0
AddrB[2] => Mux22.IN0
AddrB[2] => Mux23.IN0
AddrB[2] => Mux24.IN0
AddrB[2] => Mux25.IN0
AddrB[2] => Mux26.IN0
AddrB[2] => Mux27.IN0
AddrB[2] => Mux28.IN0
AddrB[2] => Mux29.IN0
AddrB[2] => Mux30.IN0
AddrB[2] => Mux31.IN0
AddrC[0] => Mux32.IN2
AddrC[0] => Mux33.IN2
AddrC[0] => Mux34.IN2
AddrC[0] => Mux35.IN2
AddrC[0] => Mux36.IN2
AddrC[0] => Mux37.IN2
AddrC[0] => Mux38.IN2
AddrC[0] => Mux39.IN2
AddrC[0] => Mux40.IN2
AddrC[0] => Mux41.IN2
AddrC[0] => Mux42.IN2
AddrC[0] => Mux43.IN2
AddrC[0] => Mux44.IN2
AddrC[0] => Mux45.IN2
AddrC[0] => Mux46.IN2
AddrC[0] => Mux47.IN2
AddrC[1] => Mux32.IN1
AddrC[1] => Mux33.IN1
AddrC[1] => Mux34.IN1
AddrC[1] => Mux35.IN1
AddrC[1] => Mux36.IN1
AddrC[1] => Mux37.IN1
AddrC[1] => Mux38.IN1
AddrC[1] => Mux39.IN1
AddrC[1] => Mux40.IN1
AddrC[1] => Mux41.IN1
AddrC[1] => Mux42.IN1
AddrC[1] => Mux43.IN1
AddrC[1] => Mux44.IN1
AddrC[1] => Mux45.IN1
AddrC[1] => Mux46.IN1
AddrC[1] => Mux47.IN1
AddrC[2] => Mux32.IN0
AddrC[2] => Mux33.IN0
AddrC[2] => Mux34.IN0
AddrC[2] => Mux35.IN0
AddrC[2] => Mux36.IN0
AddrC[2] => Mux37.IN0
AddrC[2] => Mux38.IN0
AddrC[2] => Mux39.IN0
AddrC[2] => Mux40.IN0
AddrC[2] => Mux41.IN0
AddrC[2] => Mux42.IN0
AddrC[2] => Mux43.IN0
AddrC[2] => Mux44.IN0
AddrC[2] => Mux45.IN0
AddrC[2] => Mux46.IN0
AddrC[2] => Mux47.IN0
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[0] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[1] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[2] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[3] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[4] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[5] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[6] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIH[7] => RegsH.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[0] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[1] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[2] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[3] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[4] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[5] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[6] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DIL[7] => RegsL.DATAB
DOAH[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
DOAH[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
DOAH[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
DOAH[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
DOAH[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
DOAH[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
DOAH[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
DOAH[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
DOAL[0] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
DOAL[1] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
DOAL[2] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
DOAL[3] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
DOAL[4] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
DOAL[5] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
DOAL[6] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
DOAL[7] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
DOBH[0] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
DOBH[1] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
DOBH[2] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
DOBH[3] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
DOBH[4] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
DOBH[5] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
DOBH[6] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
DOBH[7] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
DOBL[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
DOBL[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
DOBL[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
DOBL[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
DOBL[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
DOBL[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
DOBL[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
DOBL[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
DOCH[0] <= Mux39.DB_MAX_OUTPUT_PORT_TYPE
DOCH[1] <= Mux38.DB_MAX_OUTPUT_PORT_TYPE
DOCH[2] <= Mux37.DB_MAX_OUTPUT_PORT_TYPE
DOCH[3] <= Mux36.DB_MAX_OUTPUT_PORT_TYPE
DOCH[4] <= Mux35.DB_MAX_OUTPUT_PORT_TYPE
DOCH[5] <= Mux34.DB_MAX_OUTPUT_PORT_TYPE
DOCH[6] <= Mux33.DB_MAX_OUTPUT_PORT_TYPE
DOCH[7] <= Mux32.DB_MAX_OUTPUT_PORT_TYPE
DOCL[0] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE
DOCL[1] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE
DOCL[2] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE
DOCL[3] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE
DOCL[4] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE
DOCL[5] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE
DOCL[6] <= Mux41.DB_MAX_OUTPUT_PORT_TYPE
DOCL[7] <= Mux40.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|video:video_inst
CLOCK_25 => VGA_SYNC:vga_sync_inst.clock_25Mhz
VRAM_DATA[0] => CRAM_ADDR[3].DATAIN
VRAM_DATA[1] => CRAM_ADDR[4].DATAIN
VRAM_DATA[2] => CRAM_ADDR[5].DATAIN
VRAM_DATA[3] => CRAM_ADDR[6].DATAIN
VRAM_DATA[4] => CRAM_ADDR[7].DATAIN
VRAM_DATA[5] => CRAM_ADDR[8].DATAIN
VRAM_DATA[6] => CRAM_ADDR[9].DATAIN
VRAM_DATA[7] => CRAM_ADDR[10].DATAIN
VRAM_ADDR[0] <= VGA_SYNC:vga_sync_inst.pixel_column[3]
VRAM_ADDR[1] <= VGA_SYNC:vga_sync_inst.pixel_column[4]
VRAM_ADDR[2] <= VGA_SYNC:vga_sync_inst.pixel_column[5]
VRAM_ADDR[3] <= VGA_SYNC:vga_sync_inst.pixel_column[6]
VRAM_ADDR[4] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[5] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[6] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[7] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[8] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[9] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[10] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[11] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[12] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_ADDR[13] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
VRAM_CLOCK <= VGA_SYNC:vga_sync_inst.pixel_clock
VRAM_WREN <= <VCC>
CRAM_DATA[0] => Mux0.IN3
CRAM_DATA[1] => Mux0.IN4
CRAM_DATA[2] => Mux0.IN5
CRAM_DATA[3] => Mux0.IN6
CRAM_DATA[4] => Mux0.IN7
CRAM_DATA[5] => Mux0.IN8
CRAM_DATA[6] => Mux0.IN9
CRAM_DATA[7] => Mux0.IN10
CRAM_ADDR[0] <= VGA_SYNC:vga_sync_inst.pixel_row[0]
CRAM_ADDR[1] <= VGA_SYNC:vga_sync_inst.pixel_row[1]
CRAM_ADDR[2] <= VGA_SYNC:vga_sync_inst.pixel_row[2]
CRAM_ADDR[3] <= VRAM_DATA[0].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[4] <= VRAM_DATA[1].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[5] <= VRAM_DATA[2].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[6] <= VRAM_DATA[3].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[7] <= VRAM_DATA[4].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[8] <= VRAM_DATA[5].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[9] <= VRAM_DATA[6].DB_MAX_OUTPUT_PORT_TYPE
CRAM_ADDR[10] <= VRAM_DATA[7].DB_MAX_OUTPUT_PORT_TYPE
CRAM_WEB <= <VCC>
VGA_R[0] <= VGA_SYNC:vga_sync_inst.red_out[0]
VGA_R[1] <= VGA_SYNC:vga_sync_inst.red_out[1]
VGA_R[2] <= VGA_SYNC:vga_sync_inst.red_out[2]
VGA_R[3] <= VGA_SYNC:vga_sync_inst.red_out[3]
VGA_G[0] <= VGA_SYNC:vga_sync_inst.green_out[0]
VGA_G[1] <= VGA_SYNC:vga_sync_inst.green_out[1]
VGA_G[2] <= VGA_SYNC:vga_sync_inst.green_out[2]
VGA_G[3] <= VGA_SYNC:vga_sync_inst.green_out[3]
VGA_B[0] <= VGA_SYNC:vga_sync_inst.blue_out[0]
VGA_B[1] <= VGA_SYNC:vga_sync_inst.blue_out[1]
VGA_B[2] <= VGA_SYNC:vga_sync_inst.blue_out[2]
VGA_B[3] <= VGA_SYNC:vga_sync_inst.blue_out[3]
VGA_HS <= VGA_SYNC:vga_sync_inst.horiz_sync_out
VGA_VS <= VGA_SYNC:vga_sync_inst.vert_sync_out


|z80soc|video:video_inst|VGA_SYNC:vga_sync_inst
clock_25Mhz => blue_out[0]~reg0.CLK
clock_25Mhz => blue_out[1]~reg0.CLK
clock_25Mhz => blue_out[2]~reg0.CLK
clock_25Mhz => blue_out[3]~reg0.CLK
clock_25Mhz => green_out[0]~reg0.CLK
clock_25Mhz => green_out[1]~reg0.CLK
clock_25Mhz => green_out[2]~reg0.CLK
clock_25Mhz => green_out[3]~reg0.CLK
clock_25Mhz => red_out[0]~reg0.CLK
clock_25Mhz => red_out[1]~reg0.CLK
clock_25Mhz => red_out[2]~reg0.CLK
clock_25Mhz => red_out[3]~reg0.CLK
clock_25Mhz => vert_sync_out~reg0.CLK
clock_25Mhz => horiz_sync_out~reg0.CLK
clock_25Mhz => pixel_row[0]~reg0.CLK
clock_25Mhz => pixel_row[1]~reg0.CLK
clock_25Mhz => pixel_row[2]~reg0.CLK
clock_25Mhz => pixel_row[3]~reg0.CLK
clock_25Mhz => pixel_row[4]~reg0.CLK
clock_25Mhz => pixel_row[5]~reg0.CLK
clock_25Mhz => pixel_row[6]~reg0.CLK
clock_25Mhz => pixel_row[7]~reg0.CLK
clock_25Mhz => pixel_row[8]~reg0.CLK
clock_25Mhz => pixel_row[9]~reg0.CLK
clock_25Mhz => video_on_v.CLK
clock_25Mhz => pixel_column[0]~reg0.CLK
clock_25Mhz => pixel_column[1]~reg0.CLK
clock_25Mhz => pixel_column[2]~reg0.CLK
clock_25Mhz => pixel_column[3]~reg0.CLK
clock_25Mhz => pixel_column[4]~reg0.CLK
clock_25Mhz => pixel_column[5]~reg0.CLK
clock_25Mhz => pixel_column[6]~reg0.CLK
clock_25Mhz => pixel_column[7]~reg0.CLK
clock_25Mhz => pixel_column[8]~reg0.CLK
clock_25Mhz => pixel_column[9]~reg0.CLK
clock_25Mhz => video_on_h.CLK
clock_25Mhz => vert_sync.CLK
clock_25Mhz => v_count[0].CLK
clock_25Mhz => v_count[1].CLK
clock_25Mhz => v_count[2].CLK
clock_25Mhz => v_count[3].CLK
clock_25Mhz => v_count[4].CLK
clock_25Mhz => v_count[5].CLK
clock_25Mhz => v_count[6].CLK
clock_25Mhz => v_count[7].CLK
clock_25Mhz => v_count[8].CLK
clock_25Mhz => v_count[9].CLK
clock_25Mhz => horiz_sync.CLK
clock_25Mhz => h_count[0].CLK
clock_25Mhz => h_count[1].CLK
clock_25Mhz => h_count[2].CLK
clock_25Mhz => h_count[3].CLK
clock_25Mhz => h_count[4].CLK
clock_25Mhz => h_count[5].CLK
clock_25Mhz => h_count[6].CLK
clock_25Mhz => h_count[7].CLK
clock_25Mhz => h_count[8].CLK
clock_25Mhz => h_count[9].CLK
clock_25Mhz => pixel_clock.DATAIN
red[0] => red_out.IN1
red[1] => red_out.IN1
red[2] => red_out.IN1
red[3] => red_out.IN1
green[0] => green_out.IN1
green[1] => green_out.IN1
green[2] => green_out.IN1
green[3] => green_out.IN1
blue[0] => blue_out.IN1
blue[1] => blue_out.IN1
blue[2] => blue_out.IN1
blue[3] => blue_out.IN1
red_out[0] <= red_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_out[1] <= red_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_out[2] <= red_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
red_out[3] <= red_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
green_out[0] <= green_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
green_out[1] <= green_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
green_out[2] <= green_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
green_out[3] <= green_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
blue_out[0] <= blue_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
blue_out[1] <= blue_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
blue_out[2] <= blue_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
blue_out[3] <= blue_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
horiz_sync_out <= horiz_sync_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
vert_sync_out <= vert_sync_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
video_on <= video_on_int.DB_MAX_OUTPUT_PORT_TYPE
pixel_clock <= clock_25Mhz.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[0] <= pixel_row[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[1] <= pixel_row[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[2] <= pixel_row[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[3] <= pixel_row[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[4] <= pixel_row[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[5] <= pixel_row[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[6] <= pixel_row[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[7] <= pixel_row[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[8] <= pixel_row[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_row[9] <= pixel_row[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[0] <= pixel_column[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[1] <= pixel_column[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[2] <= pixel_column[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[3] <= pixel_column[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[4] <= pixel_column[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[5] <= pixel_column[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[6] <= pixel_column[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[7] <= pixel_column[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[8] <= pixel_column[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pixel_column[9] <= pixel_column[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|vram:vram_inst
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
rdaddress[11] => altsyncram:altsyncram_component.address_b[11]
rdaddress[12] => altsyncram:altsyncram_component.address_b[12]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
wraddress[11] => altsyncram:altsyncram_component.address_a[11]
wraddress[12] => altsyncram:altsyncram_component.address_a[12]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|z80soc|vram:vram_inst|altsyncram:altsyncram_component
wren_a => altsyncram_66l1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_66l1:auto_generated.data_a[0]
data_a[1] => altsyncram_66l1:auto_generated.data_a[1]
data_a[2] => altsyncram_66l1:auto_generated.data_a[2]
data_a[3] => altsyncram_66l1:auto_generated.data_a[3]
data_a[4] => altsyncram_66l1:auto_generated.data_a[4]
data_a[5] => altsyncram_66l1:auto_generated.data_a[5]
data_a[6] => altsyncram_66l1:auto_generated.data_a[6]
data_a[7] => altsyncram_66l1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_66l1:auto_generated.address_a[0]
address_a[1] => altsyncram_66l1:auto_generated.address_a[1]
address_a[2] => altsyncram_66l1:auto_generated.address_a[2]
address_a[3] => altsyncram_66l1:auto_generated.address_a[3]
address_a[4] => altsyncram_66l1:auto_generated.address_a[4]
address_a[5] => altsyncram_66l1:auto_generated.address_a[5]
address_a[6] => altsyncram_66l1:auto_generated.address_a[6]
address_a[7] => altsyncram_66l1:auto_generated.address_a[7]
address_a[8] => altsyncram_66l1:auto_generated.address_a[8]
address_a[9] => altsyncram_66l1:auto_generated.address_a[9]
address_a[10] => altsyncram_66l1:auto_generated.address_a[10]
address_a[11] => altsyncram_66l1:auto_generated.address_a[11]
address_a[12] => altsyncram_66l1:auto_generated.address_a[12]
address_b[0] => altsyncram_66l1:auto_generated.address_b[0]
address_b[1] => altsyncram_66l1:auto_generated.address_b[1]
address_b[2] => altsyncram_66l1:auto_generated.address_b[2]
address_b[3] => altsyncram_66l1:auto_generated.address_b[3]
address_b[4] => altsyncram_66l1:auto_generated.address_b[4]
address_b[5] => altsyncram_66l1:auto_generated.address_b[5]
address_b[6] => altsyncram_66l1:auto_generated.address_b[6]
address_b[7] => altsyncram_66l1:auto_generated.address_b[7]
address_b[8] => altsyncram_66l1:auto_generated.address_b[8]
address_b[9] => altsyncram_66l1:auto_generated.address_b[9]
address_b[10] => altsyncram_66l1:auto_generated.address_b[10]
address_b[11] => altsyncram_66l1:auto_generated.address_b[11]
address_b[12] => altsyncram_66l1:auto_generated.address_b[12]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_66l1:auto_generated.clock0
clock1 => altsyncram_66l1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_66l1:auto_generated.q_b[0]
q_b[1] <= altsyncram_66l1:auto_generated.q_b[1]
q_b[2] <= altsyncram_66l1:auto_generated.q_b[2]
q_b[3] <= altsyncram_66l1:auto_generated.q_b[3]
q_b[4] <= altsyncram_66l1:auto_generated.q_b[4]
q_b[5] <= altsyncram_66l1:auto_generated.q_b[5]
q_b[6] <= altsyncram_66l1:auto_generated.q_b[6]
q_b[7] <= altsyncram_66l1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated
address_a[0] => altsyncram_pal1:altsyncram1.address_b[0]
address_a[1] => altsyncram_pal1:altsyncram1.address_b[1]
address_a[2] => altsyncram_pal1:altsyncram1.address_b[2]
address_a[3] => altsyncram_pal1:altsyncram1.address_b[3]
address_a[4] => altsyncram_pal1:altsyncram1.address_b[4]
address_a[5] => altsyncram_pal1:altsyncram1.address_b[5]
address_a[6] => altsyncram_pal1:altsyncram1.address_b[6]
address_a[7] => altsyncram_pal1:altsyncram1.address_b[7]
address_a[8] => altsyncram_pal1:altsyncram1.address_b[8]
address_a[9] => altsyncram_pal1:altsyncram1.address_b[9]
address_a[10] => altsyncram_pal1:altsyncram1.address_b[10]
address_a[11] => altsyncram_pal1:altsyncram1.address_b[11]
address_a[12] => altsyncram_pal1:altsyncram1.address_b[12]
address_b[0] => altsyncram_pal1:altsyncram1.address_a[0]
address_b[1] => altsyncram_pal1:altsyncram1.address_a[1]
address_b[2] => altsyncram_pal1:altsyncram1.address_a[2]
address_b[3] => altsyncram_pal1:altsyncram1.address_a[3]
address_b[4] => altsyncram_pal1:altsyncram1.address_a[4]
address_b[5] => altsyncram_pal1:altsyncram1.address_a[5]
address_b[6] => altsyncram_pal1:altsyncram1.address_a[6]
address_b[7] => altsyncram_pal1:altsyncram1.address_a[7]
address_b[8] => altsyncram_pal1:altsyncram1.address_a[8]
address_b[9] => altsyncram_pal1:altsyncram1.address_a[9]
address_b[10] => altsyncram_pal1:altsyncram1.address_a[10]
address_b[11] => altsyncram_pal1:altsyncram1.address_a[11]
address_b[12] => altsyncram_pal1:altsyncram1.address_a[12]
clock0 => altsyncram_pal1:altsyncram1.clock1
clock1 => altsyncram_pal1:altsyncram1.clock0
data_a[0] => altsyncram_pal1:altsyncram1.data_b[0]
data_a[1] => altsyncram_pal1:altsyncram1.data_b[1]
data_a[2] => altsyncram_pal1:altsyncram1.data_b[2]
data_a[3] => altsyncram_pal1:altsyncram1.data_b[3]
data_a[4] => altsyncram_pal1:altsyncram1.data_b[4]
data_a[5] => altsyncram_pal1:altsyncram1.data_b[5]
data_a[6] => altsyncram_pal1:altsyncram1.data_b[6]
data_a[7] => altsyncram_pal1:altsyncram1.data_b[7]
q_b[0] <= altsyncram_pal1:altsyncram1.q_a[0]
q_b[1] <= altsyncram_pal1:altsyncram1.q_a[1]
q_b[2] <= altsyncram_pal1:altsyncram1.q_a[2]
q_b[3] <= altsyncram_pal1:altsyncram1.q_a[3]
q_b[4] <= altsyncram_pal1:altsyncram1.q_a[4]
q_b[5] <= altsyncram_pal1:altsyncram1.q_a[5]
q_b[6] <= altsyncram_pal1:altsyncram1.q_a[6]
q_b[7] <= altsyncram_pal1:altsyncram1.q_a[7]
wren_a => altsyncram_pal1:altsyncram1.clocken1
wren_a => altsyncram_pal1:altsyncram1.wren_b


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[1] => ram_block2a8.PORTAADDR1
address_a[1] => ram_block2a9.PORTAADDR1
address_a[1] => ram_block2a10.PORTAADDR1
address_a[1] => ram_block2a11.PORTAADDR1
address_a[1] => ram_block2a12.PORTAADDR1
address_a[1] => ram_block2a13.PORTAADDR1
address_a[1] => ram_block2a14.PORTAADDR1
address_a[1] => ram_block2a15.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[2] => ram_block2a8.PORTAADDR2
address_a[2] => ram_block2a9.PORTAADDR2
address_a[2] => ram_block2a10.PORTAADDR2
address_a[2] => ram_block2a11.PORTAADDR2
address_a[2] => ram_block2a12.PORTAADDR2
address_a[2] => ram_block2a13.PORTAADDR2
address_a[2] => ram_block2a14.PORTAADDR2
address_a[2] => ram_block2a15.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[3] => ram_block2a8.PORTAADDR3
address_a[3] => ram_block2a9.PORTAADDR3
address_a[3] => ram_block2a10.PORTAADDR3
address_a[3] => ram_block2a11.PORTAADDR3
address_a[3] => ram_block2a12.PORTAADDR3
address_a[3] => ram_block2a13.PORTAADDR3
address_a[3] => ram_block2a14.PORTAADDR3
address_a[3] => ram_block2a15.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[4] => ram_block2a8.PORTAADDR4
address_a[4] => ram_block2a9.PORTAADDR4
address_a[4] => ram_block2a10.PORTAADDR4
address_a[4] => ram_block2a11.PORTAADDR4
address_a[4] => ram_block2a12.PORTAADDR4
address_a[4] => ram_block2a13.PORTAADDR4
address_a[4] => ram_block2a14.PORTAADDR4
address_a[4] => ram_block2a15.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_a[5] => ram_block2a8.PORTAADDR5
address_a[5] => ram_block2a9.PORTAADDR5
address_a[5] => ram_block2a10.PORTAADDR5
address_a[5] => ram_block2a11.PORTAADDR5
address_a[5] => ram_block2a12.PORTAADDR5
address_a[5] => ram_block2a13.PORTAADDR5
address_a[5] => ram_block2a14.PORTAADDR5
address_a[5] => ram_block2a15.PORTAADDR5
address_a[6] => ram_block2a0.PORTAADDR6
address_a[6] => ram_block2a1.PORTAADDR6
address_a[6] => ram_block2a2.PORTAADDR6
address_a[6] => ram_block2a3.PORTAADDR6
address_a[6] => ram_block2a4.PORTAADDR6
address_a[6] => ram_block2a5.PORTAADDR6
address_a[6] => ram_block2a6.PORTAADDR6
address_a[6] => ram_block2a7.PORTAADDR6
address_a[6] => ram_block2a8.PORTAADDR6
address_a[6] => ram_block2a9.PORTAADDR6
address_a[6] => ram_block2a10.PORTAADDR6
address_a[6] => ram_block2a11.PORTAADDR6
address_a[6] => ram_block2a12.PORTAADDR6
address_a[6] => ram_block2a13.PORTAADDR6
address_a[6] => ram_block2a14.PORTAADDR6
address_a[6] => ram_block2a15.PORTAADDR6
address_a[7] => ram_block2a0.PORTAADDR7
address_a[7] => ram_block2a1.PORTAADDR7
address_a[7] => ram_block2a2.PORTAADDR7
address_a[7] => ram_block2a3.PORTAADDR7
address_a[7] => ram_block2a4.PORTAADDR7
address_a[7] => ram_block2a5.PORTAADDR7
address_a[7] => ram_block2a6.PORTAADDR7
address_a[7] => ram_block2a7.PORTAADDR7
address_a[7] => ram_block2a8.PORTAADDR7
address_a[7] => ram_block2a9.PORTAADDR7
address_a[7] => ram_block2a10.PORTAADDR7
address_a[7] => ram_block2a11.PORTAADDR7
address_a[7] => ram_block2a12.PORTAADDR7
address_a[7] => ram_block2a13.PORTAADDR7
address_a[7] => ram_block2a14.PORTAADDR7
address_a[7] => ram_block2a15.PORTAADDR7
address_a[8] => ram_block2a0.PORTAADDR8
address_a[8] => ram_block2a1.PORTAADDR8
address_a[8] => ram_block2a2.PORTAADDR8
address_a[8] => ram_block2a3.PORTAADDR8
address_a[8] => ram_block2a4.PORTAADDR8
address_a[8] => ram_block2a5.PORTAADDR8
address_a[8] => ram_block2a6.PORTAADDR8
address_a[8] => ram_block2a7.PORTAADDR8
address_a[8] => ram_block2a8.PORTAADDR8
address_a[8] => ram_block2a9.PORTAADDR8
address_a[8] => ram_block2a10.PORTAADDR8
address_a[8] => ram_block2a11.PORTAADDR8
address_a[8] => ram_block2a12.PORTAADDR8
address_a[8] => ram_block2a13.PORTAADDR8
address_a[8] => ram_block2a14.PORTAADDR8
address_a[8] => ram_block2a15.PORTAADDR8
address_a[9] => ram_block2a0.PORTAADDR9
address_a[9] => ram_block2a1.PORTAADDR9
address_a[9] => ram_block2a2.PORTAADDR9
address_a[9] => ram_block2a3.PORTAADDR9
address_a[9] => ram_block2a4.PORTAADDR9
address_a[9] => ram_block2a5.PORTAADDR9
address_a[9] => ram_block2a6.PORTAADDR9
address_a[9] => ram_block2a7.PORTAADDR9
address_a[9] => ram_block2a8.PORTAADDR9
address_a[9] => ram_block2a9.PORTAADDR9
address_a[9] => ram_block2a10.PORTAADDR9
address_a[9] => ram_block2a11.PORTAADDR9
address_a[9] => ram_block2a12.PORTAADDR9
address_a[9] => ram_block2a13.PORTAADDR9
address_a[9] => ram_block2a14.PORTAADDR9
address_a[9] => ram_block2a15.PORTAADDR9
address_a[10] => ram_block2a0.PORTAADDR10
address_a[10] => ram_block2a1.PORTAADDR10
address_a[10] => ram_block2a2.PORTAADDR10
address_a[10] => ram_block2a3.PORTAADDR10
address_a[10] => ram_block2a4.PORTAADDR10
address_a[10] => ram_block2a5.PORTAADDR10
address_a[10] => ram_block2a6.PORTAADDR10
address_a[10] => ram_block2a7.PORTAADDR10
address_a[10] => ram_block2a8.PORTAADDR10
address_a[10] => ram_block2a9.PORTAADDR10
address_a[10] => ram_block2a10.PORTAADDR10
address_a[10] => ram_block2a11.PORTAADDR10
address_a[10] => ram_block2a12.PORTAADDR10
address_a[10] => ram_block2a13.PORTAADDR10
address_a[10] => ram_block2a14.PORTAADDR10
address_a[10] => ram_block2a15.PORTAADDR10
address_a[11] => ram_block2a0.PORTAADDR11
address_a[11] => ram_block2a1.PORTAADDR11
address_a[11] => ram_block2a2.PORTAADDR11
address_a[11] => ram_block2a3.PORTAADDR11
address_a[11] => ram_block2a4.PORTAADDR11
address_a[11] => ram_block2a5.PORTAADDR11
address_a[11] => ram_block2a6.PORTAADDR11
address_a[11] => ram_block2a7.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_1oa:decode3.data[0]
address_a[12] => decode_1oa:decode_a.data[0]
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[0] => ram_block2a10.PORTBADDR
address_b[0] => ram_block2a11.PORTBADDR
address_b[0] => ram_block2a12.PORTBADDR
address_b[0] => ram_block2a13.PORTBADDR
address_b[0] => ram_block2a14.PORTBADDR
address_b[0] => ram_block2a15.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[1] => ram_block2a10.PORTBADDR1
address_b[1] => ram_block2a11.PORTBADDR1
address_b[1] => ram_block2a12.PORTBADDR1
address_b[1] => ram_block2a13.PORTBADDR1
address_b[1] => ram_block2a14.PORTBADDR1
address_b[1] => ram_block2a15.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[2] => ram_block2a10.PORTBADDR2
address_b[2] => ram_block2a11.PORTBADDR2
address_b[2] => ram_block2a12.PORTBADDR2
address_b[2] => ram_block2a13.PORTBADDR2
address_b[2] => ram_block2a14.PORTBADDR2
address_b[2] => ram_block2a15.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
address_b[3] => ram_block2a10.PORTBADDR3
address_b[3] => ram_block2a11.PORTBADDR3
address_b[3] => ram_block2a12.PORTBADDR3
address_b[3] => ram_block2a13.PORTBADDR3
address_b[3] => ram_block2a14.PORTBADDR3
address_b[3] => ram_block2a15.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[4] => ram_block2a8.PORTBADDR4
address_b[4] => ram_block2a9.PORTBADDR4
address_b[4] => ram_block2a10.PORTBADDR4
address_b[4] => ram_block2a11.PORTBADDR4
address_b[4] => ram_block2a12.PORTBADDR4
address_b[4] => ram_block2a13.PORTBADDR4
address_b[4] => ram_block2a14.PORTBADDR4
address_b[4] => ram_block2a15.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[5] => ram_block2a8.PORTBADDR5
address_b[5] => ram_block2a9.PORTBADDR5
address_b[5] => ram_block2a10.PORTBADDR5
address_b[5] => ram_block2a11.PORTBADDR5
address_b[5] => ram_block2a12.PORTBADDR5
address_b[5] => ram_block2a13.PORTBADDR5
address_b[5] => ram_block2a14.PORTBADDR5
address_b[5] => ram_block2a15.PORTBADDR5
address_b[6] => ram_block2a0.PORTBADDR6
address_b[6] => ram_block2a1.PORTBADDR6
address_b[6] => ram_block2a2.PORTBADDR6
address_b[6] => ram_block2a3.PORTBADDR6
address_b[6] => ram_block2a4.PORTBADDR6
address_b[6] => ram_block2a5.PORTBADDR6
address_b[6] => ram_block2a6.PORTBADDR6
address_b[6] => ram_block2a7.PORTBADDR6
address_b[6] => ram_block2a8.PORTBADDR6
address_b[6] => ram_block2a9.PORTBADDR6
address_b[6] => ram_block2a10.PORTBADDR6
address_b[6] => ram_block2a11.PORTBADDR6
address_b[6] => ram_block2a12.PORTBADDR6
address_b[6] => ram_block2a13.PORTBADDR6
address_b[6] => ram_block2a14.PORTBADDR6
address_b[6] => ram_block2a15.PORTBADDR6
address_b[7] => ram_block2a0.PORTBADDR7
address_b[7] => ram_block2a1.PORTBADDR7
address_b[7] => ram_block2a2.PORTBADDR7
address_b[7] => ram_block2a3.PORTBADDR7
address_b[7] => ram_block2a4.PORTBADDR7
address_b[7] => ram_block2a5.PORTBADDR7
address_b[7] => ram_block2a6.PORTBADDR7
address_b[7] => ram_block2a7.PORTBADDR7
address_b[7] => ram_block2a8.PORTBADDR7
address_b[7] => ram_block2a9.PORTBADDR7
address_b[7] => ram_block2a10.PORTBADDR7
address_b[7] => ram_block2a11.PORTBADDR7
address_b[7] => ram_block2a12.PORTBADDR7
address_b[7] => ram_block2a13.PORTBADDR7
address_b[7] => ram_block2a14.PORTBADDR7
address_b[7] => ram_block2a15.PORTBADDR7
address_b[8] => ram_block2a0.PORTBADDR8
address_b[8] => ram_block2a1.PORTBADDR8
address_b[8] => ram_block2a2.PORTBADDR8
address_b[8] => ram_block2a3.PORTBADDR8
address_b[8] => ram_block2a4.PORTBADDR8
address_b[8] => ram_block2a5.PORTBADDR8
address_b[8] => ram_block2a6.PORTBADDR8
address_b[8] => ram_block2a7.PORTBADDR8
address_b[8] => ram_block2a8.PORTBADDR8
address_b[8] => ram_block2a9.PORTBADDR8
address_b[8] => ram_block2a10.PORTBADDR8
address_b[8] => ram_block2a11.PORTBADDR8
address_b[8] => ram_block2a12.PORTBADDR8
address_b[8] => ram_block2a13.PORTBADDR8
address_b[8] => ram_block2a14.PORTBADDR8
address_b[8] => ram_block2a15.PORTBADDR8
address_b[9] => ram_block2a0.PORTBADDR9
address_b[9] => ram_block2a1.PORTBADDR9
address_b[9] => ram_block2a2.PORTBADDR9
address_b[9] => ram_block2a3.PORTBADDR9
address_b[9] => ram_block2a4.PORTBADDR9
address_b[9] => ram_block2a5.PORTBADDR9
address_b[9] => ram_block2a6.PORTBADDR9
address_b[9] => ram_block2a7.PORTBADDR9
address_b[9] => ram_block2a8.PORTBADDR9
address_b[9] => ram_block2a9.PORTBADDR9
address_b[9] => ram_block2a10.PORTBADDR9
address_b[9] => ram_block2a11.PORTBADDR9
address_b[9] => ram_block2a12.PORTBADDR9
address_b[9] => ram_block2a13.PORTBADDR9
address_b[9] => ram_block2a14.PORTBADDR9
address_b[9] => ram_block2a15.PORTBADDR9
address_b[10] => ram_block2a0.PORTBADDR10
address_b[10] => ram_block2a1.PORTBADDR10
address_b[10] => ram_block2a2.PORTBADDR10
address_b[10] => ram_block2a3.PORTBADDR10
address_b[10] => ram_block2a4.PORTBADDR10
address_b[10] => ram_block2a5.PORTBADDR10
address_b[10] => ram_block2a6.PORTBADDR10
address_b[10] => ram_block2a7.PORTBADDR10
address_b[10] => ram_block2a8.PORTBADDR10
address_b[10] => ram_block2a9.PORTBADDR10
address_b[10] => ram_block2a10.PORTBADDR10
address_b[10] => ram_block2a11.PORTBADDR10
address_b[10] => ram_block2a12.PORTBADDR10
address_b[10] => ram_block2a13.PORTBADDR10
address_b[10] => ram_block2a14.PORTBADDR10
address_b[10] => ram_block2a15.PORTBADDR10
address_b[11] => ram_block2a0.PORTBADDR11
address_b[11] => ram_block2a1.PORTBADDR11
address_b[11] => ram_block2a2.PORTBADDR11
address_b[11] => ram_block2a3.PORTBADDR11
address_b[11] => ram_block2a4.PORTBADDR11
address_b[11] => ram_block2a5.PORTBADDR11
address_b[11] => ram_block2a6.PORTBADDR11
address_b[11] => ram_block2a7.PORTBADDR11
address_b[12] => address_reg_b[0].DATAIN
address_b[12] => decode_1oa:decode4.data[0]
address_b[12] => decode_1oa:decode_b.data[0]
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock0 => address_reg_a[0].CLK
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clock1 => address_reg_b[0].CLK
clocken1 => ~NO_FANOUT~
data_a[0] => ram_block2a0.PORTADATAIN
data_a[0] => ram_block2a8.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[1] => ram_block2a9.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[2] => ram_block2a10.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[3] => ram_block2a11.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[4] => ram_block2a12.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[5] => ram_block2a13.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[6] => ram_block2a14.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[7] => ram_block2a15.PORTADATAIN
data_b[0] => ram_block2a0.PORTBDATAIN
data_b[0] => ram_block2a8.PORTBDATAIN
data_b[1] => ram_block2a1.PORTBDATAIN
data_b[1] => ram_block2a9.PORTBDATAIN
data_b[2] => ram_block2a2.PORTBDATAIN
data_b[2] => ram_block2a10.PORTBDATAIN
data_b[3] => ram_block2a3.PORTBDATAIN
data_b[3] => ram_block2a11.PORTBDATAIN
data_b[4] => ram_block2a4.PORTBDATAIN
data_b[4] => ram_block2a12.PORTBDATAIN
data_b[5] => ram_block2a5.PORTBDATAIN
data_b[5] => ram_block2a13.PORTBDATAIN
data_b[6] => ram_block2a6.PORTBDATAIN
data_b[6] => ram_block2a14.PORTBDATAIN
data_b[7] => ram_block2a7.PORTBDATAIN
data_b[7] => ram_block2a15.PORTBDATAIN
q_a[0] <= mux_hib:mux5.result[0]
q_a[1] <= mux_hib:mux5.result[1]
q_a[2] <= mux_hib:mux5.result[2]
q_a[3] <= mux_hib:mux5.result[3]
q_a[4] <= mux_hib:mux5.result[4]
q_a[5] <= mux_hib:mux5.result[5]
q_a[6] <= mux_hib:mux5.result[6]
q_a[7] <= mux_hib:mux5.result[7]
q_b[0] <= mux_hib:mux6.result[0]
q_b[1] <= mux_hib:mux6.result[1]
q_b[2] <= mux_hib:mux6.result[2]
q_b[3] <= mux_hib:mux6.result[3]
q_b[4] <= mux_hib:mux6.result[4]
q_b[5] <= mux_hib:mux6.result[5]
q_b[6] <= mux_hib:mux6.result[6]
q_b[7] <= mux_hib:mux6.result[7]
wren_a => decode_1oa:decode3.enable
wren_b => decode_1oa:decode4.enable


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode3
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode4
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode_a
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode_b
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux5
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|z80soc|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux6
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


|z80soc|charram:cram
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|z80soc|charram:cram|altsyncram:altsyncram_component
wren_a => altsyncram_h1o1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_h1o1:auto_generated.data_a[0]
data_a[1] => altsyncram_h1o1:auto_generated.data_a[1]
data_a[2] => altsyncram_h1o1:auto_generated.data_a[2]
data_a[3] => altsyncram_h1o1:auto_generated.data_a[3]
data_a[4] => altsyncram_h1o1:auto_generated.data_a[4]
data_a[5] => altsyncram_h1o1:auto_generated.data_a[5]
data_a[6] => altsyncram_h1o1:auto_generated.data_a[6]
data_a[7] => altsyncram_h1o1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_h1o1:auto_generated.address_a[0]
address_a[1] => altsyncram_h1o1:auto_generated.address_a[1]
address_a[2] => altsyncram_h1o1:auto_generated.address_a[2]
address_a[3] => altsyncram_h1o1:auto_generated.address_a[3]
address_a[4] => altsyncram_h1o1:auto_generated.address_a[4]
address_a[5] => altsyncram_h1o1:auto_generated.address_a[5]
address_a[6] => altsyncram_h1o1:auto_generated.address_a[6]
address_a[7] => altsyncram_h1o1:auto_generated.address_a[7]
address_a[8] => altsyncram_h1o1:auto_generated.address_a[8]
address_a[9] => altsyncram_h1o1:auto_generated.address_a[9]
address_a[10] => altsyncram_h1o1:auto_generated.address_a[10]
address_b[0] => altsyncram_h1o1:auto_generated.address_b[0]
address_b[1] => altsyncram_h1o1:auto_generated.address_b[1]
address_b[2] => altsyncram_h1o1:auto_generated.address_b[2]
address_b[3] => altsyncram_h1o1:auto_generated.address_b[3]
address_b[4] => altsyncram_h1o1:auto_generated.address_b[4]
address_b[5] => altsyncram_h1o1:auto_generated.address_b[5]
address_b[6] => altsyncram_h1o1:auto_generated.address_b[6]
address_b[7] => altsyncram_h1o1:auto_generated.address_b[7]
address_b[8] => altsyncram_h1o1:auto_generated.address_b[8]
address_b[9] => altsyncram_h1o1:auto_generated.address_b[9]
address_b[10] => altsyncram_h1o1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_h1o1:auto_generated.clock0
clock1 => altsyncram_h1o1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_h1o1:auto_generated.q_b[0]
q_b[1] <= altsyncram_h1o1:auto_generated.q_b[1]
q_b[2] <= altsyncram_h1o1:auto_generated.q_b[2]
q_b[3] <= altsyncram_h1o1:auto_generated.q_b[3]
q_b[4] <= altsyncram_h1o1:auto_generated.q_b[4]
q_b[5] <= altsyncram_h1o1:auto_generated.q_b[5]
q_b[6] <= altsyncram_h1o1:auto_generated.q_b[6]
q_b[7] <= altsyncram_h1o1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|z80soc|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated
address_a[0] => altsyncram_36o1:altsyncram1.address_b[0]
address_a[1] => altsyncram_36o1:altsyncram1.address_b[1]
address_a[2] => altsyncram_36o1:altsyncram1.address_b[2]
address_a[3] => altsyncram_36o1:altsyncram1.address_b[3]
address_a[4] => altsyncram_36o1:altsyncram1.address_b[4]
address_a[5] => altsyncram_36o1:altsyncram1.address_b[5]
address_a[6] => altsyncram_36o1:altsyncram1.address_b[6]
address_a[7] => altsyncram_36o1:altsyncram1.address_b[7]
address_a[8] => altsyncram_36o1:altsyncram1.address_b[8]
address_a[9] => altsyncram_36o1:altsyncram1.address_b[9]
address_a[10] => altsyncram_36o1:altsyncram1.address_b[10]
address_b[0] => altsyncram_36o1:altsyncram1.address_a[0]
address_b[1] => altsyncram_36o1:altsyncram1.address_a[1]
address_b[2] => altsyncram_36o1:altsyncram1.address_a[2]
address_b[3] => altsyncram_36o1:altsyncram1.address_a[3]
address_b[4] => altsyncram_36o1:altsyncram1.address_a[4]
address_b[5] => altsyncram_36o1:altsyncram1.address_a[5]
address_b[6] => altsyncram_36o1:altsyncram1.address_a[6]
address_b[7] => altsyncram_36o1:altsyncram1.address_a[7]
address_b[8] => altsyncram_36o1:altsyncram1.address_a[8]
address_b[9] => altsyncram_36o1:altsyncram1.address_a[9]
address_b[10] => altsyncram_36o1:altsyncram1.address_a[10]
clock0 => altsyncram_36o1:altsyncram1.clock1
clock1 => altsyncram_36o1:altsyncram1.clock0
data_a[0] => altsyncram_36o1:altsyncram1.data_b[0]
data_a[1] => altsyncram_36o1:altsyncram1.data_b[1]
data_a[2] => altsyncram_36o1:altsyncram1.data_b[2]
data_a[3] => altsyncram_36o1:altsyncram1.data_b[3]
data_a[4] => altsyncram_36o1:altsyncram1.data_b[4]
data_a[5] => altsyncram_36o1:altsyncram1.data_b[5]
data_a[6] => altsyncram_36o1:altsyncram1.data_b[6]
data_a[7] => altsyncram_36o1:altsyncram1.data_b[7]
q_b[0] <= altsyncram_36o1:altsyncram1.q_a[0]
q_b[1] <= altsyncram_36o1:altsyncram1.q_a[1]
q_b[2] <= altsyncram_36o1:altsyncram1.q_a[2]
q_b[3] <= altsyncram_36o1:altsyncram1.q_a[3]
q_b[4] <= altsyncram_36o1:altsyncram1.q_a[4]
q_b[5] <= altsyncram_36o1:altsyncram1.q_a[5]
q_b[6] <= altsyncram_36o1:altsyncram1.q_a[6]
q_b[7] <= altsyncram_36o1:altsyncram1.q_a[7]
wren_a => altsyncram_36o1:altsyncram1.clocken1
wren_a => altsyncram_36o1:altsyncram1.wren_b


|z80soc|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_a[6] => ram_block2a0.PORTAADDR6
address_a[6] => ram_block2a1.PORTAADDR6
address_a[6] => ram_block2a2.PORTAADDR6
address_a[6] => ram_block2a3.PORTAADDR6
address_a[6] => ram_block2a4.PORTAADDR6
address_a[6] => ram_block2a5.PORTAADDR6
address_a[6] => ram_block2a6.PORTAADDR6
address_a[6] => ram_block2a7.PORTAADDR6
address_a[7] => ram_block2a0.PORTAADDR7
address_a[7] => ram_block2a1.PORTAADDR7
address_a[7] => ram_block2a2.PORTAADDR7
address_a[7] => ram_block2a3.PORTAADDR7
address_a[7] => ram_block2a4.PORTAADDR7
address_a[7] => ram_block2a5.PORTAADDR7
address_a[7] => ram_block2a6.PORTAADDR7
address_a[7] => ram_block2a7.PORTAADDR7
address_a[8] => ram_block2a0.PORTAADDR8
address_a[8] => ram_block2a1.PORTAADDR8
address_a[8] => ram_block2a2.PORTAADDR8
address_a[8] => ram_block2a3.PORTAADDR8
address_a[8] => ram_block2a4.PORTAADDR8
address_a[8] => ram_block2a5.PORTAADDR8
address_a[8] => ram_block2a6.PORTAADDR8
address_a[8] => ram_block2a7.PORTAADDR8
address_a[9] => ram_block2a0.PORTAADDR9
address_a[9] => ram_block2a1.PORTAADDR9
address_a[9] => ram_block2a2.PORTAADDR9
address_a[9] => ram_block2a3.PORTAADDR9
address_a[9] => ram_block2a4.PORTAADDR9
address_a[9] => ram_block2a5.PORTAADDR9
address_a[9] => ram_block2a6.PORTAADDR9
address_a[9] => ram_block2a7.PORTAADDR9
address_a[10] => ram_block2a0.PORTAADDR10
address_a[10] => ram_block2a1.PORTAADDR10
address_a[10] => ram_block2a2.PORTAADDR10
address_a[10] => ram_block2a3.PORTAADDR10
address_a[10] => ram_block2a4.PORTAADDR10
address_a[10] => ram_block2a5.PORTAADDR10
address_a[10] => ram_block2a6.PORTAADDR10
address_a[10] => ram_block2a7.PORTAADDR10
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[6] => ram_block2a0.PORTBADDR6
address_b[6] => ram_block2a1.PORTBADDR6
address_b[6] => ram_block2a2.PORTBADDR6
address_b[6] => ram_block2a3.PORTBADDR6
address_b[6] => ram_block2a4.PORTBADDR6
address_b[6] => ram_block2a5.PORTBADDR6
address_b[6] => ram_block2a6.PORTBADDR6
address_b[6] => ram_block2a7.PORTBADDR6
address_b[7] => ram_block2a0.PORTBADDR7
address_b[7] => ram_block2a1.PORTBADDR7
address_b[7] => ram_block2a2.PORTBADDR7
address_b[7] => ram_block2a3.PORTBADDR7
address_b[7] => ram_block2a4.PORTBADDR7
address_b[7] => ram_block2a5.PORTBADDR7
address_b[7] => ram_block2a6.PORTBADDR7
address_b[7] => ram_block2a7.PORTBADDR7
address_b[8] => ram_block2a0.PORTBADDR8
address_b[8] => ram_block2a1.PORTBADDR8
address_b[8] => ram_block2a2.PORTBADDR8
address_b[8] => ram_block2a3.PORTBADDR8
address_b[8] => ram_block2a4.PORTBADDR8
address_b[8] => ram_block2a5.PORTBADDR8
address_b[8] => ram_block2a6.PORTBADDR8
address_b[8] => ram_block2a7.PORTBADDR8
address_b[9] => ram_block2a0.PORTBADDR9
address_b[9] => ram_block2a1.PORTBADDR9
address_b[9] => ram_block2a2.PORTBADDR9
address_b[9] => ram_block2a3.PORTBADDR9
address_b[9] => ram_block2a4.PORTBADDR9
address_b[9] => ram_block2a5.PORTBADDR9
address_b[9] => ram_block2a6.PORTBADDR9
address_b[9] => ram_block2a7.PORTBADDR9
address_b[10] => ram_block2a0.PORTBADDR10
address_b[10] => ram_block2a1.PORTBADDR10
address_b[10] => ram_block2a2.PORTBADDR10
address_b[10] => ram_block2a3.PORTBADDR10
address_b[10] => ram_block2a4.PORTBADDR10
address_b[10] => ram_block2a5.PORTBADDR10
address_b[10] => ram_block2a6.PORTBADDR10
address_b[10] => ram_block2a7.PORTBADDR10
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_b[0] => ram_block2a0.PORTBDATAIN
data_b[1] => ram_block2a1.PORTBDATAIN
data_b[2] => ram_block2a2.PORTBDATAIN
data_b[3] => ram_block2a3.PORTBDATAIN
data_b[4] => ram_block2a4.PORTBDATAIN
data_b[5] => ram_block2a5.PORTBDATAIN
data_b[6] => ram_block2a6.PORTBDATAIN
data_b[7] => ram_block2a7.PORTBDATAIN
q_a[0] <= ram_block2a0.PORTADATAOUT
q_a[1] <= ram_block2a1.PORTADATAOUT
q_a[2] <= ram_block2a2.PORTADATAOUT
q_a[3] <= ram_block2a3.PORTADATAOUT
q_a[4] <= ram_block2a4.PORTADATAOUT
q_a[5] <= ram_block2a5.PORTADATAOUT
q_a[6] <= ram_block2a6.PORTADATAOUT
q_a[7] <= ram_block2a7.PORTADATAOUT
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a7.PORTAWE
wren_b => ram_block2a0.PORTBRE
wren_b => ram_block2a1.PORTBRE
wren_b => ram_block2a2.PORTBRE
wren_b => ram_block2a3.PORTBRE
wren_b => ram_block2a4.PORTBRE
wren_b => ram_block2a5.PORTBRE
wren_b => ram_block2a6.PORTBRE
wren_b => ram_block2a7.PORTBRE


|z80soc|rom:rom_inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
address[12] => altsyncram:altsyncram_component.address_a[12]
address[13] => altsyncram:altsyncram_component.address_a[13]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|z80soc|rom:rom_inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_tr91:auto_generated.address_a[0]
address_a[1] => altsyncram_tr91:auto_generated.address_a[1]
address_a[2] => altsyncram_tr91:auto_generated.address_a[2]
address_a[3] => altsyncram_tr91:auto_generated.address_a[3]
address_a[4] => altsyncram_tr91:auto_generated.address_a[4]
address_a[5] => altsyncram_tr91:auto_generated.address_a[5]
address_a[6] => altsyncram_tr91:auto_generated.address_a[6]
address_a[7] => altsyncram_tr91:auto_generated.address_a[7]
address_a[8] => altsyncram_tr91:auto_generated.address_a[8]
address_a[9] => altsyncram_tr91:auto_generated.address_a[9]
address_a[10] => altsyncram_tr91:auto_generated.address_a[10]
address_a[11] => altsyncram_tr91:auto_generated.address_a[11]
address_a[12] => altsyncram_tr91:auto_generated.address_a[12]
address_a[13] => altsyncram_tr91:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_tr91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_tr91:auto_generated.q_a[0]
q_a[1] <= altsyncram_tr91:auto_generated.q_a[1]
q_a[2] <= altsyncram_tr91:auto_generated.q_a[2]
q_a[3] <= altsyncram_tr91:auto_generated.q_a[3]
q_a[4] <= altsyncram_tr91:auto_generated.q_a[4]
q_a[5] <= altsyncram_tr91:auto_generated.q_a[5]
q_a[6] <= altsyncram_tr91:auto_generated.q_a[6]
q_a[7] <= altsyncram_tr91:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|z80soc|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_4oa:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_4oa:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[1].CLK
clock0 => out_address_reg_a[0].CLK
q_a[0] <= mux_kib:mux2.result[0]
q_a[1] <= mux_kib:mux2.result[1]
q_a[2] <= mux_kib:mux2.result[2]
q_a[3] <= mux_kib:mux2.result[3]
q_a[4] <= mux_kib:mux2.result[4]
q_a[5] <= mux_kib:mux2.result[5]
q_a[6] <= mux_kib:mux2.result[6]
q_a[7] <= mux_kib:mux2.result[7]


|z80soc|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|decode_4oa:deep_decode
data[0] => w_anode141w[1].IN0
data[0] => w_anode154w[1].IN1
data[0] => w_anode162w[1].IN0
data[0] => w_anode170w[1].IN1
data[1] => w_anode141w[2].IN0
data[1] => w_anode154w[2].IN0
data[1] => w_anode162w[2].IN1
data[1] => w_anode170w[2].IN1
enable => w_anode141w[1].IN0
enable => w_anode154w[1].IN0
enable => w_anode162w[1].IN0
enable => w_anode170w[1].IN0
eq[0] <= w_anode141w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode154w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode162w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode170w[2].DB_MAX_OUTPUT_PORT_TYPE


|z80soc|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|mux_kib:mux2
data[0] => _.IN0
data[0] => _.IN0
data[1] => _.IN0
data[1] => _.IN0
data[2] => _.IN0
data[2] => _.IN0
data[3] => _.IN0
data[3] => _.IN0
data[4] => _.IN0
data[4] => _.IN0
data[5] => _.IN0
data[5] => _.IN0
data[6] => _.IN0
data[6] => _.IN0
data[7] => _.IN0
data[7] => _.IN0
data[8] => _.IN0
data[9] => _.IN0
data[10] => _.IN0
data[11] => _.IN0
data[12] => _.IN0
data[13] => _.IN0
data[14] => _.IN0
data[15] => _.IN0
data[16] => _.IN1
data[16] => _.IN1
data[17] => _.IN1
data[17] => _.IN1
data[18] => _.IN1
data[18] => _.IN1
data[19] => _.IN1
data[19] => _.IN1
data[20] => _.IN1
data[20] => _.IN1
data[21] => _.IN1
data[21] => _.IN1
data[22] => _.IN1
data[22] => _.IN1
data[23] => _.IN1
data[23] => _.IN1
data[24] => _.IN0
data[25] => _.IN0
data[26] => _.IN0
data[27] => _.IN0
data[28] => _.IN0
data[29] => _.IN0
data[30] => _.IN0
data[31] => _.IN0
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN1
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[0] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0
sel[1] => _.IN0


|z80soc|clk_div:clkdiv_inst
clock_in_50Mhz => clock_357Mhz_int.CLK
clock_in_50Mhz => count_357Mhz[0].CLK
clock_in_50Mhz => count_357Mhz[1].CLK
clock_in_50Mhz => count_357Mhz[2].CLK
clock_in_50Mhz => count_357Mhz[3].CLK
clock_in_50Mhz => clock_10Mhz_int.CLK
clock_in_50Mhz => count_10Mhz[0].CLK
clock_in_50Mhz => count_10Mhz[1].CLK
clock_in_50Mhz => count_10Mhz[2].CLK
clock_in_50Mhz => clock_1Hz~reg0.CLK
clock_in_50Mhz => clock_10Hz~reg0.CLK
clock_in_50Mhz => clock_100Hz~reg0.CLK
clock_in_50Mhz => clock_1KHz~reg0.CLK
clock_in_50Mhz => clock_10KHz~reg0.CLK
clock_in_50Mhz => clock_100KHz~reg0.CLK
clock_in_50Mhz => clock_1MHz~reg0.CLK
clock_in_50Mhz => clock_357Mhz~reg0.CLK
clock_in_50Mhz => clock_10MHz~reg0.CLK
clock_in_50Mhz => clock_25MHz~reg0.CLK
clock_in_50Mhz => clock_25Mhz_int.CLK
clock_25MHz <= clock_25MHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_10MHz <= clock_10MHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_357Mhz <= clock_357Mhz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_1MHz <= clock_1MHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_100KHz <= clock_100KHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_10KHz <= clock_10KHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_1KHz <= clock_1KHz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_100Hz <= clock_100Hz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_10Hz <= clock_10Hz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock_1Hz <= clock_1Hz~reg0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|decoder_7seg:DISPHEX0
NUMBER[0] => Mux0.IN19
NUMBER[0] => Mux1.IN19
NUMBER[0] => Mux2.IN19
NUMBER[0] => Mux3.IN19
NUMBER[0] => Mux4.IN19
NUMBER[0] => Mux5.IN19
NUMBER[0] => Mux6.IN19
NUMBER[1] => Mux0.IN18
NUMBER[1] => Mux1.IN18
NUMBER[1] => Mux2.IN18
NUMBER[1] => Mux3.IN18
NUMBER[1] => Mux4.IN18
NUMBER[1] => Mux5.IN18
NUMBER[1] => Mux6.IN18
NUMBER[2] => Mux0.IN17
NUMBER[2] => Mux1.IN17
NUMBER[2] => Mux2.IN17
NUMBER[2] => Mux3.IN17
NUMBER[2] => Mux4.IN17
NUMBER[2] => Mux5.IN17
NUMBER[2] => Mux6.IN17
NUMBER[3] => Mux0.IN16
NUMBER[3] => Mux1.IN16
NUMBER[3] => Mux2.IN16
NUMBER[3] => Mux3.IN16
NUMBER[3] => Mux4.IN16
NUMBER[3] => Mux5.IN16
NUMBER[3] => Mux6.IN16
HEX_DISP[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|decoder_7seg:DISPHEX1
NUMBER[0] => Mux0.IN19
NUMBER[0] => Mux1.IN19
NUMBER[0] => Mux2.IN19
NUMBER[0] => Mux3.IN19
NUMBER[0] => Mux4.IN19
NUMBER[0] => Mux5.IN19
NUMBER[0] => Mux6.IN19
NUMBER[1] => Mux0.IN18
NUMBER[1] => Mux1.IN18
NUMBER[1] => Mux2.IN18
NUMBER[1] => Mux3.IN18
NUMBER[1] => Mux4.IN18
NUMBER[1] => Mux5.IN18
NUMBER[1] => Mux6.IN18
NUMBER[2] => Mux0.IN17
NUMBER[2] => Mux1.IN17
NUMBER[2] => Mux2.IN17
NUMBER[2] => Mux3.IN17
NUMBER[2] => Mux4.IN17
NUMBER[2] => Mux5.IN17
NUMBER[2] => Mux6.IN17
NUMBER[3] => Mux0.IN16
NUMBER[3] => Mux1.IN16
NUMBER[3] => Mux2.IN16
NUMBER[3] => Mux3.IN16
NUMBER[3] => Mux4.IN16
NUMBER[3] => Mux5.IN16
NUMBER[3] => Mux6.IN16
HEX_DISP[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|decoder_7seg:DISPHEX2
NUMBER[0] => Mux0.IN19
NUMBER[0] => Mux1.IN19
NUMBER[0] => Mux2.IN19
NUMBER[0] => Mux3.IN19
NUMBER[0] => Mux4.IN19
NUMBER[0] => Mux5.IN19
NUMBER[0] => Mux6.IN19
NUMBER[1] => Mux0.IN18
NUMBER[1] => Mux1.IN18
NUMBER[1] => Mux2.IN18
NUMBER[1] => Mux3.IN18
NUMBER[1] => Mux4.IN18
NUMBER[1] => Mux5.IN18
NUMBER[1] => Mux6.IN18
NUMBER[2] => Mux0.IN17
NUMBER[2] => Mux1.IN17
NUMBER[2] => Mux2.IN17
NUMBER[2] => Mux3.IN17
NUMBER[2] => Mux4.IN17
NUMBER[2] => Mux5.IN17
NUMBER[2] => Mux6.IN17
NUMBER[3] => Mux0.IN16
NUMBER[3] => Mux1.IN16
NUMBER[3] => Mux2.IN16
NUMBER[3] => Mux3.IN16
NUMBER[3] => Mux4.IN16
NUMBER[3] => Mux5.IN16
NUMBER[3] => Mux6.IN16
HEX_DISP[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|decoder_7seg:DISPHEX3
NUMBER[0] => Mux0.IN19
NUMBER[0] => Mux1.IN19
NUMBER[0] => Mux2.IN19
NUMBER[0] => Mux3.IN19
NUMBER[0] => Mux4.IN19
NUMBER[0] => Mux5.IN19
NUMBER[0] => Mux6.IN19
NUMBER[1] => Mux0.IN18
NUMBER[1] => Mux1.IN18
NUMBER[1] => Mux2.IN18
NUMBER[1] => Mux3.IN18
NUMBER[1] => Mux4.IN18
NUMBER[1] => Mux5.IN18
NUMBER[1] => Mux6.IN18
NUMBER[2] => Mux0.IN17
NUMBER[2] => Mux1.IN17
NUMBER[2] => Mux2.IN17
NUMBER[2] => Mux3.IN17
NUMBER[2] => Mux4.IN17
NUMBER[2] => Mux5.IN17
NUMBER[2] => Mux6.IN17
NUMBER[3] => Mux0.IN16
NUMBER[3] => Mux1.IN16
NUMBER[3] => Mux2.IN16
NUMBER[3] => Mux3.IN16
NUMBER[3] => Mux4.IN16
NUMBER[3] => Mux5.IN16
NUMBER[3] => Mux6.IN16
HEX_DISP[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
HEX_DISP[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|ps2kbd:ps2_kbd_inst
clock => keyboard:kbd_inst.clock
clkdelay => caps[0].CLK
clkdelay => caps[1].CLK
reset => keyboard:kbd_inst.reset
read => keyboard:kbd_inst.read
scan_ready <= keyboard:kbd_inst.scan_ready
ps2_ascii_code[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
ps2_ascii_code[7] <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE


|z80soc|ps2kbd:ps2_kbd_inst|keyboard:kbd_inst
keyboard_clk => filter[7].DATAIN
keyboard_data => SHIFTIN.DATAB
keyboard_data => process_2.IN1
clock => keyboard_clk_filtered.CLK
clock => filter[0].CLK
clock => filter[1].CLK
clock => filter[2].CLK
clock => filter[3].CLK
clock => filter[4].CLK
clock => filter[5].CLK
clock => filter[6].CLK
clock => filter[7].CLK
clock => clock_enable.CLK
reset => INCNT.OUTPUTSELECT
reset => INCNT.OUTPUTSELECT
reset => INCNT.OUTPUTSELECT
reset => INCNT.OUTPUTSELECT
reset => READ_CHAR.OUTPUTSELECT
reset => ready_set.OUTPUTSELECT
reset => scan_code[0]~reg0.ENA
reset => scan_code[1]~reg0.ENA
reset => scan_code[2]~reg0.ENA
reset => scan_code[3]~reg0.ENA
reset => scan_code[4]~reg0.ENA
reset => scan_code[5]~reg0.ENA
reset => scan_code[6]~reg0.ENA
reset => scan_code[7]~reg0.ENA
reset => SHIFTIN[0].ENA
reset => SHIFTIN[1].ENA
reset => SHIFTIN[2].ENA
reset => SHIFTIN[3].ENA
reset => SHIFTIN[4].ENA
reset => SHIFTIN[5].ENA
reset => SHIFTIN[6].ENA
reset => SHIFTIN[7].ENA
reset => SHIFTIN[8].ENA
read => scan_ready~reg0.ACLR
scan_code[0] <= scan_code[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[1] <= scan_code[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[2] <= scan_code[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[3] <= scan_code[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[4] <= scan_code[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[5] <= scan_code[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[6] <= scan_code[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_code[7] <= scan_code[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_ready <= scan_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE