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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [z80soc.map.rpt] - Rev 46
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Analysis & Synthesis report for z80socSun Jun 19 14:41:59 2016Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Parallel Compilation5. Analysis & Synthesis Source Files Read6. Analysis & Synthesis Resource Usage Summary7. Analysis & Synthesis Resource Utilization by Entity8. Analysis & Synthesis RAM Summary9. Analysis & Synthesis IP Cores Summary10. Registers Removed During Synthesis11. Removed Registers Triggering Further Register Optimizations12. General Register Statistics13. Inverted Register Statistics14. Multiplexer Restructuring Statistics (Restructuring Performed)15. Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated16. Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram117. Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated18. Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram119. Source assignments for rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated20. Parameter Settings for User Entity Instance: T80se:z80_inst21. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u022. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_MCode:mcode23. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_ALU:alu24. Parameter Settings for User Entity Instance: vram:vram_inst|altsyncram:altsyncram_component25. Parameter Settings for User Entity Instance: charram:cram|altsyncram:altsyncram_component26. Parameter Settings for User Entity Instance: rom:rom_inst|altsyncram:altsyncram_component27. altsyncram Parameter Settings by Entity Instance28. Port Connectivity Checks: "clk_div:clkdiv_inst"29. Port Connectivity Checks: "video:video_inst|VGA_SYNC:vga_sync_inst"30. Port Connectivity Checks: "video:video_inst"31. Port Connectivity Checks: "T80se:z80_inst|T80:u0"32. Port Connectivity Checks: "T80se:z80_inst"33. Elapsed Time Per Partition34. Analysis & Synthesis Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2013 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+--------------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+------------------------------------+-------------------------------------------------+; Analysis & Synthesis Status ; Successful - Sun Jun 19 14:41:59 2016 ;; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;; Revision Name ; z80soc ;; Top-level Entity Name ; Z80SOC ;; Family ; Cyclone II ;; Total logic elements ; 2,705 ;; Total combinational functions ; 2,464 ;; Dedicated logic registers ; 535 ;; Total registers ; 535 ;; Total pins ; 281 ;; Total virtual pins ; 0 ;; Total memory bits ; 196,600 ;; Embedded Multiplier 9-bit elements ; 0 ;; Total PLLs ; 0 ;+------------------------------------+-------------------------------------------------++----------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+----------------------------------------------------------------------------+--------------------+--------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------+--------------------+; Device ; EP2C20F484C7 ; ;; Top-level entity name ; z80soc ; z80soc ;; Family name ; Cyclone II ; Cyclone IV GX ;; Use smart compilation ; On ; Off ;; Auto Shift Register Replacement ; Off ; Auto ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Restructure Multiplexers ; Auto ; Auto ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Disable OpenCore Plus hardware evaluation ; Off ; Off ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL_1993 ; VHDL_1993 ;; State Machine Processing ; Auto ; Auto ;; Safe State Machine ; Off ; Off ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Infer RAMs from Raw Logic ; On ; On ;; Parallel Synthesis ; On ; On ;; DSP Block Balancing ; Auto ; Auto ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Remove Duplicate Registers ; On ; On ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Optimization Technique ; Balanced ; Balanced ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;; Auto ROM Replacement ; On ; On ;; Auto RAM Replacement ; On ; On ;; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Allow Synchronous Control Signals ; On ; On ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto RAM to Logic Cell Conversion ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; Off ; Off ;; Report Parameter Settings ; On ; On ;; Report Source Assignments ; On ; On ;; Report Connectivity Checks ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 2 ; 2 ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Auto Gated Clock Conversion ; Off ; Off ;; Block Design Naming ; Auto ; Auto ;; SDC constraint protection ; Off ; Off ;; Synthesis Effort ; Auto ; Auto ;; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;; Pre-Mapping Resynthesis Optimization ; Off ; Off ;; Analysis & Synthesis Message Level ; Medium ; Medium ;; Disable Register Merging Across Hierarchies ; Auto ; Auto ;; Resource Aware Inference For Block RAM ; On ; On ;; Synthesis Seed ; 1 ; 1 ;+----------------------------------------------------------------------------+--------------------+--------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 2 ;; Maximum allowed ; 1 ;+----------------------------+--------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------+; memoryCores/vram.vhd ; yes ; User Wizard-Generated File ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/vram.vhd ; ;; memoryCores/charram.vhd ; yes ; User Wizard-Generated File ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/charram.vhd ; ;; memoryCores/rom.vhd ; yes ; User Wizard-Generated File ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/rom.vhd ; ;; vhdl/keyboard.VHD ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD ; ;; vhdl/ps2bkd.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/ps2bkd.vhd ; ;; vhdl/T80.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80.vhd ; ;; vhdl/T80_ALU.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_ALU.vhd ; ;; vhdl/T80_MCode.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_MCode.vhd ; ;; vhdl/T80_Pack.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_Pack.vhd ; ;; vhdl/T80_Reg.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_Reg.vhd ; ;; vhdl/T80se.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80se.vhd ; ;; vhdl/video.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/video.vhd ; ;; vhdl/clk_div.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd ; ;; vhdl/decoder_7seg.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/decoder_7seg.vhd ; ;; vhdl/z80soc.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd ; ;; vhdl/vga_sync.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/vga_sync.vhd ; ;; vhdl/z80soc_pack.vhd ; yes ; User VHDL File ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc_pack.vhd ; ;; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ;; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ;; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;; altrom.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ;; altram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ;; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ;; db/altsyncram_66l1.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_66l1.tdf ; ;; db/altsyncram_pal1.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_pal1.tdf ; ;; db/decode_1oa.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/decode_1oa.tdf ; ;; db/mux_hib.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/mux_hib.tdf ; ;; db/altsyncram_h1o1.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_h1o1.tdf ; ;; db/altsyncram_36o1.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_36o1.tdf ; ;; ../ROMdata/lat9-08.mif ; yes ; Auto-Found Memory Initialization File ; F:/z80soc-local/hw/0.7.3/ROMdata/lat9-08.mif ; ;; db/altsyncram_tr91.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_tr91.tdf ; ;; ../ROMdata/rom.hex ; yes ; Auto-Found Memory Initialization File ; F:/z80soc-local/hw/0.7.3/ROMdata/rom.hex ; ;; db/decode_4oa.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/decode_4oa.tdf ; ;; db/mux_kib.tdf ; yes ; Auto-Generated Megafunction ; F:/z80soc-local/hw/0.7.3/DE1/db/mux_kib.tdf ; ;+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------++-------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+---------------------------------------------+---------+; Resource ; Usage ;+---------------------------------------------+---------+; Estimated Total logic elements ; 2,705 ;; ; ;; Total combinational functions ; 2464 ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 1731 ;; -- 3 input functions ; 454 ;; -- <=2 input functions ; 279 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 2278 ;; -- arithmetic mode ; 186 ;; ; ;; Total registers ; 535 ;; -- Dedicated logic registers ; 535 ;; -- I/O registers ; 0 ;; ; ;; I/O pins ; 281 ;; Total memory bits ; 196600 ;; Embedded Multiplier 9-bit elements ; 0 ;; Maximum fan-out node ; Clk_Z80 ;; Maximum fan-out ; 409 ;; Total fan-out ; 11670 ;; Average fan-out ; 3.50 ;+---------------------------------------------+---------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+; |Z80SOC ; 2464 (110) ; 535 (65) ; 196600 ; 0 ; 0 ; 0 ; 281 ; 0 ; |Z80SOC ; work ;; |T80se:z80_inst| ; 2037 (10) ; 345 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|T80se:z80_inst ; work ;; |T80:u0| ; 2027 (838) ; 333 (205) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|T80se:z80_inst|T80:u0 ; work ;; |T80_ALU:alu| ; 458 (458) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu ; work ;; |T80_MCode:mcode| ; 475 (475) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|T80se:z80_inst|T80:u0|T80_MCode:mcode ; work ;; |T80_Reg:Regs| ; 256 (256) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs ; work ;; |charram:cram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|charram:cram ; work ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|charram:cram|altsyncram:altsyncram_component ; work ;; |altsyncram_h1o1:auto_generated| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated ; work ;; |altsyncram_36o1:altsyncram1| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1 ; work ;; |clk_div:clkdiv_inst| ; 33 (33) ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|clk_div:clkdiv_inst ; work ;; |decoder_7seg:DISPHEX0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|decoder_7seg:DISPHEX0 ; work ;; |decoder_7seg:DISPHEX1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|decoder_7seg:DISPHEX1 ; work ;; |decoder_7seg:DISPHEX2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|decoder_7seg:DISPHEX2 ; work ;; |decoder_7seg:DISPHEX3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|decoder_7seg:DISPHEX3 ; work ;; |ps2kbd:ps2_kbd_inst| ; 144 (128) ; 35 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|ps2kbd:ps2_kbd_inst ; work ;; |keyboard:kbd_inst| ; 16 (16) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|ps2kbd:ps2_kbd_inst|keyboard:kbd_inst ; work ;; |rom:rom_inst| ; 20 (0) ; 4 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|rom:rom_inst ; work ;; |altsyncram:altsyncram_component| ; 20 (0) ; 4 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component ; work ;; |altsyncram_tr91:auto_generated| ; 20 (0) ; 4 (4) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated ; work ;; |decode_4oa:deep_decode| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|decode_4oa:deep_decode ; work ;; |mux_kib:mux2| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|mux_kib:mux2 ; work ;; |video:video_inst| ; 80 (22) ; 49 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|video:video_inst ; work ;; |VGA_SYNC:vga_sync_inst| ; 58 (58) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|video:video_inst|VGA_SYNC:vga_sync_inst ; work ;; |vram:vram_inst| ; 12 (0) ; 1 (0) ; 49144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst ; work ;; |altsyncram:altsyncram_component| ; 12 (0) ; 1 (0) ; 49144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component ; work ;; |altsyncram_66l1:auto_generated| ; 12 (0) ; 1 (0) ; 49144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated ; work ;; |altsyncram_pal1:altsyncram1| ; 12 (0) ; 1 (1) ; 49144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1 ; work ;; |decode_1oa:decode4| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode4 ; work ;; |mux_hib:mux5| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux5 ; work ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis RAM Summary ;+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------+; charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; 16384 ; ../ROMdata/lat9-08.mif ;; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 16384 ; 8 ; -- ; -- ; 131072 ; ../ROMdata/rom.hex ;; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 6143 ; 8 ; 6143 ; 8 ; 49144 ; None ;+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis IP Cores Summary ;+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------+; Altera ; RAM: 2-PORT ; N/A ; N/A ; N/A ; |Z80SOC|charram:cram ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/charram.vhd ;; Altera ; ROM: 1-PORT ; N/A ; N/A ; N/A ; |Z80SOC|rom:rom_inst ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/rom.vhd ;; Altera ; RAM: 2-PORT ; N/A ; N/A ; N/A ; |Z80SOC|vram:vram_inst ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/vram.vhd ;+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------++----------------------------------------------------------------------------------------------------------+; Registers Removed During Synthesis ;+---------------------------------------------------------+------------------------------------------------+; Register name ; Reason for Removal ;+---------------------------------------------------------+------------------------------------------------+; video:video_inst|VGA_SYNC:vga_sync_inst|green_out[3] ; Stuck at GND due to stuck port data_in ;; video:video_inst|VGA_SYNC:vga_sync_inst|red_out[0..3] ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|OldNMI_n ; Lost fanout ;; T80se:z80_inst|T80:u0|BusReq_s ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|INT_s ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|BusAck ; Stuck at GND due to stuck port data_in ;; video:video_inst|VGA_SYNC:vga_sync_inst|green_out[0..2] ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|IntE_FF1 ; Lost fanout ;; T80se:z80_inst|T80:u0|NMI_s ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|IntCycle ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|IStatus[0,1] ; Lost fanout ;; T80se:z80_inst|T80:u0|NMICycle ; Stuck at GND due to stuck port data_in ;; T80se:z80_inst|T80:u0|Auto_Wait_t2 ; Lost fanout ;; T80se:z80_inst|T80:u0|Auto_Wait_t1 ; Lost fanout ;; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[9] ; Stuck at GND due to stuck port data_in ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|clock_enable ; Merged with clk_div:clkdiv_inst|count_10Mhz[0] ;; Total Number of Removed Registers = 22 ; ;+---------------------------------------------------------+------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------+; Removed Registers Triggering Further Register Optimizations ;+--------------------------------+---------------------------+--------------------------------------------------------------------+; Register name ; Reason for Removal ; Registers Removed due to This Register ;+--------------------------------+---------------------------+--------------------------------------------------------------------+; T80se:z80_inst|T80:u0|BusReq_s ; Stuck at GND ; T80se:z80_inst|T80:u0|BusAck, T80se:z80_inst|T80:u0|Auto_Wait_t2, ;; ; due to stuck port data_in ; T80se:z80_inst|T80:u0|Auto_Wait_t1 ;; T80se:z80_inst|T80:u0|IntCycle ; Stuck at GND ; T80se:z80_inst|T80:u0|IStatus[0], T80se:z80_inst|T80:u0|IStatus[1] ;; ; due to stuck port data_in ; ;; T80se:z80_inst|T80:u0|INT_s ; Stuck at GND ; T80se:z80_inst|T80:u0|IntE_FF1 ;; ; due to stuck port data_in ; ;+--------------------------------+---------------------------+--------------------------------------------------------------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 535 ;; Number of registers using Synchronous Clear ; 7 ;; Number of registers using Synchronous Load ; 25 ;; Number of registers using Asynchronous Clear ; 176 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 356 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++---------------------------------------------------+; Inverted Register Statistics ;+-----------------------------------------+---------+; Inverted Register ; Fan out ;+-----------------------------------------+---------+; T80se:z80_inst|WR_n ; 3 ;; T80se:z80_inst|MREQ_n ; 6 ;; T80se:z80_inst|RD_n ; 4 ;; T80se:z80_inst|IORQ_n ; 2 ;; T80se:z80_inst|T80:u0|MCycle[0] ; 92 ;; T80se:z80_inst|T80:u0|F[6] ; 11 ;; T80se:z80_inst|T80:u0|F[0] ; 14 ;; T80se:z80_inst|T80:u0|F[2] ; 8 ;; T80se:z80_inst|T80:u0|F[7] ; 7 ;; T80se:z80_inst|T80:u0|SP[0] ; 5 ;; T80se:z80_inst|T80:u0|SP[1] ; 5 ;; T80se:z80_inst|T80:u0|SP[2] ; 5 ;; T80se:z80_inst|T80:u0|SP[3] ; 5 ;; T80se:z80_inst|T80:u0|SP[4] ; 5 ;; T80se:z80_inst|T80:u0|SP[5] ; 5 ;; T80se:z80_inst|T80:u0|SP[6] ; 5 ;; T80se:z80_inst|T80:u0|SP[7] ; 5 ;; T80se:z80_inst|T80:u0|SP[8] ; 5 ;; T80se:z80_inst|T80:u0|ACC[0] ; 7 ;; T80se:z80_inst|T80:u0|SP[9] ; 5 ;; T80se:z80_inst|T80:u0|ACC[1] ; 7 ;; T80se:z80_inst|T80:u0|SP[10] ; 5 ;; T80se:z80_inst|T80:u0|ACC[2] ; 7 ;; T80se:z80_inst|T80:u0|SP[11] ; 5 ;; T80se:z80_inst|T80:u0|ACC[3] ; 9 ;; T80se:z80_inst|T80:u0|SP[12] ; 5 ;; T80se:z80_inst|T80:u0|ACC[4] ; 7 ;; T80se:z80_inst|T80:u0|SP[13] ; 5 ;; T80se:z80_inst|T80:u0|ACC[5] ; 9 ;; T80se:z80_inst|T80:u0|SP[14] ; 5 ;; T80se:z80_inst|T80:u0|ACC[6] ; 7 ;; T80se:z80_inst|T80:u0|SP[15] ; 5 ;; T80se:z80_inst|T80:u0|ACC[7] ; 7 ;; T80se:z80_inst|T80:u0|F[1] ; 20 ;; T80se:z80_inst|T80:u0|F[4] ; 8 ;; \random:rand_temp[15] ; 2 ;; T80se:z80_inst|T80:u0|Fp[6] ; 1 ;; T80se:z80_inst|T80:u0|Fp[0] ; 1 ;; T80se:z80_inst|T80:u0|Fp[2] ; 1 ;; T80se:z80_inst|T80:u0|Fp[7] ; 1 ;; T80se:z80_inst|T80:u0|Ap[0] ; 1 ;; T80se:z80_inst|T80:u0|Ap[1] ; 1 ;; T80se:z80_inst|T80:u0|Ap[2] ; 1 ;; T80se:z80_inst|T80:u0|Ap[3] ; 1 ;; T80se:z80_inst|T80:u0|Ap[4] ; 1 ;; T80se:z80_inst|T80:u0|Ap[5] ; 1 ;; T80se:z80_inst|T80:u0|Ap[6] ; 1 ;; T80se:z80_inst|T80:u0|Ap[7] ; 1 ;; T80se:z80_inst|T80:u0|F[5] ; 2 ;; T80se:z80_inst|T80:u0|Fp[1] ; 1 ;; T80se:z80_inst|T80:u0|Fp[4] ; 1 ;; T80se:z80_inst|T80:u0|F[3] ; 2 ;; T80se:z80_inst|T80:u0|Fp[5] ; 1 ;; T80se:z80_inst|T80:u0|Fp[3] ; 1 ;; Total number of inverted registers = 54 ; ;+-----------------------------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|ALU_Op_r[2] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|RegAddrC[1] ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|Read_To_Reg_r[2] ;; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |Z80SOC|video:video_inst|VGA_SYNC:vga_sync_inst|v_count[2] ;; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|XY_State[0] ;; 6:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|IR[7] ;; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|MCycle[2] ;; 5:1 ; 8 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |Z80SOC|ps2_ascii_reg1[1] ;; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |Z80SOC|ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ;; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|R[2] ;; 11:1 ; 8 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|BusB[7] ;; 12:1 ; 8 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|BusA[1] ;; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|ISet[0] ;; 6:1 ; 5 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[0] ;; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[3] ;; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[10] ;; 11:1 ; 7 bits ; 49 LEs ; 21 LEs ; 28 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|PC[1] ;; 11:1 ; 8 bits ; 56 LEs ; 32 LEs ; 24 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|PC[11] ;; 17:1 ; 8 bits ; 88 LEs ; 32 LEs ; 56 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|A[1] ;; 17:1 ; 8 bits ; 88 LEs ; 40 LEs ; 48 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|A[8] ;; 5:1 ; 8 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|DO[7] ;; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|SP[4] ;; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|SP[8] ;; 8:1 ; 8 bits ; 40 LEs ; 24 LEs ; 16 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|ACC[3] ;; 18:1 ; 2 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |Z80SOC|T80se:z80_inst|T80:u0|F[3] ;; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|Q_t ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_MCode:mcode|Mux47 ;; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|DAA_Q[2] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[1] ;; 8:1 ; 16 bits ; 80 LEs ; 80 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux43 ;; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|Mux14 ;; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|DAA_Q[7] ;; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|RegDIH[3] ;; 8:1 ; 16 bits ; 80 LEs ; 80 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux22 ;; 8:1 ; 16 bits ; 80 LEs ; 80 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux5 ;; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|RegAddrA[1] ;; 17:1 ; 4 bits ; 44 LEs ; 24 LEs ; 20 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[6] ;; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|RegWEH ;; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[7] ;; 20:1 ; 4 bits ; 52 LEs ; 48 LEs ; 4 LEs ; No ; |Z80SOC|DI_CPU[6] ;; 20:1 ; 4 bits ; 52 LEs ; 52 LEs ; 0 LEs ; No ; |Z80SOC|DI_CPU[3] ;+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------++------------------------------------------------------------------------------------------------------+; Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated ;+---------------------------------+--------------------+------+----------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+----------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+----------------------------------------++----------------------------------------------------------------------------------------------------------------------------------+; Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1 ;+---------------------------------+--------------------+------+--------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+--------------------------------------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+--------------------------------------------------------------------++----------------------------------------------------------------------------------------------------+; Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated ;+---------------------------------+--------------------+------+--------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+--------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+--------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1 ;+---------------------------------+--------------------+------+------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+------------------------------------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+------------------------------------------------------------------++----------------------------------------------------------------------------------------------------+; Source assignments for rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated ;+---------------------------------+--------------------+------+--------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+--------------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+--------------------------------------++-------------------------------------------------------------+; Parameter Settings for User Entity Instance: T80se:z80_inst ;+----------------+-------+------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------+; mode ; 0 ; Signed Integer ;; t2write ; 1 ; Signed Integer ;; iowait ; 1 ; Signed Integer ;+----------------+-------+------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------+; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0 ;+----------------+-------+-------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------+; mode ; 0 ; Signed Integer ;; iowait ; 1 ; Signed Integer ;; flag_c ; 0 ; Signed Integer ;; flag_n ; 1 ; Signed Integer ;; flag_p ; 2 ; Signed Integer ;; flag_x ; 3 ; Signed Integer ;; flag_h ; 4 ; Signed Integer ;; flag_y ; 5 ; Signed Integer ;; flag_z ; 6 ; Signed Integer ;; flag_s ; 7 ; Signed Integer ;+----------------+-------+-------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_MCode:mcode ;+----------------+-------+-----------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------+; mode ; 0 ; Signed Integer ;; flag_c ; 0 ; Signed Integer ;; flag_n ; 1 ; Signed Integer ;; flag_p ; 2 ; Signed Integer ;; flag_x ; 3 ; Signed Integer ;; flag_h ; 4 ; Signed Integer ;; flag_y ; 5 ; Signed Integer ;; flag_z ; 6 ; Signed Integer ;; flag_s ; 7 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_ALU:alu ;+----------------+-------+-------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------+; mode ; 0 ; Signed Integer ;; flag_c ; 0 ; Signed Integer ;; flag_n ; 1 ; Signed Integer ;; flag_p ; 2 ; Signed Integer ;; flag_x ; 3 ; Signed Integer ;; flag_h ; 4 ; Signed Integer ;; flag_y ; 5 ; Signed Integer ;; flag_z ; 6 ; Signed Integer ;; flag_s ; 7 ; Signed Integer ;+----------------+-------+-------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: vram:vram_inst|altsyncram:altsyncram_component ;+------------------------------------+----------------------+---------------------------------+; Parameter Name ; Value ; Type ;+------------------------------------+----------------------+---------------------------------+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH_BYTEENA ; 1 ; Untyped ;; OPERATION_MODE ; DUAL_PORT ; Untyped ;; WIDTH_A ; 8 ; Signed Integer ;; WIDTHAD_A ; 13 ; Signed Integer ;; NUMWORDS_A ; 6143 ; Signed Integer ;; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;; ADDRESS_ACLR_A ; NONE ; Untyped ;; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 8 ; Signed Integer ;; WIDTHAD_B ; 13 ; Signed Integer ;; NUMWORDS_B ; 6143 ; Signed Integer ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; AUTO ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;; INIT_FILE ; UNUSED ; Untyped ;; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;; ENABLE_ECC ; FALSE ; Untyped ;; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;; WIDTH_ECCSTATUS ; 3 ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CBXI_PARAMETER ; altsyncram_66l1 ; Untyped ;+------------------------------------+----------------------+---------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: charram:cram|altsyncram:altsyncram_component ;+------------------------------------+------------------------+-----------------------------+; Parameter Name ; Value ; Type ;+------------------------------------+------------------------+-----------------------------+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH_BYTEENA ; 1 ; Untyped ;; OPERATION_MODE ; DUAL_PORT ; Untyped ;; WIDTH_A ; 8 ; Signed Integer ;; WIDTHAD_A ; 11 ; Signed Integer ;; NUMWORDS_A ; 2048 ; Signed Integer ;; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;; ADDRESS_ACLR_A ; NONE ; Untyped ;; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 8 ; Signed Integer ;; WIDTHAD_B ; 11 ; Signed Integer ;; NUMWORDS_B ; 2048 ; Signed Integer ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; AUTO ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;; INIT_FILE ; ../ROMdata/lat9-08.mif ; Untyped ;; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ;; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;; ENABLE_ECC ; FALSE ; Untyped ;; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;; WIDTH_ECCSTATUS ; 3 ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CBXI_PARAMETER ; altsyncram_h1o1 ; Untyped ;+------------------------------------+------------------------+-----------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: rom:rom_inst|altsyncram:altsyncram_component ;+------------------------------------+----------------------+-------------------------------+; Parameter Name ; Value ; Type ;+------------------------------------+----------------------+-------------------------------+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH_BYTEENA ; 1 ; Untyped ;; OPERATION_MODE ; ROM ; Untyped ;; WIDTH_A ; 8 ; Signed Integer ;; WIDTHAD_A ; 14 ; Signed Integer ;; NUMWORDS_A ; 16384 ; Signed Integer ;; OUTDATA_REG_A ; CLOCK0 ; Untyped ;; ADDRESS_ACLR_A ; NONE ; Untyped ;; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 1 ; Untyped ;; WIDTHAD_B ; 1 ; Untyped ;; NUMWORDS_B ; 1 ; Untyped ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; AUTO ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;; INIT_FILE ; ../ROMdata/rom.hex ; Untyped ;; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;; ENABLE_ECC ; FALSE ; Untyped ;; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;; WIDTH_ECCSTATUS ; 3 ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CBXI_PARAMETER ; altsyncram_tr91 ; Untyped ;+------------------------------------+----------------------+-------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------+; altsyncram Parameter Settings by Entity Instance ;+-------------------------------------------+------------------------------------------------+; Name ; Value ;+-------------------------------------------+------------------------------------------------+; Number of entity instances ; 3 ;; Entity Instance ; vram:vram_inst|altsyncram:altsyncram_component ;; -- OPERATION_MODE ; DUAL_PORT ;; -- WIDTH_A ; 8 ;; -- NUMWORDS_A ; 6143 ;; -- OUTDATA_REG_A ; UNREGISTERED ;; -- WIDTH_B ; 8 ;; -- NUMWORDS_B ; 6143 ;; -- ADDRESS_REG_B ; CLOCK1 ;; -- OUTDATA_REG_B ; UNREGISTERED ;; -- RAM_BLOCK_TYPE ; AUTO ;; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;; Entity Instance ; charram:cram|altsyncram:altsyncram_component ;; -- OPERATION_MODE ; DUAL_PORT ;; -- WIDTH_A ; 8 ;; -- NUMWORDS_A ; 2048 ;; -- OUTDATA_REG_A ; UNREGISTERED ;; -- WIDTH_B ; 8 ;; -- NUMWORDS_B ; 2048 ;; -- ADDRESS_REG_B ; CLOCK1 ;; -- OUTDATA_REG_B ; UNREGISTERED ;; -- RAM_BLOCK_TYPE ; AUTO ;; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;; Entity Instance ; rom:rom_inst|altsyncram:altsyncram_component ;; -- OPERATION_MODE ; ROM ;; -- WIDTH_A ; 8 ;; -- NUMWORDS_A ; 16384 ;; -- OUTDATA_REG_A ; CLOCK0 ;; -- WIDTH_B ; 1 ;; -- NUMWORDS_B ; 1 ;; -- ADDRESS_REG_B ; CLOCK1 ;; -- OUTDATA_REG_B ; UNREGISTERED ;; -- RAM_BLOCK_TYPE ; AUTO ;; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;+-------------------------------------------+------------------------------------------------++------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "clk_div:clkdiv_inst" ;+--------------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------+--------+----------+-------------------------------------------------------------------------------------+; clock_1mhz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; clock_100khz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; clock_10khz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; clock_1khz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; clock_10hz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; clock_1hz ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+--------------+--------+----------+-------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "video:video_inst|VGA_SYNC:vga_sync_inst" ;+----------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------+--------+----------+-------------------------------------------------------------------------------------+; red ; Input ; Info ; Stuck at GND ;; green ; Input ; Info ; Stuck at GND ;; video_on ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+----------+--------+----------+-------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "video:video_inst" ;+---------------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------------+--------+----------+-------------------------------------------------------------------------------------+; vram_addr[13] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; vram_wren ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; cram_web ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+---------------+--------+----------+-------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "T80se:z80_inst|T80:u0" ;+------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------+--------+----------+-------------------------------------------------------------------------------------+; inte ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; stop ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------+--------+----------+-------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "T80se:z80_inst" ;+---------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------+; clken ; Input ; Info ; Stuck at VCC ;; wait_n ; Input ; Info ; Stuck at VCC ;; int_n ; Input ; Info ; Stuck at VCC ;; nmi_n ; Input ; Info ; Stuck at VCC ;; busrq_n ; Input ; Info ; Stuck at VCC ;; m1_n ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; rfsh_n ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; halt_n ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; busak_n ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------++-------------------------------+; Elapsed Time Per Partition ;+----------------+--------------+; Partition Name ; Elapsed Time ;+----------------+--------------+; Top ; 00:00:41 ;+----------------+--------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus II 64-Bit Analysis & SynthesisInfo: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web EditionInfo: Processing started: Sun Jun 19 14:40:54 2016Info: Command: quartus_map --read_settings_files=on --write_settings_files=off z80soc -c z80socWarning (20028): Parallel compilation is not licensed and has been disabledInfo (12021): Found 2 design units, including 1 entities, in source file memorycores/vram.vhdInfo (12022): Found design unit 1: vram-SYNInfo (12023): Found entity 1: vramInfo (12021): Found 2 design units, including 1 entities, in source file memorycores/charram.vhdInfo (12022): Found design unit 1: charram-SYNInfo (12023): Found entity 1: charramInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/lcd.vhdInfo (12022): Found design unit 1: LCD-RTLInfo (12023): Found entity 1: LCDInfo (12021): Found 2 design units, including 1 entities, in source file memorycores/rom.vhdInfo (12022): Found design unit 1: rom-SYNInfo (12023): Found entity 1: romInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/keyboard.vhdInfo (12022): Found design unit 1: keyboard-aInfo (12023): Found entity 1: keyboardInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/ps2bkd.vhdInfo (12022): Found design unit 1: ps2kbd-rtlInfo (12023): Found entity 1: ps2kbdInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/t80.vhdInfo (12022): Found design unit 1: T80-rtlInfo (12023): Found entity 1: T80Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_alu.vhdInfo (12022): Found design unit 1: T80_ALU-rtlInfo (12023): Found entity 1: T80_ALUInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_mcode.vhdInfo (12022): Found design unit 1: T80_MCode-rtlInfo (12023): Found entity 1: T80_MCodeInfo (12021): Found 1 design units, including 0 entities, in source file vhdl/t80_pack.vhdInfo (12022): Found design unit 1: T80_PackInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_reg.vhdInfo (12022): Found design unit 1: T80_Reg-rtlInfo (12023): Found entity 1: T80_RegInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/t80se.vhdInfo (12022): Found design unit 1: T80se-rtlInfo (12023): Found entity 1: T80seInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/char_rom.vhdInfo (12022): Found design unit 1: Char_ROM-aInfo (12023): Found entity 1: Char_ROMInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/video.vhdInfo (12022): Found design unit 1: video-AInfo (12023): Found entity 1: videoInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/clk_div.vhdInfo (12022): Found design unit 1: clk_div-aInfo (12023): Found entity 1: clk_divInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/decoder_7seg.vhdInfo (12022): Found design unit 1: decoder_7seg-rtlInfo (12023): Found entity 1: decoder_7segInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/z80soc.vhdInfo (12022): Found design unit 1: Z80SOC-rtlInfo (12023): Found entity 1: Z80SOCInfo (12021): Found 2 design units, including 1 entities, in source file vhdl/vga_sync.vhdInfo (12022): Found design unit 1: VGA_SYNC-aInfo (12023): Found entity 1: VGA_SYNCInfo (12021): Found 1 design units, including 0 entities, in source file vhdl/z80soc_pack.vhdInfo (12022): Found design unit 1: z80soc_packInfo (12127): Elaborating entity "z80soc" for the top level hierarchyWarning (10541): VHDL Signal Declaration warning at z80soc.vhd(140): used implicit default value for signal "SD_DAT3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10541): VHDL Signal Declaration warning at z80soc.vhd(141): used implicit default value for signal "SD_CMD" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10541): VHDL Signal Declaration warning at z80soc.vhd(142): used implicit default value for signal "SD_CLK" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(310): object "clk1mhz" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at z80soc.vhd(314): object "clk10hz" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at z80soc.vhd(315): object "clk1hz" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at z80soc.vhd(317): object "clk1khz" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at z80soc.vhd(336): object "vram_web" assigned a value but never readWarning (10036): Verilog HDL or VHDL warning at z80soc.vhd(347): object "cram_web" assigned a value but never readWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(362): used explicit default value for signal "Z80SOC_Arch_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(364): used explicit default value for signal "RAMTOP_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(365): used explicit default value for signal "RAMBOTT_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(366): used explicit default value for signal "VRAM_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(367): used explicit default value for signal "STACK_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(368): used explicit default value for signal "CHARRAM_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(369): used explicit default value for signal "VIDCOLS_reg" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at z80soc.vhd(370): used explicit default value for signal "VIDROWS_reg" because signal was never assigned a valueInfo (12128): Elaborating entity "T80se" for hierarchy "T80se:z80_inst"Info (12128): Elaborating entity "T80" for hierarchy "T80se:z80_inst|T80:u0"Info (12128): Elaborating entity "T80_MCode" for hierarchy "T80se:z80_inst|T80:u0|T80_MCode:mcode"Info (12128): Elaborating entity "T80_ALU" for hierarchy "T80se:z80_inst|T80:u0|T80_ALU:alu"Info (12128): Elaborating entity "T80_Reg" for hierarchy "T80se:z80_inst|T80:u0|T80_Reg:Regs"Info (12128): Elaborating entity "video" for hierarchy "video:video_inst"Warning (10036): Verilog HDL or VHDL warning at video.vhd(54): object "video_on_sig" assigned a value but never readInfo (12128): Elaborating entity "VGA_SYNC" for hierarchy "video:video_inst|VGA_SYNC:vga_sync_inst"Info (12128): Elaborating entity "vram" for hierarchy "vram:vram_inst"Info (12128): Elaborating entity "altsyncram" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component"Info (12130): Elaborated megafunction instantiation "vram:vram_inst|altsyncram:altsyncram_component"Info (12133): Instantiated megafunction "vram:vram_inst|altsyncram:altsyncram_component" with the following parameter:Info (12134): Parameter "address_reg_b" = "CLOCK1"Info (12134): Parameter "clock_enable_input_a" = "BYPASS"Info (12134): Parameter "clock_enable_input_b" = "BYPASS"Info (12134): Parameter "clock_enable_output_a" = "BYPASS"Info (12134): Parameter "clock_enable_output_b" = "BYPASS"Info (12134): Parameter "intended_device_family" = "Cyclone II"Info (12134): Parameter "lpm_type" = "altsyncram"Info (12134): Parameter "numwords_a" = "6143"Info (12134): Parameter "numwords_b" = "6143"Info (12134): Parameter "operation_mode" = "DUAL_PORT"Info (12134): Parameter "outdata_aclr_b" = "NONE"Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"Info (12134): Parameter "power_up_uninitialized" = "FALSE"Info (12134): Parameter "widthad_a" = "13"Info (12134): Parameter "widthad_b" = "13"Info (12134): Parameter "width_a" = "8"Info (12134): Parameter "width_b" = "8"Info (12134): Parameter "width_byteena_a" = "1"Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_66l1.tdfInfo (12023): Found entity 1: altsyncram_66l1Info (12128): Elaborating entity "altsyncram_66l1" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated"Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_pal1.tdfInfo (12023): Found entity 1: altsyncram_pal1Info (12128): Elaborating entity "altsyncram_pal1" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1"Warning (287013): Variable or input pin "clocken1" is defined but never used.Info (12021): Found 1 design units, including 1 entities, in source file db/decode_1oa.tdfInfo (12023): Found entity 1: decode_1oaInfo (12128): Elaborating entity "decode_1oa" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode3"Info (12128): Elaborating entity "decode_1oa" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode_a"Info (12021): Found 1 design units, including 1 entities, in source file db/mux_hib.tdfInfo (12023): Found entity 1: mux_hibInfo (12128): Elaborating entity "mux_hib" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux5"Info (12128): Elaborating entity "charram" for hierarchy "charram:cram"Info (12128): Elaborating entity "altsyncram" for hierarchy "charram:cram|altsyncram:altsyncram_component"Info (12130): Elaborated megafunction instantiation "charram:cram|altsyncram:altsyncram_component"Info (12133): Instantiated megafunction "charram:cram|altsyncram:altsyncram_component" with the following parameter:Info (12134): Parameter "address_reg_b" = "CLOCK1"Info (12134): Parameter "clock_enable_input_a" = "BYPASS"Info (12134): Parameter "clock_enable_input_b" = "BYPASS"Info (12134): Parameter "clock_enable_output_a" = "BYPASS"Info (12134): Parameter "clock_enable_output_b" = "BYPASS"Info (12134): Parameter "init_file" = "../ROMdata/lat9-08.mif"Info (12134): Parameter "intended_device_family" = "Cyclone II"Info (12134): Parameter "lpm_type" = "altsyncram"Info (12134): Parameter "numwords_a" = "2048"Info (12134): Parameter "numwords_b" = "2048"Info (12134): Parameter "operation_mode" = "DUAL_PORT"Info (12134): Parameter "outdata_aclr_b" = "NONE"Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"Info (12134): Parameter "power_up_uninitialized" = "FALSE"Info (12134): Parameter "widthad_a" = "11"Info (12134): Parameter "widthad_b" = "11"Info (12134): Parameter "width_a" = "8"Info (12134): Parameter "width_b" = "8"Info (12134): Parameter "width_byteena_a" = "1"Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h1o1.tdfInfo (12023): Found entity 1: altsyncram_h1o1Info (12128): Elaborating entity "altsyncram_h1o1" for hierarchy "charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated"Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_36o1.tdfInfo (12023): Found entity 1: altsyncram_36o1Info (12128): Elaborating entity "altsyncram_36o1" for hierarchy "charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1"Info (12128): Elaborating entity "rom" for hierarchy "rom:rom_inst"Info (12128): Elaborating entity "altsyncram" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component"Info (12130): Elaborated megafunction instantiation "rom:rom_inst|altsyncram:altsyncram_component"Info (12133): Instantiated megafunction "rom:rom_inst|altsyncram:altsyncram_component" with the following parameter:Info (12134): Parameter "address_aclr_a" = "NONE"Info (12134): Parameter "clock_enable_input_a" = "BYPASS"Info (12134): Parameter "clock_enable_output_a" = "BYPASS"Info (12134): Parameter "init_file" = "../ROMdata/rom.hex"Info (12134): Parameter "intended_device_family" = "Cyclone IV E"Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"Info (12134): Parameter "lpm_type" = "altsyncram"Info (12134): Parameter "numwords_a" = "16384"Info (12134): Parameter "operation_mode" = "ROM"Info (12134): Parameter "outdata_aclr_a" = "NONE"Info (12134): Parameter "outdata_reg_a" = "CLOCK0"Info (12134): Parameter "widthad_a" = "14"Info (12134): Parameter "width_a" = "8"Info (12134): Parameter "width_byteena_a" = "1"Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_tr91.tdfInfo (12023): Found entity 1: altsyncram_tr91Info (12128): Elaborating entity "altsyncram_tr91" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated"Warning (113007): Byte addressed memory initialization file "rom.hex" was read in the word-addressed formatWarning (113015): Width of data items in "rom.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 509 warnings, reporting 10Warning (113009): Data at line (1) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (2) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (3) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (4) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (5) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (6) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (7) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (8) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (9) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Warning (113009): Data at line (10) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (8364) in the Memory Initialization File "F:/z80soc-local/hw/0.7.3/ROMdata/rom.hex" -- setting initial value for remaining addresses to 0Info (12021): Found 1 design units, including 1 entities, in source file db/decode_4oa.tdfInfo (12023): Found entity 1: decode_4oaInfo (12128): Elaborating entity "decode_4oa" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|decode_4oa:deep_decode"Info (12021): Found 1 design units, including 1 entities, in source file db/mux_kib.tdfInfo (12023): Found entity 1: mux_kibInfo (12128): Elaborating entity "mux_kib" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|mux_kib:mux2"Info (12128): Elaborating entity "clk_div" for hierarchy "clk_div:clkdiv_inst"Info (12128): Elaborating entity "decoder_7seg" for hierarchy "decoder_7seg:DISPHEX0"Info (12128): Elaborating entity "ps2kbd" for hierarchy "ps2kbd:ps2_kbd_inst"Warning (10492): VHDL Process Statement warning at ps2bkd.vhd(58): signal "caps" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at ps2bkd.vhd(58): signal "scan_code_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity listInfo (12128): Elaborating entity "keyboard" for hierarchy "ps2kbd:ps2_kbd_inst|keyboard:kbd_inst"Warning (19016): Clock multiplexers are found and protectedWarning (19017): Found clock multiplexer Clk_Z80Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)Warning (13049): Converted tri-state buffer "DI_CPU[0]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[1]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[2]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[3]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[4]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[5]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[6]" feeding internal logic into a wireWarning (13049): Converted tri-state buffer "DI_CPU[7]" feeding internal logic into a wireWarning (12069): Ignored assignment(s) for "CLOCK_27[0]" because "CLOCK_27" is not a bus or arrayWarning (12069): Ignored assignment(s) for "CLOCK_27[1]" because "CLOCK_27" is not a bus or arrayWarning (13039): The following bidir pins have no driversWarning (13040): Bidir "PS2_DAT" has no driverWarning (13040): Bidir "PS2_CLK" has no driverWarning (13027): Removed fan-outs from the following always-disabled I/O buffersWarning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[8]" to the node "SRAM_DQ[8]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[9]" to the node "SRAM_DQ[9]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[10]" to the node "SRAM_DQ[10]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[11]" to the node "SRAM_DQ[11]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[12]" to the node "SRAM_DQ[12]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[13]" to the node "SRAM_DQ[13]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[14]" to the node "SRAM_DQ[14]"Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[15]" to the node "SRAM_DQ[15]"Info (13000): Registers with preset signals will power-up highInfo (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-BackWarning (13024): Output pins are stuck at VCC or GNDWarning (13410): Pin "DRAM_ADDR[0]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[1]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[2]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[3]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[4]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[5]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[6]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[7]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[8]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[9]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[10]" is stuck at GNDWarning (13410): Pin "DRAM_ADDR[11]" is stuck at GNDWarning (13410): Pin "DRAM_LDQM" is stuck at GNDWarning (13410): Pin "DRAM_UDQM" is stuck at GNDWarning (13410): Pin "DRAM_WE_N" is stuck at VCCWarning (13410): Pin "DRAM_CAS_N" is stuck at VCCWarning (13410): Pin "DRAM_RAS_N" is stuck at VCCWarning (13410): Pin "DRAM_CS_N" is stuck at VCCWarning (13410): Pin "DRAM_BA_0" is stuck at GNDWarning (13410): Pin "DRAM_BA_1" is stuck at GNDWarning (13410): Pin "DRAM_CLK" is stuck at GNDWarning (13410): Pin "DRAM_CKE" is stuck at GNDWarning (13410): Pin "FL_ADDR[0]" is stuck at GNDWarning (13410): Pin "FL_ADDR[1]" is stuck at GNDWarning (13410): Pin "FL_ADDR[2]" is stuck at GNDWarning (13410): Pin "FL_ADDR[3]" is stuck at GNDWarning (13410): Pin "FL_ADDR[4]" is stuck at GNDWarning (13410): Pin "FL_ADDR[5]" is stuck at GNDWarning (13410): Pin "FL_ADDR[6]" is stuck at GNDWarning (13410): Pin "FL_ADDR[7]" is stuck at GNDWarning (13410): Pin "FL_ADDR[8]" is stuck at GNDWarning (13410): Pin "FL_ADDR[9]" is stuck at GNDWarning (13410): Pin "FL_ADDR[10]" is stuck at GNDWarning (13410): Pin "FL_ADDR[11]" is stuck at GNDWarning (13410): Pin "FL_ADDR[12]" is stuck at GNDWarning (13410): Pin "FL_ADDR[13]" is stuck at GNDWarning (13410): Pin "FL_ADDR[14]" is stuck at GNDWarning (13410): Pin "FL_ADDR[15]" is stuck at GNDWarning (13410): Pin "FL_ADDR[16]" is stuck at GNDWarning (13410): Pin "FL_ADDR[17]" is stuck at GNDWarning (13410): Pin "FL_ADDR[18]" is stuck at GNDWarning (13410): Pin "FL_ADDR[19]" is stuck at GNDWarning (13410): Pin "FL_ADDR[20]" is stuck at GNDWarning (13410): Pin "FL_ADDR[21]" is stuck at GNDWarning (13410): Pin "FL_WE_N" is stuck at VCCWarning (13410): Pin "FL_RST_N" is stuck at GNDWarning (13410): Pin "FL_OE_N" is stuck at VCCWarning (13410): Pin "FL_CE_N" is stuck at VCCWarning (13410): Pin "SRAM_ADDR[16]" is stuck at GNDWarning (13410): Pin "SRAM_ADDR[17]" is stuck at GNDWarning (13410): Pin "SRAM_UB_N" is stuck at VCCWarning (13410): Pin "SRAM_LB_N" is stuck at GNDWarning (13410): Pin "SRAM_CE_N" is stuck at GNDWarning (13410): Pin "SD_DAT3" is stuck at GNDWarning (13410): Pin "SD_CMD" is stuck at GNDWarning (13410): Pin "SD_CLK" is stuck at GNDWarning (13410): Pin "TDO" is stuck at GNDWarning (13410): Pin "I2C_SCLK" is stuck at GNDWarning (13410): Pin "VGA_R[0]" is stuck at GNDWarning (13410): Pin "VGA_R[1]" is stuck at GNDWarning (13410): Pin "VGA_R[2]" is stuck at GNDWarning (13410): Pin "VGA_R[3]" is stuck at GNDWarning (13410): Pin "VGA_G[0]" is stuck at GNDWarning (13410): Pin "VGA_G[1]" is stuck at GNDWarning (13410): Pin "VGA_G[2]" is stuck at GNDWarning (13410): Pin "VGA_G[3]" is stuck at GNDWarning (13410): Pin "AUD_DACDAT" is stuck at GNDWarning (13410): Pin "AUD_XCK" is stuck at GNDInfo (17049): 6 registers lost all their fanouts during netlist optimizations.Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELLWarning (21074): Design contains 9 input pin(s) that do not drive logicWarning (15610): No output dependent on input pin "CLOCK_27"Warning (15610): No output dependent on input pin "EXT_CLOCK"Warning (15610): No output dependent on input pin "UART_RXD"Warning (15610): No output dependent on input pin "IRDA_RXD"Warning (15610): No output dependent on input pin "SD_DAT"Warning (15610): No output dependent on input pin "TDI"Warning (15610): No output dependent on input pin "TCK"Warning (15610): No output dependent on input pin "TCS"Warning (15610): No output dependent on input pin "AUD_ADCDAT"Info (21057): Implemented 3088 device resources after synthesis - the final resource count might be differentInfo (21058): Implemented 24 input pinsInfo (21059): Implemented 139 output pinsInfo (21060): Implemented 118 bidirectional pinsInfo (21061): Implemented 2751 logic cellsInfo (21064): Implemented 56 RAM segmentsInfo: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 139 warningsInfo: Peak virtual memory: 544 megabytesInfo: Processing ended: Sun Jun 19 14:41:59 2016Info: Elapsed time: 00:01:05Info: Total CPU time (on all processors): 00:00:45