Subversion Repositories zet86

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               uart_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               uart_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2S60F672C5ES
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name TOP_LEVEL_ENTITY uart_test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:20:04  AUGUST 27, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name VERILOG_FILE altpll0.v
set_global_assignment -name VERILOG_FILE uart_test.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_wb.v
set_global_assignment -name VERILOG_FILE ../verilog/timescale.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_debug_if.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_defines.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_receiver.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_regs.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_rfifo.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_sync_flops.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_tfifo.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_top.v
set_global_assignment -name VERILOG_FILE ../verilog/uart_transmitter.v
set_global_assignment -name VERILOG_FILE ../verilog/raminfr.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_location_assignment PIN_K8 -to stxo_
set_location_assignment PIN_AF15 -to clk_
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name DEVICE_MIGRATION_LIST "EP2S60F672C5ES,EP2S60F672C5"
set_location_assignment PIN_AD26 -to led_[7]
set_location_assignment PIN_AD25 -to led_[6]
set_location_assignment PIN_AC25 -to led_[5]
set_location_assignment PIN_AC24 -to led_[4]
set_location_assignment PIN_AB24 -to led_[3]
set_location_assignment PIN_AB23 -to led_[2]
set_location_assignment PIN_AB26 -to led_[1]
set_location_assignment PIN_AB25 -to led_[0]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"