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[/] [zet86/] [trunk/] [soc/] [but_int.v] - Rev 49
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module but_int ( input clk, input rst, input but_, output reg intr, input inta ); // Register declaration reg old_but; // Behaviour always @(posedge clk) if (rst) intr <= 1'b0; else intr <= intr ? !inta : (but_ && !old_but); always @(posedge clk) old_but <= but_; endmodule