Subversion Repositories zet86

# Bus clock nets
#NET "sys_clk_in"  TNM_NET = "sys_clk_in";
#NET "tft_clk"  TNM_NET = "tft_clk";
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;

NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;

NET led LOC = G5;

#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
#------------------------------------------------------------------------------

#NET tft_lcd_b<0> LOC = L26; # VGA_B2
#NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
#NET tft_lcd_b<1> LOC = C5;  # VGA_B3
#NET tft_lcd_b<2> LOC = C7;  # VGA_B4
#NET tft_lcd_b<3> LOC = B7;  # VGA_B5
#NET tft_lcd_b<4> LOC = G8;  # VGA_B6
#NET tft_lcd_b<5> LOC = F8;  # VGA_B7
#NET tft_lcd_b<*> SLEW = FAST;
#NET tft_lcd_b<*> DRIVE = 8;
NET tft_lcd_b[0] LOC = G8;  # VGA_B6
NET tft_lcd_b[1] LOC = F8;  # VGA_B7
#NET tft_lcd_b SLEW = FAST;
#NET tft_lcd_b DRIVE = 8;


NET tft_lcd_clk  LOC = AF8;
#NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
#NET tft_lcd_clk  SLEW = FAST;
#NET tft_lcd_clk  DRIVE = 8;

#NET tft_lcd_g<0> LOC = M20; # VGA_G2
#NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
#NET tft_lcd_g<1> LOC = E4;  # VGA_G3
#NET tft_lcd_g<2> LOC = D3;  # VGA_G4
#NET tft_lcd_g<3> LOC = H7;  # VGA_G5
#NET tft_lcd_g<4> LOC = H8;  # VGA_G6
#NET tft_lcd_g<5> LOC = C1;  # VGA_G7
#NET tft_lcd_g<*> SLEW = FAST;
#NET tft_lcd_g<*> DRIVE = 8;
NET tft_lcd_g[0] LOC = H8;  # VGA_G6
NET tft_lcd_g[1] LOC = C1;  # VGA_G7
#NET tft_lcd_g SLEW = FAST;
#NET tft_lcd_g DRIVE = 8;

NET tft_lcd_hsync LOC = C10;
#NET tft_lcd_hsync SLEW = FAST;
#NET tft_lcd_hsync DRIVE = 8;

#NET tft_lcd_r<0> LOC = N25; #VGA_R2
#NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
#NET tft_lcd_r<1> LOC = C2; #VGA_R3
#NET tft_lcd_r<2> LOC = G7; #VGA_R4
#NET tft_lcd_r<3> LOC = F7; #VGA_R5
#NET tft_lcd_r<4> LOC = E5; #VGA_R6
#NET tft_lcd_r<5> LOC = E6; #VGA_R7
#NET tft_lcd_r<*> SLEW = FAST;
#NET tft_lcd_r<*> DRIVE = 8;
NET tft_lcd_r[0] LOC = E5; #VGA_R6
NET tft_lcd_r[1] LOC = E6; #VGA_R7
#NET tft_lcd_r SLEW = FAST;
#NET tft_lcd_r DRIVE = 8;

NET tft_lcd_vsync LOC = A8;
#NET tft_lcd_vsync SLEW = FAST;
#NET tft_lcd_vsync DRIVE = 8;

#TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
#TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;