URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
[/] [zipcpu/] [trunk/] [bench/] [asm/] [wdt.S] - Rev 16
Go to most recent revision | Compare with Previous | Blame | View Log
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename: wdt.S
;
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose: Test to see whether or not the watchdog timer works. We'll
; start the watchdog, clear a register, then write as many times
; as we can to memory before the watchdog kicks in.
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; License: GPL, v3, as defined and found on www.gnu.org,
; http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Registers:
; R12 Peripheral base
; R11 Address of our one memory variable
;
start:
CLR R12 ; Get the address of our peripheral base
LDIHI $c000h,R12
MOV $1+PC,R11 ; Get a memory address for a variable
BRA $1
.DAT 0
LDI $-1,R0 ; Start the watchdog timer
STO R0,$1(R12)
LSR $1,R0
STO R0,$4(R12)
LSR $1,R0
STO R0,$5(R12)
LSR $1,R0
STO R0,$6(R12)
;
CLR R0
loop:
ADD $1,R0
LOD (R11),R1
CMP R0,R1
STO.LT R0,(R11)
TST R0
BLT $2
BRA $-7
HALT
Go to most recent revision | Compare with Previous | Blame | View Log