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[/] [zipcpu/] [trunk/] [bench/] [asm/] [wdt.S] - Rev 172
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Filename: wdt.S;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core;; Purpose: Test to see whether or not the watchdog timer works. We'll; start the watchdog, clear a register, then write as many times; as we can to memory before the watchdog kicks in.;; Creator: Dan Gisselquist, Ph.D.; Gisselquist Technology, LLC;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Copyright (C) 2015, Gisselquist Technology, LLC;; This program is free software (firmware): you can redistribute it and/or; modify it under the terms of the GNU General Public License as published; by the Free Software Foundation, either version 3 of the License, or (at; your option) any later version.;; This program is distributed in the hope that it will be useful, but WITHOUT; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License; for more details.;; License: GPL, v3, as defined and found on www.gnu.org,; http://www.gnu.org/licenses/gpl.html;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Registers:; R12 Peripheral base; R11 Address of our one memory variable;#include "sys.i"start:LDI 0xc0000000,R12 ; Get the address of our peripheral baseMOV $1(PC),R11 ; Get a memory address for a variableBRA skip_test_variabletest_variable:.DAT 0skip_test_variable:LDI $-1,R0 ; Start the watchdog timerSTO R0,sys.bus.wdt(R12)LSR $1,R0 ; R0 now = 0x7fffffffSTO R0,sys.bus.tma(R12)LSR $1,R0 ; R0 now = 0x3fffffffSTO R0,sys.bus.tmb(R12)LSR $1,R0STO R0,sys.bus.tmc(R12);CLR R0wdt_test_loop:ADD $1,R0LOD (R11),R1CMP R0,R1STO.LT R0,(R11)TST -1,R0BLT wdt_test_program_is_brokenBRA wdt_test_loopwdt_test_program_is_broken:HALT
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