URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
[/] [zipcpu/] [trunk/] [doc/] [src/] [spec.tex] - Rev 42
Go to most recent revision | Compare with Previous | Blame | View Log
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%% Filename: spec.tex
%%
%% Project: Zip CPU -- a small, lightweight, RISC CPU soft core
%%
%% Purpose: This LaTeX file contains all of the documentation/description
%% currently provided with this Zip CPU soft core. It supersedes
%% any information about the instruction set or CPUs found
%% elsewhere. It's not nearly as interesting, though, as the PDF
%% file it creates, so I'd recommend reading that before diving
%% into this file. You should be able to find the PDF file in
%% the SVN distribution together with this PDF file and a copy of
%% the GPL-3.0 license this file is distributed under. If not,
%% just type 'make' in the doc directory and it (should) build
%% without a problem.
%%
%%
%% Creator: Dan Gisselquist
%% Gisselquist Technology, LLC
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%% Copyright (C) 2015, Gisselquist Technology, LLC
%%
%% This program is free software (firmware): you can redistribute it and/or
%% modify it under the terms of the GNU General Public License as published
%% by the Free Software Foundation, either version 3 of the License, or (at
%% your option) any later version.
%%
%% This program is distributed in the hope that it will be useful, but WITHOUT
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
%% for more details.
%%
%% You should have received a copy of the GNU General Public License along
%% with this program. (It's in the $(ROOT)/doc directory, run make with no
%% target there if the PDF file isn't present.) If not, see
%% <http://www.gnu.org/licenses/> for a copy.
%%
%% License: GPL, v3, as defined and found on www.gnu.org,
%% http://www.gnu.org/licenses/gpl.html
%%
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\documentclass{gqtekspec}
\project{Zip CPU}
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.5}
\definecolor{webred}{rgb}{0.2,0,0}
\definecolor{webgreen}{rgb}{0,0.2,0}
\usepackage[dvips,ps2pdf,colorlinks=true,
anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,
pdfauthor={Dan Gisselquist},
pdfsubject={Zip CPU}]{hyperref}
\begin{document}
\pagestyle{gqtekspecplain}
\titlepage
\begin{license}
Copyright (C) \theyear\today, Gisselquist Technology, LLC
This project is free software (firmware): you can redistribute it and/or
modify it under the terms of the GNU General Public License as published
by the Free Software Foundation, either version 3 of the License, or (at
your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
copy.
\end{license}
\begin{revisionhistory}
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline
0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline
\end{revisionhistory}
% Revision History
% Table of Contents, named Contents
\tableofcontents
\listoffigures
\listoftables
\begin{preface}
Many people have asked me why I am building the Zip CPU. ARM processors are
good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both
have better toolsets than the Zip CPU will ever have. OpenRISC is also
available, RISC--V may be replacing it. Why build a new processor?
The easiest, most obvious answer is the simple one: Because I can.
There's more to it, though. There's a lot that I would like to do with a
processor, and I want to be able to do it in a vendor independent fashion.
First, I would like to be able to place this processor inside an FPGA. Without
paying royalties, ARM is out of the question. I would then like to be able to
generate Verilog code, both for the processor and the system it sits within,
that can run equivalently on both Xilinx and Altera chips, and that can be
easily ported from one manufacturer's chipsets to another. Even more, before
purchasing a chip or a board, I would like to know that my soft core works. I
would like to build a test bench to test components with, and Verilator is my
chosen test bench. This forces me to use all Verilog, and it prevents me from
using any proprietary cores. For this reason, Microblaze and Nios are out of
the question.
Why not OpenRISC? That's a hard question. The OpenRISC team has done some
wonderful work on an amazing processor, and I'll have to admit that I am
envious of what they've accomplished. I would like to port binutils to the
Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The
OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has
a lot of features of modern CPUs within it that ... well, let's just say it's
not the little guy on the block. The Zip CPU is lighter weight, costing only
about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic
peripherals.
My final reason is that I'm building the Zip CPU as a learning experience. The
Zip CPU has allowed me to learn a lot about how CPUs work on a very micro
level. For the first time, I am beginning to understand many of the Computer
Architecture lessons from years ago.
To summarize: Because I can, because it is open source, because it is light
weight, and as an exercise in learning.
\end{preface}
\chapter{Introduction}
\pagenumbering{arabic}
\setcounter{page}{1}
The original goal of the Zip CPU was to be a very simple CPU. You might
think of it as a poor man's alternative to the OpenRISC architecture.
For this reason, all instructions have been designed to be as simple as
possible, and are all designed to be executed in one instruction cycle per
instruction, barring pipeline stalls. Indeed, even the bus has been simplified
to a constant 32-bit width, with no option for more or less. This has
resulted in the choice to drop push and pop instructions, pre-increment and
post-decrement addressing modes, and more.
For those who like buzz words, the Zip CPU is:
\begin{itemize}
\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits,
instructions are 32-bits wide, etc.
\item A RISC CPU. There is no microcode for executing instructions. All
instructions are designed to be completed in one clock cycle.
\item A Load/Store architecture. (Only load and store instructions
can access memory.)
\item Wishbone compliant. All peripherals are accessed just like
memory across this bus.
\item A Von-Neumann architecture. (The instructions and data share a
common bus.)
\item A pipelined architecture, having stages for {\bf Prefetch},
{\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory}
unit, and {\bf Write-back}. See Fig.~\ref{fig:cpu}
\begin{figure}\begin{center}
\includegraphics[width=3.5in]{../gfx/cpu.eps}
\caption{Zip CPU internal pipeline architecture}\label{fig:cpu}
\end{center}\end{figure}
for a diagram of this structure.
\item Completely open source, licensed under the GPL.\footnote{Should you
need a copy of the Zip CPU licensed under other terms, please
contact me.}
\end{itemize}
Now, however, that I've worked on the Zip CPU for a while, it is not nearly
as simple as I originally hoped. Worse, I've had to adjust to create
capabilities that I was never expecting to need. These include:
\begin{itemize}
\item {\bf External Debug:} Once placed upon an FPGA, some external means is
still necessary to debug this CPU. That means that there needs to be
an external register that can control the CPU: reset it, halt it, step
it, and tell whether it is running or not. My chosen interface
includes a second register similar to this control register. This
second register allows the external controller or debugger to examine
registers internal to the CPU.
\item {\bf Internal Debug:} Being able to run a debugger from within
a user process requires an ability to step a user process from
within a debugger. It also requires a break instruction that can
be substituted for any other instruction, and substituted back.
The break is actually difficult: the break instruction cannot be
allowed to execute. That way, upon a break, the debugger should
be able to jump back into the user process to step the instruction
that would've been at the break point initially, and then to
replace the break after passing it.
Incidentally, this break messes with the prefetch cache and the
pipeline: if you change an instruction partially through the pipeline,
the whole pipeline needs to be cleansed. Likewise if you change
an instruction in memory, you need to make sure the cache is reloaded
with the new instruction.
\item {\bf Prefetch Cache:} My original implementation had a very
simple prefetch stage. Any time the PC changed the prefetch would go
and fetch the new instruction. While this was perhaps this simplest
approach, it cost roughly five clocks for every instruction. This
was deemed unacceptable, as I wanted a CPU that could execute
instructions in one cycle. I therefore have a prefetch cache that
issues pipelined wishbone accesses to memory and then pushes
instructions at the CPU. Sadly, this accounts for about 20\% of the
logic in the entire CPU, or 15\% of the logic in the entire system.
\item {\bf Operating System:} In order to support an operating system,
interrupts and so forth, the CPU needs to support supervisor and
user modes, as well as a means of switching between them. For example,
the user needs a means of executing a system call. This is the
purpose of the {\bf `trap'} instruction. This instruction needs to
place the CPU into supervisor mode (here equivalent to disabling
interrupts), as well as handing it a parameter such as identifying
which O/S function was called.
My initial approach to building a trap instruction was to create an external
peripheral which, when written to, would generate an interrupt and could
return the last value written to it. In practice, this approach didn't work
at all: the CPU executed two instructions while waiting for the
trap interrupt to take place. Since then, I've decided to keep the rest of
the CC register for that purpose so that a write to the CC register, with the
GIE bit cleared, could be used to execute a trap. This has other problems,
though, primarily in the limitation of the uses of the CC register. In
particular, the CC register is the best place to put CPU state information and
to ``announce'' special CPU features (floating point, etc). So the trap
instruction still switches to interrupt mode, but the CC register is not
nearly as useful for telling the supervisor mode processor what trap is being
executed.
Modern timesharing systems also depend upon a {\bf Timer} interrupt
to handle task swapping. For the Zip CPU, this interrupt is handled
external to the CPU as part of the CPU System, found in {\tt zipsystem.v}.
The timer module itself is found in {\tt ziptimer.v}.
\item {\bf Pipeline Stalls:} My original plan was to not support pipeline
stalls at all, but rather to require the compiler to properly schedule
all instructions so that stalls would never be necessary. After trying
to build such an architecture, I gave up, having learned some things:
For example, in order to facilitate interrupt handling and debug
stepping, the CPU needs to know what instructions have finished, and
which have not. In other words, it needs to know where it can restart
the pipeline from. Once restarted, it must act as though it had
never stopped. This killed my idea of delayed branching, since what
would be the appropriate program counter to restart at? The one the
CPU was going to branch to, or the ones in the delay slots? This
also makes the idea of compressed instruction codes difficult, since,
again, where do you restart on interrupt?
So I switched to a model of discrete execution: Once an instruction
enters into either the ALU or memory unit, the instruction is
guaranteed to complete. If the logic recognizes a branch or a
condition that would render the instruction entering into this stage
possibly inappropriate (i.e. a conditional branch preceding a store
instruction for example), then the pipeline stalls for one cycle
until the conditional branch completes. Then, if it generates a new
PC address, the stages preceding are all wiped clean.
The discrete execution model allows such things as sleeping: if the
CPU is put to ``sleep,'' the ALU and memory stages stall and back up
everything before them. Likewise, anything that has entered the ALU
or memory stage when the CPU is placed to sleep continues to completion.
To handle this logic, each pipeline stage has three control signals:
a valid signal, a stall signal, and a clock enable signal. In
general, a stage stalls if it's contents are valid and the next step
is stalled. This allows the pipeline to fill any time a later stage
stalls.
This approach is also different from other pipeline approaches. Instead
of keeping the entire pipeline filled, each stage is treated
independently. Therefore, individual stages may move forward as long
as the subsequent stage is available, regardless of whether the stage
behind it is filled.
\item {\bf Verilog Modules:} When examining how other processors worked
here on open cores, many of them had one separate module per pipeline
stage. While this appeared to me to be a fascinating and commendable
idea, my own implementation didn't work out quite so nicely.
As an example, the decode module produces a {\em lot} of
control wires and registers. Creating a module out of this, with
only the simplest of logic within it, seemed to be more a lesson
in passing wires around, rather than encapsulating logic.
Another example was the register writeback section. I would love
this section to be a module in its own right, and many have made them
such. However, other modules depend upon writeback results other
than just what's placed in the register (i.e., the control wires).
For these reasons, I didn't manage to fit this section into it's
own module.
The result is that the majority of the CPU code can be found in
the {\tt zipcpu.v} file.
\end{itemize}
With that introduction out of the way, let's move on to the instruction
set.
\chapter{CPU Architecture}\label{chap:arch}
The Zip CPU supports a set of two operand instructions, where the second operand
(always a register) is the result. The only exception is the store instruction,
where the first operand (always a register) is the source of the data to be
stored.
\section{Simplified Bus}
The bus architecture of the Zip CPU is that of a simplified WISHBONE bus.
It has been simplified in this fashion: all operations are 32--bit operations.
The bus is neither little endian nor big endian. For this reason, all words
are 32--bits. All instructions are also 32--bits wide. Everything has been
built around the 32--bit word.
\section{Register Set}
The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor
and a user set as shown in Fig.~\ref{fig:regset}.
\begin{figure}\begin{center}
\includegraphics[width=3.5in]{../gfx/regset.eps}
\caption{Zip CPU Register File}\label{fig:regset}
\end{center}\end{figure}
The supervisor set is used in interrupt mode when interrupts are disabled,
whereas the user set is used otherwise. Of this register set, the Program
Counter (PC) is register 15, whereas the status register (SR) or condition
code register
(CC) is register 14. By convention, the stack pointer will be register 13 and
noted as (SP)--although there is nothing special about this register other
than this convention.
The CPU can access both register sets via move instructions from the
supervisor state, whereas the user state can only access the user registers.
The status register is special, and bears further mention. As shown in
Fig.~\ref{tbl:cc-register},
\begin{table}\begin{center}
\begin{bitlist}
31\ldots 11 & R/W & Reserved for future uses\\\hline
10 & R & (Reserved for) Bus-Error Flag\\\hline
9 & R & Trap, or user interrupt, Flag. Cleared on return to userspace.\\\hline
8 & R & (Reserved for) Illegal Instruction Flag\\\hline
7 & R/W & Break--Enable\\\hline
6 & R/W & Step\\\hline
5 & R/W & Global Interrupt Enable (GIE)\\\hline
4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline
3 & R/W & Overflow\\\hline
2 & R/W & Negative. The sign bit was set as a result of the last ALU instruction.\\\hline
1 & R/W & Carry\\\hline
0 & R/W & Zero. The last ALU operation produced a zero.\\\hline
\end{bitlist}
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
\end{center}\end{table}
the lower 11~bits of the status register form
a set of CPU state and condition codes. Writes to other bits of this register
are preserved.
Of the condition codes, the bottom four bits are the current flags:
Zero (Z),
Carry (C),
Negative (N),
and Overflow (V).
The next bit is a clock enable (0 to enable) or sleep bit (1 to put
the CPU to sleep). Setting this bit will cause the CPU to
wait for an interrupt (if interrupts are enabled), or to
completely halt (if interrupts are disabled).
The sixth bit is a global interrupt enable bit (GIE). When this
sixth bit is a `1' interrupts will be enabled, else disabled. When
interrupts are disabled, the CPU will be in supervisor mode, otherwise
it is in user mode. Thus, to execute a context switch, one only
need enable or disable interrupts. (When an interrupt line goes
high, interrupts will automatically be disabled, as the CPU goes
and deals with its context switch.) Special logic has been added to
keep the user mode from setting the sleep register and clearing the
GIE register at the same time, with clearing the GIE register taking
precedence.
The seventh bit is a step bit. This bit can be
set from supervisor mode only. After setting this bit, should
the supervisor mode process switch to user mode, it would then
accomplish one instruction in user mode before returning to supervisor
mode. Then, upon return to supervisor mode, this bit will
be automatically cleared. This bit has no effect on the CPU while in
supervisor mode.
This functionality was added to enable a userspace debugger
functionality on a user process, working through supervisor mode
of course.
The eighth bit is a break enable bit. This controls whether a break
instruction in user mode will halt the processor for an external debugger
(break enabled), or whether the break instruction will simply send send the
CPU into interrupt mode. Encountering a break in supervisor mode will
halt the CPU independent of the break enable bit. This bit can only be set
within supervisor mode.
% Should break enable be a supervisor mode bit, while the break enable bit
% in user mode is a break has taken place bit?
%
This functionality was added to enable an external debugger to
set and manage breakpoints.
The ninth bit is reserved for an illegal instruction bit. When the CPU
tries to execute either a non-existant instruction, or an instruction from
an address that produces a bus error, the CPU will (once implemented) switch
to supervisor mode while setting this bit. The bit will automatically be
cleared upon any return to user mode.
The tenth bit is a trap bit. It is set whenever the user requests a soft
interrupt, and cleared on any return to userspace command. This allows the
supervisor, in supervisor mode, to determine whether it got to supervisor
mode from a trap or from an external interrupt or both.
These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.
\begin{table}
\begin{center}
\begin{tabular}{l|l}
Bit & Meaning \\\hline
9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline
8 & (Reserved for) Floating point enable \\\hline
7 & Halt on break, to support an external debugger \\\hline
6 & Step, single step the CPU in user mode\\\hline
5 & GIE, or Global Interrupt Enable \\\hline
4 & Sleep \\\hline
3 & V, or overflow bit.\\\hline
2 & N, or negative bit.\\\hline
1 & C, or carry bit.\\\hline
0 & Z, or zero bit. \\\hline
\end{tabular}
\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}
\end{center}\end{table}
\section{Conditional Instructions}
Most, although not quite all, instructions may be conditionally executed. From
the four condition code flags, eight conditions are defined. These are shown
in Tbl.~\ref{tbl:conditions}.
\begin{table}
\begin{center}
\begin{tabular}{l|l|l}
Code & Mneumonic & Condition \\\hline
3'h0 & None & Always execute the instruction \\
3'h1 & {\tt .Z} & Only execute when 'Z' is set \\
3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\
3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\
3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\
3'h5 & {\tt .LT} & Less than ('N' set) \\
3'h6 & {\tt .C} & Carry set\\
3'h7 & {\tt .V} & Overflow set\\
\end{tabular}
\caption{Conditions for conditional operand execution}\label{tbl:conditions}
\end{center}
\end{table}
There is no condition code for less than or equal, not C or not V. Sorry,
I ran out of space in 3--bits. Conditioning on a non--supported condition
is still possible, but it will take an extra instruction and a pipeline stall. (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
Conditionally executed ALU instructions will not further adjust the
condition codes.
\section{Operand B}
Many instruction forms have a 21-bit source ``Operand B'' associated with them.
This Operand B is either equal to a register plus a signed immediate offset,
or an immediate offset by itself. This value is encoded as shown in
Tbl.~\ref{tbl:opb}.
\begin{table}\begin{center}
\begin{tabular}{|l|l|l|}\hline
Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline
1'b0 & \multicolumn{2}{l|}{20--bit Signed Immediate value} \\\hline
1'b1 & 4-bit Register & 16--bit Signed immediate offset \\\hline
\end{tabular}
\caption{Bit allocation for Operand B}\label{tbl:opb}
\end{center}\end{table}
Sixteen and twenty bit immediate values don't make sense for all instructions.
For example, what is the point of a 20--bit immediate when executing a 16--bit
multiply? Likewise, why have a 16--bit immediate when adding to a logical
or arithmetic shift? In these cases, the extra bits are reserved for future
instruction possibilities.
\section{Address Modes}
The Zip CPU supports two addressing modes: register plus immediate, and
immediate address. Addresses are therefore encoded in the same fashion as
Operand B's, shown above.
A lot of long hard thought was put into whether to allow pre/post increment
and decrement addressing modes. Finding no way to use these operators without
taking two or more clocks per instruction,\footnote{The two clocks figure
comes from the design of the register set, allowing only one write per clock.
That write is either from the memory unit or the ALU, but never both.} these
addressing modes have been
removed from the realm of possibilities. This means that the Zip CPU has no
native way of executing push, pop, return, or jump to subroutine operations.
Each of these instructions can be emulated with a set of instructions from the
existing set.
\section{Move Operands}
The previous set of operands would be perfect and complete, save only that
the CPU needs access to non--supervisory registers while in supervisory mode.
Therefore, the MOV instruction is special and offers access to these registers
\ldots when in supervisory mode. To keep the compiler simple, the extra bits
are ignored in non-supervisory mode (as though they didn't exist), rather than
being mapped to new instructions or additional capabilities. The bits
indicating which register set each register lies within are the A-Usr and
B-Usr bits. When set to a one, these refer to a user mode register. When set
to a zero, these refer to a register in the current mode, whether user or
supervisor. Further, because a load immediate instruction exists, there is no
move capability between an immediate and a register: all moves come from either
a register or a register plus an offset.
This actually leads to a bit of a problem: since the MOV instruction encodes
which register set each register is coming from or moving to, how shall a
compiler or assembler know how to compile a MOV instruction without knowing
the mode of the CPU at the time? For this reason, the compiler will assume
all MOV registers are supervisor registers, and display them as normal.
Anything with the user bit set will be treated as a user register. The CPU
will quietly ignore the supervisor bits while in user mode, and anything
marked as a user register will always be valid.
\section{Multiply Operations}
The Zip CPU supports two Multiply operations, a 16x16 bit signed multiply
({\tt MPYS}) and a 16x16 bit unsigned multiply ({\tt MPYU}). In both
cases, the operand is a register plus a 16-bit immediate, subject to the
rule that the register cannot be the PC or CC registers. The PC register
field has been stolen to create a multiply by immediate instruction. The
CC register field is reserved.
\section{Floating Point}
The Zip CPU does not (yet) support floating point operations. However, the
instruction set reserves two possibilities for future floating point
operations.
The first floating point operation hole in the instruction set involves
setting a proposed (but non-existent) floating point bit in the CC register.
The next instruction
would then simply interpret its operands as floating point instructions.
Not all instructions, however, have floating point equivalents. Further, the
immediate fields do not apply in floating point mode, and must be set to
zero. Not all instructions make sense as floating point operations.
Therefore, only the CMP, SUB, ADD, and MPY instructions may be issued as
floating point instructions. Other instructions allow the examining of the
floating point bit in the CC register. In all cases, the floating point bit
is cleared one instruction after it is set.
The other possibility for floating point operations involves exploiting the
hole in the instruction set that the NOOP and BREAK instructions reside within.
These two instructions use 24--bits of address space, when only a single bit
is necessary. A simple adjustment to this space could create instructions
with 4--bit register addresses for each register, a 3--bit field for
conditional execution, and a 2--bit field for which operation.
In this fashion, such a floating point capability would only fill 13--bits of
the 24--bit field, still leaving lots of room for expansion.
In both cases, the Zip CPU would support 32--bit single precision floats
only, since other choices would complicate the pipeline.
The current architecture does not support a floating point not-implemented
interrupt. Any soft floating point emulation must be done deliberately.
\section{Native Instructions}
The instruction set for the Zip CPU is summarized in
Tbl.~\ref{tbl:zip-instructions}.
\begin{table}\begin{center}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline
\rowcolor[gray]{0.85}
Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}
& \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}
& Sets CC? \\\hline\hline
{\tt CMP(Sub)} & \multicolumn{4}{l|}{4'h0}
& \multicolumn{4}{l|}{D. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt TST(And)} & \multicolumn{4}{l|}{4'h1}
& \multicolumn{4}{l|}{D. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt MOV} & \multicolumn{4}{l|}{4'h2}
& \multicolumn{4}{l|}{D. Reg}
& \multicolumn{3}{l|}{Cond.}
& A-Usr
& \multicolumn{4}{l|}{B-Reg}
& B-Usr
& \multicolumn{15}{l|}{15'bit signed offset}
& \\\hline
{\tt LODI} & \multicolumn{4}{l|}{4'h3}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{24}{l|}{24'bit Signed Immediate}
& \\\hline
{\tt NOOP} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'he}
& \multicolumn{24}{l|}{24'h00}
& \\\hline
{\tt BREAK} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'he}
& \multicolumn{24}{l|}{24'h01}
& \\\hline
{\em Reserved} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'he}
& \multicolumn{24}{l|}{24'bits, but not 0 or 1.}
& \\\hline
{\tt LODIHI }& \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'hf}
& \multicolumn{3}{l|}{Cond.}
& 1'b1
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{16}{l|}{16-bit Immediate}
& \\\hline
{\tt LODILO} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'hf}
& \multicolumn{3}{l|}{Cond.}
& 1'b0
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{16}{l|}{16-bit Immediate}
& \\\hline
16-b {\tt MPYU} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& 1'b0 & \multicolumn{4}{l|}{Reg}
& \multicolumn{16}{l|}{16-bit Offset}
& Yes \\\hline
16-b {\tt MPYU}(I) & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& 1'b0 & \multicolumn{4}{l|}{4'hf}
& \multicolumn{16}{l|}{16-bit Offset}
& Yes \\\hline
16-b {\tt MPYS} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& 1'b1 & \multicolumn{4}{l|}{Reg}
& \multicolumn{16}{l|}{16-bit Offset}
& Yes \\\hline
16-b {\tt MPYS}(I) & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& 1'b1 & \multicolumn{4}{l|}{4'hf}
& \multicolumn{16}{l|}{16-bit Offset}
& Yes \\\hline
{\tt ROL} & \multicolumn{4}{l|}{4'h5}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}
& \\\hline
{\tt LOD} & \multicolumn{4}{l|}{4'h6}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B address}
& \\\hline
{\tt STO} & \multicolumn{4}{l|}{4'h7}
& \multicolumn{4}{l|}{D. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B address}
& \\\hline
{\tt SUB} & \multicolumn{4}{l|}{4'h8}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt AND} & \multicolumn{4}{l|}{4'h9}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt ADD} & \multicolumn{4}{l|}{4'ha}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt OR} & \multicolumn{4}{l|}{4'hb}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt XOR} & \multicolumn{4}{l|}{4'hc}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B}
& Yes \\\hline
{\tt LSL/ASL} & \multicolumn{4}{l|}{4'hd}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
& Yes \\\hline
{\tt ASR} & \multicolumn{4}{l|}{4'he}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
& Yes \\\hline
{\tt LSR} & \multicolumn{4}{l|}{4'hf}
& \multicolumn{4}{l|}{R. Reg}
& \multicolumn{3}{l|}{Cond.}
& \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
& Yes \\\hline
\end{tabular}
\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions}
\end{center}\end{table}
As you can see, there's lots of room for instruction set expansion. The
NOOP and BREAK instructions are the only instructions within one particular
24--bit hole. The rest of this space is reserved for future enhancements.
\section{Derived Instructions}
The Zip CPU supports many other common instructions, but not all of them
are single cycle instructions. The derived instruction tables,
Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3}
and~\ref{tbl:derived-4},
help to capture some of how these other instructions may be implemented on
the Zip CPU. Many of these instructions will have assembly equivalents,
such as the branch instructions, to facilitate working with the CPU.
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
Mapped & Actual & Notes \\\hline
{\tt ABS Rx}
& \parbox[t]{1.5in}{\tt TST -1,Rx\\NEG.LT Rx}
& Absolute value, depends upon derived NEG.\\\hline
\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
& \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
& Add with carry \\\hline
{\tt BRA.Cond +/-\$Addr}
& \hbox{\tt MOV.cond \$Addr+PC,PC}
& Branch or jump on condition. Works for 15--bit
signed address offsets.\\\hline
{\tt BRA.Cond +/-\$Addr}
& \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
& Branch/jump on condition. Works for
23 bit address offsets, but costs a register, an extra instruction,
and sets the flags. \\\hline
{\tt BNC PC+\$Addr}
& \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
& Example of a branch on an unsupported
condition, in this case a branch on not carry \\\hline
{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline
{\tt CLRF.NZ Rx }
& {\tt XOR.NZ Rx,Rx}
& Clear Rx, and flags, if the Z-bit is not set \\\hline
{\tt CLR Rx }
& {\tt LDI \$0,Rx}
& Clears Rx, leaves flags untouched. This instruction cannot be
conditional. \\\hline
{\tt EXCH.W Rx }
& {\tt ROL \$16,Rx}
& Exchanges the top and bottom 16'bit words of Rx \\\hline
{\tt HALT }
& {\tt Or \$SLEEP,CC}
& This only works when issued in interrupt/supervisor mode. In user
mode this is simply a wait until interrupt instruction. \\\hline
{\tt INT } & {\tt LDI \$0,CC} & \\\hline
{\tt IRET}
& {\tt OR \$GIE,CC}
& Also known as an RTU instruction (Return to Userspace) \\\hline
{\tt JMP R6+\$Addr}
& {\tt MOV \$Addr(R6),PC}
& \\\hline
{\tt JSR PC+\$Addr}
& \parbox[t]{1.5in}{\tt SUB \$1,SP \\\
MOV \$3+PC,R0 \\
STO R0,1(SP) \\
MOV \$Addr+PC,PC \\
ADD \$1,SP}
& Jump to Subroutine. Note the required cleanup instruction after
returning. This could easily be turned into a three instruction
operand, removing the preliminary stack instruction before and
the cleanup after, by adjusting how any stack frame was built for
this routine to include space at the top of the stack for the PC.
Note also that jumping to a subroutine costs a copy register, {\tt R0}
in this case.
\\\hline
{\tt JSR PC+\$Addr }
& \parbox[t]{1.5in}{\tt MOV \$3+PC,R12 \\ MOV \$addr+PC,PC}
&This is the high speed
version of a subroutine call, necessitating a register to hold the
last PC address. In its favor, this method doesn't suffer the
mandatory memory access of the other approach. \\\hline
{\tt LDI.l \$val,Rx }
& \parbox[t]{1.8in}{\tt LDIHI (\$val$>>$16)\&0x0ffff, Rx \\
LDILO (\$val\&0x0ffff),Rx}
& Sadly, there's not enough instruction
space to load a complete immediate value into any register.
Therefore, fully loading any register takes two cycles.
The LDIHI (load immediate high) and LDILO (load immediate low)
instructions have been created to facilitate this. \\\hline
\end{tabular}
\caption{Derived Instructions}\label{tbl:derived-1}
\end{center}\end{table}
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
Mapped & Actual & Notes \\\hline
{\tt LOD.b \$addr,Rx}
& \parbox[t]{1.5in}{\tt %
LDI \$addr,Ra \\
LDI \$addr,Rb \\
LSR \$2,Ra \\
AND \$3,Rb \\
LOD (Ra),Rx \\
LSL \$3,Rb \\
SUB \$32,Rb \\
ROL Rb,Rx \\
AND \$0ffh,Rx}
& \parbox[t]{3in}{This CPU is designed for 32'bit word
length instructions. Byte addressing is not supported by the CPU or
the bus, so it therefore takes more work to do.
Note also that in this example, \$Addr is a byte-wise address, where
all other addresses in this document are 32-bit wordlength addresses.
For this reason,
we needed to drop the bottom two bits. This also limits the address
space of character accesses using this method from 16 MB down to 4MB.}
\\\hline
\parbox[t]{1.5in}{\tt LSL \$1,Rx\\ LSLC \$1,Ry}
& \parbox[t]{1.5in}{\tt LSL \$1,Ry \\
LSL \$1,Rx \\
OR.C \$1,Ry}
& Logical shift left with carry. Note that the
instruction order is now backwards, to keep the conditions valid.
That is, LSL sets the carry flag, so if we did this the other way
with Rx before Ry, then the condition flag wouldn't have been right
for an OR correction at the end. \\\hline
\parbox[t]{1.5in}{\tt LSR \$1,Rx \\ LSRC \$1,Ry}
& \parbox[t]{1.5in}{\tt CLR Rz \\
LSR \$1,Ry \\
LDIHI.C \$8000h,Rz \\
LSR \$1,Rx \\
OR Rz,Rx}
& Logical shift right with carry \\\hline
{\tt NEG Rx} & \parbox[t]{1.5in}{\tt XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline
{\tt NEG.C Rx} & \parbox[t]{1.5in}{\tt MOV.C \$-1+Rx,Rx\\XOR.C \$-1,Rx} & \\\hline
{\tt NOOP} & {\tt NOOP} & While there are many
operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these
operations have consequences in that they might stall the bus if
Rx isn't ready yet. For this reason, we have a dedicated NOOP
instruction. \\\hline
{\tt NOT Rx } & {\tt XOR \$-1,Rx } & \\\hline
{\tt POP Rx }
& \parbox[t]{1.5in}{\tt LOD \$1(SP),Rx \\ ADD \$1,SP}
& Note
that for interrupt purposes, one can never depend upon the value at
(SP). Hence you read from it, then increment it, lest having
incremented it first something then comes along and writes to that
value before you can read the result. \\\hline
\end{tabular}
\caption{Derived Instructions, continued}\label{tbl:derived-2}
\end{center}\end{table}
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
{\tt PUSH Rx}
& \parbox[t]{1.5in}{SUB \$1,SP \\
STO Rx,\$1(SP)}
& Note that for pipelined operation, it helps to coalesce all the
{\tt SUB}'s into one command, and place the {\tt STO}'s right
after each other.\\\hline
{\tt PUSH Rx-Ry}
& \parbox[t]{1.5in}{\tt SUB \$n,SP \\
STO Rx,\$n(SP)
\ldots \\
STO Ry,\$1(SP)}
& Multiple pushes at once only need the single subtract from the
stack pointer. This derived instruction is analogous to a similar one
on the Motoroloa 68k architecture, although the Zip Assembler
does not support this instruction (yet). This instruction
also supports pipelined memory access.\\\hline
{\tt RESET}
& \parbox[t]{1in}{\tt STO \$1,\$watchdog(R12)\\NOOP\\NOOP}
& This depends upon the peripheral base address being
in R12.
Another opportunity might be to jump to the reset address from within
supervisor mode.\\\hline
{\tt RET} & \parbox[t]{1.5in}{\tt LOD \$1(SP),PC}
& Note that this depends upon the calling context to clean up the
stack, as outlined for the JSR instruction. \\\hline
{\tt RET} & {\tt MOV R12,PC}
& This is the high(er) speed version, that doesn't touch the stack.
As such, it doesn't suffer a stall on memory read/write to the stack.
\\\hline
{\tt STEP Rr,Rt}
& \parbox[t]{1.5in}{\tt LSR \$1,Rr \\ XOR.C Rt,Rr}
& Step a Galois implementation of a Linear Feedback Shift Register, Rr,
using taps Rt \\\hline
{\tt STO.b Rx,\$addr}
& \parbox[t]{1.5in}{\tt %
LDI \$addr,Ra \\
LDI \$addr,Rb \\
LSR \$2,Ra \\
AND \$3,Rb \\
SUB \$32,Rb \\
LOD (Ra),Ry \\
AND \$0ffh,Rx \\
AND \~\$0ffh,Ry \\
ROL Rb,Rx \\
OR Rx,Ry \\
STO Ry,(Ra) }
& \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized
for byte-wise operations.
Note that in this example, \$addr is a
byte-wise address, whereas in all of our other examples it is a
32-bit word address. This also limits the address space
of character accesses from 16 MB down to 4MB.F
Further, this instruction implies a byte ordering,
such as big or little endian.} \\\hline
{\tt SWAP Rx,Ry }
& \parbox[t]{1.5in}{\tt
XOR Ry,Rx \\
XOR Rx,Ry \\
XOR Ry,Rx}
& While no extra registers are needed, this example
does take 3-clocks. \\\hline
{\tt TRAP \#X}
& \parbox[t]{1.5in}{\tt LDI \$x,R0 \\ AND \~\$GIE,CC }
& This works because whenever a user lowers the \$GIE flag, it sets
a TRAP bit within the CC register. Therefore, upon entering the
supervisor state, the CPU only need check this bit to know that it
got there via a TRAP. The trap could be made conditional by making
the LDI and the AND conditional. In that case, the assembler would
quietly turn the LDI instruction into an LDILO and LDIHI pair,
but the effect would be the same. \\\hline
\end{tabular}
\caption{Derived Instructions, continued}\label{tbl:derived-3}
\end{center}\end{table}
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
{\tt TST Rx}
& {\tt TST \$-1,Rx}
& Set the condition codes based upon Rx. Could also do a CMP \$0,Rx,
ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc. The TST and CMP
approaches won't stall future pipeline stages looking for the value
of Rx. \\\hline
{\tt WAIT}
& {\tt Or \$GIE | \$SLEEP,CC}
& Wait until the next interrupt, then jump to supervisor/interrupt
mode.
\end{tabular}
\caption{Derived Instructions, continued}\label{tbl:derived-4}
\end{center}\end{table}
\section{Pipeline Stages}
As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},
the Zip CPU supports a five stage pipeline.
\begin{enumerate}
\item {\bf Prefetch}: Reads instruction from memory and into a cache, if so
configured. This
stage is actually pipelined itself, and so it will stall if the PC
ever changes. Stalls are also created here if the instruction isn't
in the prefetch cache.
The Zip CPU supports one of two prefetch methods, depending upon a flag
set at build time within the {\tt zipcpu.v} file. The simplest is a
non--cached implementation of a prefetch. This implementation is
fairly small, and ideal for
users of the Zip CPU who need the extra space on the FPGA fabric.
However, because this non--cached version has no cache, the maximum
number of instructions per clock is limited to about one per five.
The second prefetch module is a pipelined prefetch with a cache. This
module tries to keep the instruction address within a window of valid
instruction addresses. While effective, it is not a traditional
cache implementation. One unique feature of this cache implementation,
however, is that it can be cleared in a single clock. A disappointing
feature, though, was that it needs an extra internal pipeline stage
to be implemented.
\item {\bf Decode}: Decodes an instruction into op code, register(s) to read,
and immediate offset. This stage also determines whether the flags will
be set or whether the result will be written back.
\item {\bf Read Operands}: Read registers and apply any immediate values to
them. There is no means of detecting or flagging arithmetic overflow
or carry when adding the immediate to the operand. This stage will
stall if any source operand is pending.
\item Split into two tracks: An {\bf ALU} which will accomplish a simple
instruction, and the {\bf MemOps} stage which handles {\tt LOD} (load)
and {\tt STO} (store) instructions.
\begin{itemize}
\item Loads will stall the entire pipeline until complete.
\item Condition codes are available upon completion of the ALU stage
\item Issuing an instruction to the memory unit while the memory unit
is busy will stall the entire pipeline. If the bus deadlocks,
only a reset will release the CPU. (Watchdog timer, anyone?)
\item The Zip CPU currently has no means of reading and acting on any
error conditions on the bus.
\end{itemize}
\item {\bf Write-Back}: Conditionally write back the result to the register
set, applying the condition. This routine is bi-entrant: either the
memory or the simple instruction may request a register write.
\end{enumerate}
The Zip CPU does not support out of order execution. Therefore, if the memory
unit stalls, every other instruction stalls. Memory stores, however, can take
place concurrently with ALU operations, although memory reads (loads) cannot.
\section{Pipeline Stalls}
The processing pipeline can and will stall for a variety of reasons. Some of
these are obvious, some less so. These reasons are listed below:
\begin{itemize}
\item When the prefetch cache is exhausted
This reason should be obvious. If the prefetch cache doesn't have the
instruction in memory, the entire pipeline must stall until enough of the
prefetch cache is loaded to support the next instruction.
\item While waiting for the pipeline to load following any taken branch, jump,
return from interrupt or switch to interrupt context (5 stall cycles)
If the PC suddenly changes, the pipeline is subsequently cleared and needs to
be reloaded. Given that there are five stages to the pipeline, that accounts
for four of the five stalls. The stall cycle is lost in the pipelined prefetch
stage which needs at least one clock with a valid PC before it can produce
a new output.
The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
{\tt LDI \$X,PC} instructions specially, however. These instructions, when
not conditioned on the flags, can execute with only 3~stall cycles.
\item When reading from a prior register while also adding an immediate offset
\begin{enumerate}
\item\ {\tt OPCODE ?,RA}
\item\ {\em (stall)}
\item\ {\tt OPCODE I+RA,RB}
\end{enumerate}
Since the addition of the immediate register within OpB decoding gets applied
during the read operand stage so that it can be nicely settled before the ALU,
any instruction that will write back an operand must be separated from the
opcode that will read and apply an immediate offset by one instruction. The
good news is that this stall can easily be mitigated by proper scheduling.
That is, any instruction that does not add an immediate to {\tt RA} may be
scheduled into the stall slot.
\item When any write to either the CC or PC Register is followed by a memory
operation
\begin{enumerate}
\item\ {\tt OPCODE RA,PC} {\em Ex: a branch opcode}
\item\ {\em (stall, even if jump not taken)}
\item\ {\tt LOD \$X(RA),RB}
\end{enumerate}
Since branches take place in the writeback stage, the Zip CPU will stall the
pipeline for one clock anytime there may be a possible jump. This prevents
an instruction from executing a memory access after the jump but before the
jump is recognized.
This stall may be mitigated by shuffling the operations immediately following
a potential branch so that an ALU operation follows the branch instead of a
memory operation.
\item When reading from the CC register after setting the flags
\begin{enumerate}
\item\ {\tt ALUOP RA,RB} {\em Ex: a compare opcode}
\item\ {\em (stall)}
\item\ {\tt TST sys.ccv,CC}
\item\ {\tt BZ somewhere}
\end{enumerate}
The reason for this stall is simply performance. Many of the flags are
determined via combinatorial logic after the writeback instruction is
determined. Trying to then place these into the input for one of the operands
created a time delay loop that would no longer execute in a single 100~MHz
clock cycle. (The time delay of the multiply within the ALU wasn't helping
either \ldots).
This stall may be eliminated via proper scheduling, by placing an instruction
that does not set flags in between the ALU operation and the instruction
that references the CC register. For example, {\tt MOV \$addr+PC,uPC}
followed by an {\tt RTU} ({\tt OR \$GIE,CC}) instruction will not incur
this stall, whereas an {\tt OR \$BREAKEN,CC} followed by an {\tt OR \$STEP,CC}
will incur the stall, while a {\tt LDI \$BREAKEN|\$STEP,CC} will not.
\item When waiting for a memory read operation to complete
\begin{enumerate}
\item\ {\tt LOD address,RA}
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\item\ {\tt OPCODE I+RA,RB}
\end{enumerate}
Remember, the Zip CPU does not support out of order execution. Therefore,
anytime the memory unit becomes busy both the memory unit and the ALU must
stall until the memory unit is cleared. This is especially true of a load
instruction, which must still write its operand back to the register file.
Store instructions are different, since they can be busy with no impact on
later ALU write back operations. Hence, only loads stall the pipeline.
This also assumes that the memory being accessed is a single cycle memory.
Slower memories, such as the Quad SPI flash, will take longer--perhaps even
as long as forty clocks. During this time the CPU and the external bus
will be busy, and unable to do anything else.
\item Memory operation followed by a memory operation
\begin{enumerate}
\item\ {\tt STO address,RA}
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\item\ {\tt LOD address,RB}
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\end{enumerate}
In this case, the LOD instruction cannot start until the STO is finished.
With proper scheduling, it is possible to do something in the ALU while the
memory unit is busy with the STO instruction, but otherwise this pipeline will
stall waiting for it to complete.
The Zip CPU does have the capability of supporting pipelined memory access,
but only under the following conditions: all accesses within the pipeline
must all be reads or all be writes, all must use the same register for their
address, and there can be no stalls or other instructions between pipelined
memory access instructions. Further, the offset to memory must be increasing
by one address each instruction. These conditions work well for saving or
storing registers to the stack.
\item When waiting for a conditional memory read operation to complete
\begin{enumerate}
\item\ {\tt LOD.Z address,RA}
\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
\item\ {\tt OPCODE I+RA,RB}
\end{enumerate}
In this case, the Zip CPU doesn't warn the prefetch cache to get off the bus
two cycles before using the bus, so there's a potential for an extra three
cycle cost due to bus contention between the prefetch and the CPU.
This is true for both the LOD and the STO instructions, with the exception that
the STO instruction will continue in parallel with any ALU instructions that
follow it.
\end{itemize}
\chapter{Peripherals}\label{chap:periph}
While the previous chapter describes a CPU in isolation, the Zip System
includes a minimum set of peripherals as well. These peripherals are shown
in Fig.~\ref{fig:zipsystem}
\begin{figure}\begin{center}
\includegraphics[width=3.5in]{../gfx/system.eps}
\caption{Zip System Peripherals}\label{fig:zipsystem}
\end{center}\end{figure}
and described here. They are designed to make
the Zip CPU more useful in an Embedded Operating System environment.
\section{Interrupt Controller}
Perhaps the most important peripheral within the Zip System is the interrupt
controller. While the Zip CPU itself can only handle one interrupt, and has
only the one interrupt state: disabled or enabled, the interrupt controller
can make things more interesting.
The Zip System interrupt controller module supports up to 15 interrupts, all
controlled from one register. Bit~31 of the interrupt controller controls
overall whether interrupts are enabled (1'b1) or disabled (1'b0). Bits~16--30
control whether individual interrupts are enabled (1'b0) or disabled (1'b0).
Bit~15 is an indicator showing whether or not any interrupt is active, and
bits~0--15 indicate whether or not an individual interrupt is active.
The interrupt controller has been designed so that bits can be controlled
individually without having any knowledge of the rest of the controller
setting. To enable an interrupt, write to the register with the high order
global enable bit set and the respective interrupt enable bit set. No other
bits will be affected. To disable an interrupt, write to the register with
the high order global enable bit cleared and the respective interrupt enable
bit set. To clear an interrupt, write a `1' to that interrupts status pin.
Zero's written to the register have no affect, save that a zero written to the
master enable will disable all interrupts.
As an example, suppose you wished to enable interrupt \#4. You would then
write to the register a {\tt 0x80100010} to enable interrupt \#4 and to clear
any past active state. When you later wish to disable this interrupt, you would
write a {\tt 0x00100010} to the register. As before, this both disables the
interrupt and clears the active indicator. This also has the side effect of
disabling all interrupts, so a second write of {\tt 0x80000000} may be necessary
to re-enable any other interrupts.
The Zip System currently hosts two interrupt controllers, a primary and a
secondary. The primary interrupt controller has one interrupt line which may
come from an external interrupt controller, and one interrupt line from the
secondary controller. Other primary interrupts include the system timers,
the jiffies interrupt, and the manual cache interrupt. The secondary interrupt
controller maintains an interrupt state for all of the processor accounting
counters.
\section{Counter}
The Zip Counter is a very simple counter: it just counts. It cannot be
halted. When it rolls over, it issues an interrupt. Writing a value to the
counter just sets the current value, and it starts counting again from that
value.
Eight counters are implemented in the Zip System for process accounting.
This may change in the future, as nothing as yet uses these counters.
\section{Timer}
The Zip Timer is also very simple: it simply counts down to zero. When it
transitions from a one to a zero it creates an interrupt.
Writing any non-zero value to the timer starts the timer. If the high order
bit is set when writing to the timer, the timer becomes an interval timer and
reloads its last start time on any interrupt. Hence, to mark seconds, one
might set the timer to 100~million (the number of clocks per second), and
set the high bit. Ever after, the timer will interrupt the CPU once per
second (assuming a 100~MHz clock). This reload capability also limits the
maximum timer value to $2^{31}-1$, rather than $2^{32}-1$.
\section{Watchdog Timer}
The watchdog timer is no different from any of the other timers, save for one
critical difference: the interrupt line from the watchdog
timer is tied to the reset line of the CPU. Hence writing a `1' to the
watchdog timer will always reset the CPU.
To stop the Watchdog timer, write a `0' to it. To start it,
write any other number to it---as with the other timers.
While the watchdog timer supports interval mode, it doesn't make as much sense
as it did with the other timers.
\section{Jiffies}
This peripheral is motivated by the Linux use of `jiffies' whereby a process
can request to be put to sleep until a certain number of `jiffies' have
elapsed. Using this interface, the CPU can read the number of `jiffies'
from the peripheral (it only has the one location in address space), add the
sleep length to it, and write the result back to the peripheral. The zipjiffies
peripheral will record the value written to it only if it is nearer the current
counter value than the last current waiting interrupt time. If no other
interrupts are waiting, and this time is in the future, it will be enabled.
(There is currently no way to disable a jiffie interrupt once set, other
than to disable the interrupt line in the interrupt controller.) The processor
may then place this sleep request into a list among other sleep requests.
Once the timer expires, it would write the next Jiffy request to the peripheral
and wake up the process whose timer had expired.
Indeed, the Jiffies register is nothing more than a glorified counter with
an interrupt. Unlike the other counters, the Jiffies register cannot be set.
Writes to the jiffies register create an interrupt time. When the Jiffies
register later equals the value written to it, an interrupt will be asserted
and the register then continues counting as though no interrupt had taken
place.
The purpose of this register is to support alarm times within a CPU. To
set an alarm for a particular process $N$ clocks in advance, read the current
Jiffies value, and $N$, and write it back to the Jiffies register. The
O/S must also keep track of values written to the Jiffies register. Thus,
when an `alarm' trips, it should be removed from the list of alarms, the list
should be sorted, and the next alarm in terms of Jiffies should be written
to the register.
\section{Direct Memory Access Controller}
The Direct Memory Access (DMA) controller can be used to either move memory
from one location to another, to read from a peripheral into memory, or to
write from a peripheral into memory all without CPU intervention. Further,
since the DMA controller can issue (and does issue) pipeline wishbone accesses,
any DMA memory move will by nature be faster than a corresponding program
accomplishing the same move. To put this to numbers, it may take a program
18~clocks per word transferred, whereas this DMA controller can move one
word in two clocks--provided it has bus access. (The CPU gets priority over the
bus.)
When copying memory from one location to another, the DMA controller will
copy in units of a given transfer length--up to 1024 words at a time. It will
read that transfer length into its internal buffer, and then write to the
destination address from that buffer. If the CPU interrupts a DMA transfer,
it will release the bus, let the CPU complete whatever it needs to do, and then
restart its transfer by writing the contents of its internal buffer and then
re-entering its read cycle again.
When coupled with a peripheral, the DMA controller can be configured to start
a memory copy on an interrupt line going high. Further, the controller can be
configured to issue reads from (or to) the same address instead of incrementing
the address at each clock. The DMA completes once the total number of items
specified (not the transfer length) have been transferred.
In each case, once the transfer is complete and the DMA unit returns to
idle, the DMA will issue an interrupt.
\chapter{Operation}\label{chap:ops}
The Zip CPU, and even the Zip System, is not a System on a Chip (SoC). It
needs to be connected to its operational environment in order to be used.
Specifically, some per system adjustments need to be made:
\begin{enumerate}
\item The Zip System depends upon an external 32-bit Wishbone bus. This
must exist, and must be connected to the Zip CPU for it to work.
\item The Zip System needs to be told of its {\tt RESET\_ADDRESS}. This is
the program counter of the first instruction following a reset.
\item If you want the Zip System to start up on its own, you will need to
set the {\tt START\_HALTED} parameter to zero. Otherwise, if you
wish to manually start the CPU, that is if upon reset you want the
CPU start start in its halted, reset state, then set this parameter to
one.
\item The third parameter to set is the number of interrupts you will be
providing from external to the CPU. This can be anything from one
to nine, but it cannot be zero. (Wire this line to a 1'b0 if you
do not wish to support any external interrupts.)
\item Finally, you need to place into some wishbone accessible address, whether
RAM or (more likely) ROM, the initial instructions for the CPU.
\end{enumerate}
If you have enabled your CPU to start automatically, then upon power up the
CPU will immediately start executing your instructions.
This is, however, not how I have used the Zip CPU. I have instead used the
Zip CPU in a more controlled environment. For me, the CPU starts in a
halted state, and waits to be told to start. Further, the RESET address is a
location in RAM. After bringing up the board I am using, and further the
bus that is on it, the RAM memory is then loaded externally with the program
I wish the Zip System to run. Once the RAM is loaded, I release the CPU.
The CPU then runs until its halt condition, at which point its task is
complete.
Eventually, I intend to place an operating system onto the ZipSystem, I'm
just not there yet.
The rest of this chapter examines some common programming constructs, and
how they might be applied to the Zip System.
\section{Example: Idle Task}
One task every operating system needs is the idle task, the task that takes
place when nothing else can run. On the Zip CPU, this task is quite simple,
and it is shown in assemble in Tbl.~\ref{tbl:idle-asm}.
\begin{table}\begin{center}
\begin{tabular}{ll}
{\tt idle\_task:} \\
& {\em ; Wait for the next interrupt, then switch to supervisor task} \\
& {\tt WAIT} \\
& {\em ; When we come back, it's because the supervisor wishes to} \\
& {\em ; wait for an interrupt again, so go back to the top.} \\
& {\tt BRA idle\_task} \\
\end{tabular}
\caption{Example Idle Loop}\label{tbl:idle-asm}
\end{center}\end{table}
When this task runs, the CPU will fill up all of the pipeline stages up the
ALU. The {\tt WAIT} instruction, upon leaving the ALU, places the CPU into
a sleep state where nothing more moves. Sure, there may be some more settling,
the pipe cache continue to read until full, other instructions may issue until
the pipeline fills, but then everything will stall. Then, once an interrupt
takes place, control passes to the supervisor task to handle the interrupt.
When control passes back to this task, it will be on the next instruction.
Since that next instruction sends us back to the top of the task, the idle
task thus does nothing but wait for an interrupt.
This should be the lowest priority task, the task that runs when nothing else
can. It will help lower the FPGA power usage overall---at least its dynamic
power usage.
\section{Example: Memory Copy}
One common operation is that of a memory move or copy. Consider the C code
shown in Tbl.~\ref{tbl:memcp-c}.
\begin{table}\begin{center}
\parbox{4in}{\begin{tabbing}
{\tt void} \= {\tt memcp(void *dest, void *src, int len) \{} \\
\> {\tt for(int i=0; i<len; i++)} \\
\> \hspace{0.2in} {\tt *dest++ = *src++;} \\
\}
\end{tabbing}}
\caption{Example Memory Copy code in C}\label{tbl:memcp-c}
\end{center}\end{table}
This same code can be translated in Zip Assembly as shown in
Tbl.~\ref{tbl:memcp-asm}.
\begin{table}\begin{center}
\begin{tabular}{ll}
memcp: \\
& {\em ; R0 = *dest, R1 = *src, R2 = LEN} \\
& {\em ; The following will operate in 17 clocks per word minus one clock} \\
& {\tt CMP 0,R2} \\
& {\tt LOD.Z -1(SP),PC} {\em ; A conditional return }\\
& {\em ; (One stall on potentially writing to PC)} \\
& {\tt LOD (R1),R3} \\
& {\em ; (4 stalls, cannot be scheduled away)} \\
& {\tt STO R3,(R2)} {\em ; (4 schedulable stalls, has no impact now)} \\
& {\tt ADD 1,R1} \\
& {\tt SUB 1,R2} \\
& {\tt BNZ loop} \\
& {\em ; (5 stalls, if branch taken, to clear and refill the pipeline)} \\
& {\tt RET} \\
\end{tabular}
\caption{Example Memory Copy code in Zip Assembly}\label{tbl:memcp-asm}
\end{center}\end{table}
This example points out several things associated with the Zip CPU. First,
a straightforward implementation of a for loop is not the fastest loop
structure. For this reason, we have placed the test to continue at the
end. Second, all pointers are {\tt void} pointers to arbitrary 32--bit
data types. The Zip CPU does not have explicit support for smaller or larger
data types, and so this memory copy cannot be applied at a byte level.
Third, we've optimized the conditional jump to a return instruction into a
conditional return instruction.
\section{Context Switch}
Fundamental to any multiprocessing system is the ability to switch from one
task to the next. In the ZipSystem, this is accomplished in one of a couple
ways. The first step is that an interrupt happens. Anytime an interrupt
happens, the CPU needs to execute the following tasks in supervisor mode:
\begin{enumerate}
\item Check for a trap instruction. That is, if the user task requested a
trap, we may not wish to adjust the context, check interrupts, or call
the scheduler. Tbl.~\ref{tbl:trap-check}
\begin{table}\begin{center}
\begin{tabular}{ll}
{\tt return\_to\_user:} \\
& {\em; The instruction before the context switch processing must} \\
& {\em; be the RTU instruction that enacted user mode in the first} \\
& {\em; place. We show it here just for reference.} \\
& {\tt RTU} \\
{\tt trap\_check:} \\
& {\tt MOV uCC,R0} \\
& {\tt TST \$TRAP,R0} \\
& {\tt BNZ swap\_out} \\
& {; \em Do something here to execute the trap} \\
& {; \em Don't need to call the scheduler, so we can just return} \\
& {\tt BRA return\_to\_user} \\
\end{tabular}
\caption{Checking for whether the user issued a TRAP instruction}\label{tbl:trap-check}
\end{center}\end{table}
shows the rudiments of this code, while showing nothing of how the
actual trap would be implemented.
You may also wish to note that the instruction before the first instruction
in our context swap {\em must be} a return to userspace instruction.
Remember, the supervisor process is re--entered where it left off. This is
different from many other processors that enter interrupt mode at some vector
or other. In this case, we always enter supervisor mode right where we last
left.\footnote{The one exception to this rule is upon reset where supervisor
mode is entered at a pre--programmed wishbone memory address.}
\item Capture user counters. If the operating system is keeping track of
system usage via the accounting counters, those counters need to be
copied and accumulated into some master counter at this point.
\item Preserve the old context. This involves pushing all the user registers
onto the user stack and then copying the resulting stack address
into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.
\begin{table}\begin{center}
\begin{tabular}{ll}
{\tt swap\_out:} \\
& {\tt MOV -15(uSP),R5} \\
& {\tt STO R5,stack(R12)} \\
& {\tt MOV uR0,R0} \\
& {\tt MOV uR1,R1} \\
& {\tt MOV uR2,R2} \\
& {\tt MOV uR3,R3} \\
& {\tt MOV uR4,R4} \\
& {\tt STO R0,1(R5)} {\em ; Exploit memory pipelining: }\\
& {\tt STO R1,2(R5)} {\em ; All instructions write to stack }\\
& {\tt STO R2,3(R5)} {\em ; All offsets increment by one }\\
& {\tt STO R3,4(R5)} {\em ; Longest pipeline is 5 cycles.}\\
& {\tt STO R4,5(R5)} \\
& \ldots {\em ; Need to repeat for all user registers} \\
\iffalse
& {\tt MOV uR5,R0} \\
& {\tt MOV uR6,R1} \\
& {\tt MOV uR7,R2} \\
& {\tt MOV uR8,R3} \\
& {\tt MOV uR9,R4} \\
& {\tt STO R0,6(R5) }\\
& {\tt STO R1,7(R5) }\\
& {\tt STO R2,8(R5) }\\
& {\tt STO R3,9(R5) }\\
& {\tt STO R4,10(R5)} \\
\fi
& {\tt MOV uR10,R0} \\
& {\tt MOV uR11,R1} \\
& {\tt MOV uR12,R2} \\
& {\tt MOV uCC,R3} \\
& {\tt MOV uPC,R4} \\
& {\tt STO R0,11(R5)}\\
& {\tt STO R1,12(R5)}\\
& {\tt STO R2,13(R5)}\\
& {\tt STO R3,14(R5)}\\
& {\tt STO R4,15(R5)} \\
& {\em ; We can skip storing the stack, uSP, since it'll be stored}\\
& {\em ; elsewhere (in the task structure) }\\
\end{tabular}
\caption{Example Storing User Task Context}\label{tbl:context-out}
\end{center}\end{table}
For the sake of discussion, we assume the supervisor maintains a
pointer to the current task's structure in supervisor register
{\tt R12}, and that {\tt stack} is an offset to the beginning of this
structure indicating where the stack pointer is to be kept within it.
For those who are still interested, the full code for this context
save can be found as an assembler macro within the assembler
include file, {\tt sys.i}.
\item Reset the watchdog timer. If you are using the watchdog timer, it should
be reset on a context swap, to know that things are still working.
Example code for this is shown in Tbl.~\ref{tbl:reset-watchdog}.
\begin{table}\begin{center}
\begin{tabular}{ll}
\multicolumn{2}{l}{{\tt `define WATCHDOG\_ADDRESS 32'hc000\_0002}}\\
\multicolumn{2}{l}{{\tt `define WATCHDOG\_TICKS 32'd1\_000\_000} {; \em = 10 ms}}\\
& {\tt LDI WATCHDOG\_ADDRESS,R0} \\
& {\tt LDI WATCHDOG\_TICKS,R1} \\
& {\tt STO R1,(R0)}
\end{tabular}
\caption{Example Watchdog Reset}\label{tbl:reset-watchdog}
\end{center}\end{table}
\item Interrupt handling. An interrupt handler within the Zip System is nothing
more than a task. At context swap time, the supervisor needs to
disable all of the interrupts that have tripped, and then enable
all of the tasks that would deal with each of these interrupts.
These can be user tasks, run at higher priority than any other user
tasks. Either way, they will need to re--enable their own interrupt
themselves, if the interrupt is still relevant.
An example of this master interrut handling is shown in
Tbl.~\ref{tbl:pre-handler}.
\begin{table}\begin{center}
\begin{tabular}{ll}
{\tt pre\_handler:} \\
& {\tt LDI PIC\_ADDRESS,R0 } \\
& {\em ; Start by grabbing the interrupt state from the interrupt}\\
& {\em ; controller. We'll store this into the register R7 so that }\\
& {\em ; we can keep and preserve this information for the scheduler}\\
& {\em ; to use later. }\\
& {\tt LOD (R0),R1} \\
& {\tt MOV R1,R7 } \\
& {\em ; As a next step, we need to acknowledge and disable all active}\\
& {\em ; interrupts. We'll start by calculating all of our active}\\
& {\em ; interrupts.}\\
& {\tt AND 0x07fff,R1 } \\
& {\em ; Put the active interrupts into the upper half of R1} \\
& {\tt ROL 16,R1 } \\
& {\tt LDILO 0x0ffff,R1 } \\
& {\tt AND R7,R1}\\
& {\em ; Acknowledge and disable active interrupts}\\
& {\em ; This also disables all interrupts from the controller, so}\\
& {\em ; we'll need to re-enable interrupts in general shortly } \\
& {\tt STO R1,(R0) } \\
& {\em ; We leave our active interrupt mask in R7 so the scheduler can}\\
& {\em ; release any tasks that depended upon them. } \\
\end{tabular}
\caption{Example checking for active interrupts}\label{tbl:pre-handler}
\end{center}\end{table}
\item Calling the scheduler. This needs to be done to pick the next task
to switch to. It may be an interrupt handler, or it may be a normal
user task. From a priority standpoint, it would make sense that the
interrupt handlers all have a higher priority than the user tasks,
and that once they have been called the user tasks may then be called
again. If no task is ready to run, run the idle task to wait for an
interrupt.
This suggests a minimum of four task priorities:
\begin{enumerate}
\item Interrupt handlers, executed with their interrupts disabled
\item Device drivers, executed with interrupts re-enabled
\item User tasks
\item The idle task, executed when nothing else is able to execute
\end{enumerate}
For our purposes here, we'll just assume that a pointer to the current
task is maintained in {\tt R12}, that a {\tt JSR scheduler} is
called, and that the next current task is likewise placed into
{\tt R12}.
\item Restore the new tasks context. Given that the scheduler has returned a
task that can be run at this time, the stack pointer needs to be
pulled out of the tasks task structure, placed into the user
register, and then the rest of the user registers need to be popped
back off of the stack to run this task. An example of this is
shown in Tbl.~\ref{tbl:context-in},
\begin{table}\begin{center}
\begin{tabular}{ll}
{\tt swap\_in:} \\
& {\tt LOD stack(R12),R5} \\
& {\tt MOV 15(R1),uSP} \\
& {\em ; Be sure to exploit the memory pipelining capability} \\
& {\tt LOD 1(R5),R0} \\
& {\tt LOD 2(R5),R1} \\
& {\tt LOD 3(R5),R2} \\
& {\tt LOD 4(R5),R3} \\
& {\tt LOD 5(R5),R4} \\
& {\tt MOV R0,uR0} \\
& {\tt MOV R1,uR1} \\
& {\tt MOV R2,uR2} \\
& {\tt MOV R3,uR3} \\
& {\tt MOV R4,uR4} \\
& \ldots {\em ; Need to repeat for all user registers} \\
& {\tt LOD 11(R5),R0} \\
& {\tt LOD 12(R5),R1} \\
& {\tt LOD 13(R5),R2} \\
& {\tt LOD 14(R5),R3} \\
& {\tt LOD 15(R5),R4} \\
& {\tt MOV R0,uR10} \\
& {\tt MOV R1,uR11} \\
& {\tt MOV R2,uR12} \\
& {\tt MOV R3,uCC} \\
& {\tt MOV R4,uPC} \\
& {\tt BRA return\_to\_user} \\
\end{tabular}
\caption{Example Restoring User Task Context}\label{tbl:context-in}
\end{center}\end{table}
assuming as before that the task
pointer is found in supervisor register {\tt R12}.
As with storing the user context, the full code associated with
restoring the user context can be found in the assembler include
file, {\tt sys.i}.
\item Clear the userspace accounting registers. In order to keep track of
per process system usage, these registers need to be cleared before
reactivating the userspace process. That way, upon the next
interrupt, we'll know how many clocks the userspace program has
encountered, and how many instructions it was able to issue in
those many clocks.
\item Jump back to the instruction just before saving the last tasks context,
because that location in memory contains the return from interrupt
command that we are going to need to execute, in order to guarantee
that we return back here again.
\end{enumerate}
\chapter{Registers}\label{chap:regs}
The ZipSystem registers fall into two categories, ZipSystem internal registers
accessed via the ZipCPU shown in Tbl.~\ref{tbl:zpregs},
\begin{table}[htbp]
\begin{center}\begin{reglist}
PIC & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
WDT & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
& \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & {\em (Reserved for future use)} \\\hline
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
TMRA & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
TMRB & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
TMRC & \scalebox{0.8}{\tt 0xc0000006} & 32 & R/W & Timer C\\\hline
JIFF & \scalebox{0.8}{\tt 0xc0000007} & 32 & R/W & Jiffies \\\hline
MTASK & \scalebox{0.8}{\tt 0xc0000008} & 32 & R/W & Master Task Clock Counter \\\hline
MMSTL & \scalebox{0.8}{\tt 0xc0000009} & 32 & R/W & Master Stall Counter \\\hline
MPSTL & \scalebox{0.8}{\tt 0xc000000a} & 32 & R/W & Master Pre--Fetch Stall Counter \\\hline
MICNT & \scalebox{0.8}{\tt 0xc000000b} & 32 & R/W & Master Instruction Counter\\\hline
UTASK & \scalebox{0.8}{\tt 0xc000000c} & 32 & R/W & User Task Clock Counter \\\hline
UMSTL & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
UPSTL & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
UICNT & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
DMACTRL & \scalebox{0.8}{\tt 0xc0000010} & 32 & R/W & DMA Control Register\\\hline
DMALEN & \scalebox{0.8}{\tt 0xc0000011} & 32 & R/W & DMA total transfer length\\\hline
DMASRC & \scalebox{0.8}{\tt 0xc0000012} & 32 & R/W & DMA source address\\\hline
DMADST & \scalebox{0.8}{\tt 0xc0000013} & 32 & R/W & DMA destination address\\\hline
% Cache & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
\end{reglist}
\caption{Zip System Internal/Peripheral Registers}\label{tbl:zpregs}
\end{center}\end{table}
and the two debug registers shown in Tbl.~\ref{tbl:dbgregs}.
\begin{table}[htbp]
\begin{center}\begin{reglist}
ZIPCTRL & 0 & 32 & R/W & Debug Control Register \\\hline
ZIPDATA & 1 & 32 & R/W & Debug Data Register \\\hline
\end{reglist}
\caption{Zip System Debug Registers}\label{tbl:dbgregs}
\end{center}\end{table}
\section{Peripheral Registers}
The peripheral registers, listed in Tbl.~\ref{tbl:zpregs}, are shown in the
CPU's address space. These may be accessed by the CPU at these addresses,
and when so accessed will respond as described in Chapt.~\ref{chap:periph}.
These registers will be discussed briefly again here.
The Zip CPU Interrupt controller has four different types of bits, as shown in
Tbl.~\ref{tbl:picbits}.
\begin{table}\begin{center}
\begin{bitlist}
31 & R/W & Master Interrupt Enable\\\hline
30\ldots 16 & R/W & Interrupt Enables, write '1' to change\\\hline
15 & R & Current Master Interrupt State\\\hline
15\ldots 0 & R/W & Input Interrupt states, write '1' to clear\\\hline
\end{bitlist}
\caption{Interrupt Controller Register Bits}\label{tbl:picbits}
\end{center}\end{table}
The high order bit, or bit--31, is the master interrupt enable bit. When this
bit is set, then any time an interrupt occurs the CPU will be interrupted and
will switch to supervisor mode, etc.
Bits 30~\ldots 16 are interrupt enable bits. Should the interrupt line go
ghile while enabled, an interrupt will be generated. To set an interrupt enable
bit, one needs to write the master interrupt enable while writing a `1' to this
the bit. To clear, one need only write a `0' to the master interrupt enable,
while leaving this line high.
Bits 15\ldots 0 are the current state of the interrupt vector. Interrupt lines
trip when they go high, and remain tripped until they are acknowledged. If
the interrupt goes high for longer than one pulse, it may be high when a clear
is requested. If so, the interrupt will not clear. The line must go low
again before the status bit can be cleared.
As an example, consider the following scenario where the Zip CPU supports four
interrupts, 3\ldots0.
\begin{enumerate}
\item The Supervisor will first, while in the interrupts disabled mode,
write a {\tt 32'h800f000f} to the controller. The supervisor may then
switch to the user state with interrupts enabled.
\item When an interrupt occurs, the supervisor will switch to the interrupt
state. It will then cycle through the interrupt bits to learn which
interrupt handler to call.
\item If the interrupt handler expects more interrupts, it will clear its
current interrupt when it is done handling the interrupt in question.
To do this, it will write a '1' to the low order interrupt mask,
such as writing a {\tt 32'h80000001}.
\item If the interrupt handler does not expect any more interrupts, it will
instead clear the interrupt from the controller by writing a
{\tt 32'h00010001} to the controller.
\item Once all interrupts have been handled, the supervisor will write a
{\tt 32'h80000000} to the interrupt register to re-enable interrupt
generation.
\item The supervisor should also check the user trap bit, and possible soft
interrupt bits here, but this action has nothing to do with the
interrupt control register.
\item The supervisor will then leave interrupt mode, possibly adjusting
whichever task is running, by executing a return from interrupt
command.
\end{enumerate}
Leaving the interrupt controller, we show the timer registers bit definitions
in Tbl.~\ref{tbl:tmrbits}.
\begin{table}\begin{center}
\begin{bitlist}
31 & R/W & Auto-Reload\\\hline
30\ldots 0 & R/W & Current timer value\\\hline
\end{bitlist}
\caption{Timer Register Bits}\label{tbl:tmrbits}
\end{center}\end{table}
As you may recall, the timer just counts down to zero and then trips an
interrupt. Writing to the current timer value sets that value, and reading
from it returns that value. Writing to the current timer value while also
setting the auto--reload bit will send the timer into an auto--reload mode.
In this mode, upon setting its interrupt bit for one cycle, the timer will
also reset itself back to the value of the timer that was written to it when
the auto--reload option was written to it. To clear and stop the timer,
just simply write a `32'h00' to this register.
The Jiffies register is somewhat similar in that the register always changes.
In this case, the register counts up, whereas the timer always counted down.
Reads from this register, as shown in Tbl.~\ref{tbl:jiffybits},
\begin{table}\begin{center}
\begin{bitlist}
31\ldots 0 & R & Current jiffy value\\\hline
31\ldots 0 & W & Value/time of next interrupt\\\hline
\end{bitlist}
\caption{Jiffies Register Bits}\label{tbl:jiffybits}
\end{center}\end{table}
always return the time value contained in the register. Writes greater than
the current Jiffy value, that is where the new value minus the old value is
greater than zero while ignoring truncation, will set a new Jiffy interrupt
time. At that time, the Jiffy vector will clear, and another interrupt time
may either be written to it, or it will just continue counting without
activating any more interrupts.
The Zip CPU also supports several counter peripherals, mostly in the way of
process accounting. This peripherals have a single register associated with
them, shown in Tbl.~\ref{tbl:ctrbits}.
\begin{table}\begin{center}
\begin{bitlist}
31\ldots 0 & R/W & Current counter value\\\hline
\end{bitlist}
\caption{Counter Register Bits}\label{tbl:ctrbits}
\end{center}\end{table}
Writes to this register set the new counter value. Reads read the current
counter value.
The current design operation of these counters is that of performance counting.
Two sets of four registers are available for keeping track of performance.
The first is a task counter. This just counts clock ticks. The second
counter is a prefetch stall counter, then an master stall counter. These
allow the CPU to be evaluated as to how efficient it is. The fourth and
final counter is an instruction counter, which counts how many instructions the
CPU has issued.
It is envisioned that these counters will be used as follows: First, every time
a master counter rolls over, the supervisor (Operating System) will record
the fact. Second, whenever activating a user task, the Operating System will
set the four user counters to zero. When the user task has completed, the
Operating System will read the timers back off, to determine how much of the
CPU the process had consumed.
The final peripheral to discuss is the DMA controller. This controller
has four registers. Of these four, the length, source and destination address
registers should need no further explanation. They are full 32--bit registers
specifying the entire transfer length, the starting address to read from, and
the starting address to write to. The registers can be written to when the
DMA is idle, and read at any time. The control register, however, will need
some more explanation.
The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.
\begin{table}\begin{center}
\begin{bitlist}
31 & R & DMA Active\\\hline
30 & R & Wishbone error, transaction aborted. This bit is cleared the next time
this register is written to.\\\hline
29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline
28 & R/W & Set to '1' to prevent the controller from incrementing the
destination address, '0' for normal memory copy. \\\hline
27 \ldots 16 & W & The DMA Key. Write a 12'hfed to these bits to start the
activate any DMA transfer. \\\hline
27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline
26 \ldots 16 & R & Indicates the number of items in the transfer buffer that
have yet to be written. \\\hline
15 & R/W & Set to '1' to trigger on an interrupt, or '0' to start immediately
upon receiving a valid key.\\\hline
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
9\ldots 0 & R/W & Intermediate transfer length minus one. Thus, to transfer
one item at a time set this value to 0. To transfer 1024 at a time,
set it to 1024.\\\hline
\end{bitlist}
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
\end{center}\end{table}
This control register has been designed so that the common case of memory
access need only set the key and the transfer length. Hence, writing a
\hbox{32'h0fed03ff} to the control register will start any memory transfer.
On the other hand, if you wished to read from a serial port (constant address)
and put the result into a buffer every time a word was available, you
might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
have a serial port wired to the zero bit of this interrupt control. (The
DMA controller does not use the interrupt controller, and cannot clear
interrupts.) As a third example, if you wished to write to an external
FIFO anytime it was less than half full (had fewer than 512 items), and
interrupt line 2 indicated this condition, you might wish to issue a
\hbox{32'h1fed8dff} to this port.
\section{Debug Port Registers}
Accessing the Zip System via the debug port isn't as straight forward as
accessing the system via the wishbone bus. The debug port itself has been
reduced to two addresses, as outlined earlier in Tbl.~\ref{tbl:dbgregs}.
Access to the Zip System begins with the Debug Control register, shown in
Tbl.~\ref{tbl:dbgctrl}.
\begin{table}\begin{center}
\begin{bitlist}
31\ldots 14 & R & Reserved\\\hline
13 & R & CPU GIE setting\\\hline
12 & R & CPU is sleeping\\\hline
11 & W & Command clear PF cache\\\hline
10 & R/W & Command HALT, Set to '1' to halt the CPU\\\hline
9 & R & Stall Status, '1' if CPU is busy\\\hline
8 & R/W & Step Command, set to '1' to step the CPU, also sets the halt bit\\\hline
7 & R & Interrupt Request \\\hline
6 & R/W & Command RESET \\\hline
5\ldots 0 & R/W & Debug Register Address \\\hline
\end{bitlist}
\caption{Debug Control Register Bits}\label{tbl:dbgctrl}
\end{center}\end{table}
The first step in debugging access is to determine whether or not the CPU
is halted, and to halt it if not. To do this, first write a '1' to the
Command HALT bit. This will halt the CPU and place it into debug mode.
Once the CPU is halted, the stall status bit will drop to zero. Thus,
if bit 10 is high and bit 9 low, the debug port is open to examine the
internal state of the CPU.
At this point, the external debugger may examine internal state information
from within the CPU. To do this, first write again to the command register
a value (with command halt still high) containing the address of an internal
register of interest in the bottom 6~bits. Internal registers that may be
accessed this way are listed in Tbl.~\ref{tbl:dbgaddrs}.
\begin{table}\begin{center}
\begin{reglist}
sR0 & 0 & 32 & R/W & Supervisor Register R0 \\\hline
sR1 & 0 & 32 & R/W & Supervisor Register R1 \\\hline
sSP & 13 & 32 & R/W & Supervisor Stack Pointer\\\hline
sCC & 14 & 32 & R/W & Supervisor Condition Code Register \\\hline
sPC & 15 & 32 & R/W & Supervisor Program Counter\\\hline
uR0 & 16 & 32 & R/W & User Register R0 \\\hline
uR1 & 17 & 32 & R/W & User Register R1 \\\hline
uSP & 29 & 32 & R/W & User Stack Pointer\\\hline
uCC & 30 & 32 & R/W & User Condition Code Register \\\hline
uPC & 31 & 32 & R/W & User Program Counter\\\hline
PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline
WDT & 33 & 32 & R/W & Watchdog Timer\\\hline
CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline
TMRA & 36 & 32 & R/W & Timer A\\\hline
TMRB & 37 & 32 & R/W & Timer B\\\hline
TMRC & 38 & 32 & R/W & Timer C\\\hline
JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline
MTASK & 40 & 32 & R/W & Master task clock counter\\\hline
MMSTL & 41 & 32 & R/W & Master memory stall counter\\\hline
MPSTL & 42 & 32 & R/W & Master Pre-Fetch Stall counter\\\hline
MICNT & 43 & 32 & R/W & Master instruction counter\\\hline
UTASK & 44 & 32 & R/W & User task clock counter\\\hline
UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline
UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline
UICNT & 47 & 32 & R/W & User instruction counter\\\hline
DMACMD & 48 & 32 & R/W & DMA command and status register\\\hline
DMALEN & 49 & 32 & R/W & DMA transfer length\\\hline
DMARD & 50 & 32 & R/W & DMA read address\\\hline
DMAWR & 51 & 32 & R/W & DMA write address\\\hline
\end{reglist}
\caption{Debug Register Addresses}\label{tbl:dbgaddrs}
\end{center}\end{table}
Primarily, these ``registers'' include access to the entire CPU register
set, as well as the internal peripherals. To read one of these registers
once the address is set, simply issue a read from the data port. To write
one of these registers or peripheral ports, simply write to the data port
after setting the proper address.
In this manner, all of the CPU's internal state may be read and adjusted.
As an example of how to use this, consider what would happen in the case
of an external break point. If and when the CPU hits a break point that
causes it to halt, the Command HALT bit will activate on its own, the CPU
will then raise an external interrupt line and wait for a debugger to examine
its state. After examining the state, the debugger will need to remove
the breakpoint by writing a different instruction into memory and by writing
to the command register while holding the clear cache, command halt, and
step CPU bits high, (32'hd00). The debugger may then replace the breakpoint
now that the CPU has gone beyond it, and clear the cache again (32'h500).
To leave this debug mode, simply write a `32'h0' value to the command register.
\chapter{Wishbone Datasheets}\label{chap:wishbone}
The Zip System supports two wishbone ports, a slave debug port and a master
port for the system itself. These are shown in Tbl.~\ref{tbl:wishbone-slave}
\begin{table}[htbp]
\begin{center}
\begin{wishboneds}
Revision level of wishbone & WB B4 spec \\\hline
Type of interface & Slave, Read/Write, single words only \\\hline
Address Width & 1--bit \\\hline
Port size & 32--bit \\\hline
Port granularity & 32--bit \\\hline
Maximum Operand Size & 32--bit \\\hline
Data transfer ordering & (Irrelevant) \\\hline
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
Signal Names & \begin{tabular}{ll}
Signal Name & Wishbone Equivalent \\\hline
{\tt i\_clk} & {\tt CLK\_I} \\
{\tt i\_dbg\_cyc} & {\tt CYC\_I} \\
{\tt i\_dbg\_stb} & {\tt STB\_I} \\
{\tt i\_dbg\_we} & {\tt WE\_I} \\
{\tt i\_dbg\_addr} & {\tt ADR\_I} \\
{\tt i\_dbg\_data} & {\tt DAT\_I} \\
{\tt o\_dbg\_ack} & {\tt ACK\_O} \\
{\tt o\_dbg\_stall} & {\tt STALL\_O} \\
{\tt o\_dbg\_data} & {\tt DAT\_O}
\end{tabular}\\\hline
\end{wishboneds}
\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
\end{center}\end{table}
and Tbl.~\ref{tbl:wishbone-master} respectively.
\begin{table}[htbp]
\begin{center}
\begin{wishboneds}
Revision level of wishbone & WB B4 spec \\\hline
Type of interface & Master, Read/Write, single cycle or pipelined\\\hline
Address Width & 32--bit bits \\\hline
Port size & 32--bit \\\hline
Port granularity & 32--bit \\\hline
Maximum Operand Size & 32--bit \\\hline
Data transfer ordering & (Irrelevant) \\\hline
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
Signal Names & \begin{tabular}{ll}
Signal Name & Wishbone Equivalent \\\hline
{\tt i\_clk} & {\tt CLK\_O} \\
{\tt o\_wb\_cyc} & {\tt CYC\_O} \\
{\tt o\_wb\_stb} & {\tt STB\_O} \\
{\tt o\_wb\_we} & {\tt WE\_O} \\
{\tt o\_wb\_addr} & {\tt ADR\_O} \\
{\tt o\_wb\_data} & {\tt DAT\_O} \\
{\tt i\_wb\_ack} & {\tt ACK\_I} \\
{\tt i\_wb\_stall} & {\tt STALL\_I} \\
{\tt i\_wb\_data} & {\tt DAT\_I}
\end{tabular}\\\hline
\end{wishboneds}
\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
\end{center}\end{table}
I do not recommend that you connect these together through the interconnect.
Rather, the debug port of the CPU should be accessible regardless of the state
of the master bus.
You may wish to notice that neither the {\tt ERR} nor the {\tt RETRY} wires
have been implemented. What this means is that the CPU is currently unable
to detect a bus error condition, and so may stall indefinitely (hang) should
it choose to access a value not on the bus, or a peripheral that is not
yet properly configured.
\chapter{Clocks}\label{chap:clocks}
This core is based upon the Basys--3 development board sold by Digilent.
The Basys--3 development board contains one external 100~MHz clock, which is
sufficient to run the Zip CPU core.
\begin{table}[htbp]
\begin{center}
\begin{clocklist}
i\_clk & External & 100~MHz & 100~MHz & System clock.\\\hline
\end{clocklist}
\caption{List of Clocks}\label{tbl:clocks}
\end{center}\end{table}
I hesitate to suggest that the core can run faster than 100~MHz, since I have
had struggled with various timing violations to keep it at 100~MHz. So, for
now, I will only state that it can run at 100~MHz.
\chapter{I/O Ports}\label{chap:ioports}
The I/O ports to the Zip CPU may be grouped into three categories. The first
is that of the master wishbone used by the CPU, then the slave wishbone used
to command the CPU via a debugger, and then the rest. The first two of these
were already discussed in the wishbone chapter. They are listed here
for completeness in Tbl.~\ref{tbl:iowb-master}
\begin{table}
\begin{center}\begin{portlist}
{\tt o\_wb\_cyc} & 1 & Output & Indicates an active Wishbone cycle\\\hline
{\tt o\_wb\_stb} & 1 & Output & WB Strobe signal\\\hline
{\tt o\_wb\_we} & 1 & Output & Write enable\\\hline
{\tt o\_wb\_addr} & 32 & Output & Bus address \\\hline
{\tt o\_wb\_data} & 32 & Output & Data on WB write\\\hline
{\tt i\_wb\_ack} & 1 & Input & Slave has completed a R/W cycle\\\hline
{\tt i\_wb\_stall} & 1 & Input & WB bus slave not ready\\\hline
{\tt i\_wb\_data} & 32 & Input & Incoming bus data\\\hline
\end{portlist}\caption{CPU Master Wishbone I/O Ports}\label{tbl:iowb-master}\end{center}\end{table}
and~\ref{tbl:iowb-slave} respectively.
\begin{table}
\begin{center}\begin{portlist}
{\tt i\_wb\_cyc} & 1 & Input & Indicates an active Wishbone cycle\\\hline
{\tt i\_wb\_stb} & 1 & Input & WB Strobe signal\\\hline
{\tt i\_wb\_we} & 1 & Input & Write enable\\\hline
{\tt i\_wb\_addr} & 1 & Input & Bus address, command or data port \\\hline
{\tt i\_wb\_data} & 32 & Input & Data on WB write\\\hline
{\tt o\_wb\_ack} & 1 & Output & Slave has completed a R/W cycle\\\hline
{\tt o\_wb\_stall} & 1 & Output & WB bus slave not ready\\\hline
{\tt o\_wb\_data} & 32 & Output & Incoming bus data\\\hline
\end{portlist}\caption{CPU Debug Wishbone I/O Ports}\label{tbl:iowb-slave}\end{center}\end{table}
There are only four other lines to the CPU: the external clock, external
reset, incoming external interrupt line(s), and the outgoing debug interrupt
line. These are shown in Tbl.~\ref{tbl:ioports}.
\begin{table}
\begin{center}\begin{portlist}
{\tt i\_clk} & 1 & Input & The master CPU clock \\\hline
{\tt i\_rst} & 1 & Input & Active high reset line \\\hline
{\tt i\_ext\_int} & 1\ldots 6 & Input & Incoming external interrupts \\\hline
{\tt o\_ext\_int} & 1 & Output & CPU Halted interrupt \\\hline
\end{portlist}\caption{I/O Ports}\label{tbl:ioports}\end{center}\end{table}
The clock line was discussed briefly in Chapt.~\ref{chap:clocks}. We
typically run it at 100~MHz. The reset line is an active high reset. When
asserted, the CPU will start running again from its reset address in
memory. Further, depending upon how the CPU is configured and specifically on
the {\tt START\_HALTED} parameter, it may or may not start running
automatically. The {\tt i\_ext\_int} line is for an external interrupt. This
line may be as wide as 6~external interrupts, depending upon the setting of
the {\tt EXTERNAL\_INTERRUPTS} line. As currently configured, the ZipSystem
only supports one such interrupt line by default. For us, this line is the
output of another interrupt controller, but that's a board specific setup
detail. Finally, the Zip System produces one external interrupt whenever
the CPU halts to wait for the debugger.
\chapter{Initial Assessment}\label{chap:assessment}
Having now worked with the Zip CPU for a while, it is worth offering an
honest assessment of how well it works and how well it was designed. At the
end of this assessment, I will propose some changes that may take place in a
later version of this Zip CPU to make it better.
\section{The Good}
\begin{itemize}
\item The Zip CPU is light weight and fully featured as it exists today. For
anyone who wishes to build a general purpose CPU and then to
experiment with building and adding particular features, the Zip CPU
makes a good starting point--it is fairly simple. Modifications should
be simple enough.
\item As an estimate of the ``weight'' of this implementation, the CPU has
cost me less than 150 hours to implement from its inception.
\item The Zip CPU was designed to be an implementable soft core that could be
placed within an FPGA, controlling actions internal to the FPGA. It
fits this role rather nicely. It does not fit the role of a system on
a chip very well, but then it was never intended to be a system on a
chip but rather a system within a chip.
\item The extremely simplified instruction set of the Zip CPU was a good
choice. Although it does not have many of the commonly used
instructions, PUSH, POP, JSR, and RET among them, the simplified
instruction set has demonstrated an amazing versatility. I will contend
therefore and for anyone who will listen, that this instruction set
offers a full and complete capability for whatever a user might wish
to do with two exceptions: bytewise character access and accelerated
floating-point support.
\item This simplified instruction set is easy to decode.
\item The simplified bus transactions (32-bit words only) were also very easy
to implement.
\item The novel approach of having a single interrupt vector, which just
brings the CPU back to the instruction it left off at within the last
interrupt context doesn't appear to have been that much of a problem.
If most modern systems handle interrupt vectoring in software anyway,
why maintain hardware support for it?
\item My goal of a high rate of instructions per clock may not be the proper
measure. For example, if instructions are being read from a SPI flash
device, such as is common among FPGA implementations, these same
instructions may suffer stalls of between 64 and 128 cycles per
instruction just to read the instruction from the flash. Executing the
instruction in a single clock cycle is no longer the appropriate
measure. At the same time, it should be possible to use the DMA
peripheral to copy instructions from the FLASH to a temporary memory
location, after which they may be executed at a single instruction
cycle per access again.
\end{itemize}
\section{The Not so Good}
\begin{itemize}
\item While one of the stated goals was to use a small amount of logic,
3k~LUTs isn't that impressively small. Indeed, it's really much
too expensive when compared against other 8 and 16-bit CPUs that have
less than 1k LUTs.
Still, \ldots it's not bad, it's just not astonishingly good.
\item The fact that the instruction width equals the bus width means that the
instruction fetch cycle will always be interfering with any load or
store memory operation, with the only exception being if the
instruction is already in the cache. {\em This has become the
fundamental limit on the speed and performance of the CPU!}
Those familiar with the Von--Neumann approach of sharing a bus
between data and instructions will not be surprised by this assessment.
This could be fixed in one of three ways: the instruction set
architecture could be modified to handle Very Long Instruction Words
(VLIW) so that each 32--bit word would encode two or more instructions,
the instruction fetch bus width could be increased from 32--bits to
64--bits or more, or the instruction bus could be separated from the
data bus. Any and all of these approaches would increase the overall
LUT count.
\item The (non-existant) floating point unit was an after-thought, isn't even
built as a potential option, and most likely won't support the full
IEEE standard set of FPU instructions--even for single point precision.
This (non-existant) capability would benefit the most from an
out-of-order execution capability, which the Zip CPU does not have.
Still, sharing FPU registers with the main register set was a good
idea and worth preserving, as it simplifies context swapping.
Perhaps this really isn't a problem, but rather a feature. By not
implementing FPU instructions, the Zip CPU maintains a lower LUT count
than it would have if it did implement these instructions.
\item The CPU has no character support. This is both good and bad.
Realistically, the CPU works just fine without it. Characters can be
supported as subsets of 32-bit words without any problem. Practically,
though, it will make compiling non-Zip CPU code difficult--especially
anything that assumes sizeof(int)=4*sizeof(char), or that tries to
create unions with characters and integers and then attempts to
reference the address of the characters within that union.
\item The Zip CPU does not support a data cache. One can still be built
externally, but this is a limitation of the CPU proper as built.
Further, under the theory of the Zip CPU design (that of an embedded
soft-core processor within an FPGA, where any ``address'' may reference
either memory or a peripheral that may have side-effects), any data
cache would need to be based upon an initial knowledge of whether or
not it is supporting memory (cachable) or peripherals. This knowledge
must exist somewhere, and that somewhere is currently (and by design)
external to the CPU.
This may also be written off as a ``feature'' of the Zip CPU, since
the addition of a data cache can greatly increase the LUT count of
a soft core.
\item Many other instruction sets offer three operand instructions, whereas
the Zip CPU only offers two operand instructions. This means that it
takes the Zip CPU more instructions to do many of the same operations.
The good part of this is that it gives the Zip CPU a greater amount of
flexibility in its immediate operand mode, although that increased
flexibility isn't necessarily as valuable as one might like.
\item The Zip CPU does not currently detect and trap on either illegal
instructions or bus errors. Attempts to access non--existent
memory quietly return erroneous results, rather than halting the
process (user mode) or halting or resetting the CPU (supervisor mode).
\item The Zip CPU doesn't support out of order execution. I suppose it could
be modified to do so, but then it would no longer be the ``simple''
and low LUT count CPU it was designed to be. The two primary results
are that 1) loads may unnecessarily stall the CPU, even if other
things could be done while waiting for the load to complete, 2)
bus errors on stores will never be caught at the point of the error,
and 3) branch prediction becomes more difficult.
\item Although switching to an interrupt context in the Zip CPU design doesn't
require a tremendous swapping of registers, in reality it still
does--since any task swap still requires saving and restoring all
16~user registers. That's a lot of memory movement just to service
an interrupt.
\item The Zip CPU is by no means generic: it will never handle addresses
larger than 32-bits (16GB) without a complete and total redesign.
This may limit its utility as a generic CPU in the future, although
as an embedded CPU within an FPGA this isn't really much of a limit
or restriction.
\item While the Zip CPU has its own assembler, it has no linker and does not
(yet) support a compiler. The standard C library is an even longer
shot. My dream of having binutils and gcc support has not been
realized and at this rate may not be realized. (I've been intimidated
by the challenge everytime I've looked through those codes.)
\iffalse
\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle
execution, the Zip CPU is unable to exploit this parallelism. Instead,
apart from the DMA and the pipelined prefetch, all loads and stores
are single wishbone bus operations requiring a minimum of 3 clocks.
(In practice, this has turned into 7-clocks.)
% Addressed, 20150929
\item There is no control over whether or not an instruction sets the
condition codes--certain instructions always set the condition codes,
other instructions never set them. This effectively limits conditional
instructions to a single instruction only (with two or more
instructions as an exception), as the first instruction that sets
condition codes will break the condition code chain.
{\em (A proposed change below address this.)}
\item Using the CC register as a trap address was a bad idea--it limits the CC
registers ability to be used in future expansion, such as by adding
exception indication flags: bus error, floating point exception, etc.
{\em (This can be changed by a different O/S implementation of the trap
instruction.)}
\item The current implementation suffers from too many stalls on any
branch--even if the branch is known early on.
{\em (This is addressed in proposals below.)}
% Addressed, 20150918
\item In a similar fashion, a switch to interrupt context forces the pipeline
to be cleared, whereas it might make more sense to just continue
executing the instructions already in the pipeline while the prefetch
stage is working on switching to the interrupt context.
{\em (Also addressed in proposals below.)}
% This should happen so rarely that it is not really a problem
\fi
\end{itemize}
\section{The Next Generation}
This section could also be labeled as my ``To do'' list.
Given the feedback listed above, perhaps its time to consider what changes could be made to improve the Zip CPU in the future. I offer the following as proposals:
\begin{itemize}
\item {\bf Remove the low LUT goal.} It wasn't really achieved, and the
proposals below will only increase the amount of logic the Zip CPU
requires. While I expect that the Zip CPU will always be somewhat
of a light weight, it will never be the smallest kid on the block.
I'm actually struggling with this idea. The whole goal of the Zip
CPU was to be light weight. Wouldn't it make more sense to create and
maintain options whereby it would remain lightweight? For example, if
the process accounting registers are anything but light weight, why
keep them? Why not instead make some compile flags that just turn them
off, keeping the CPU lightweight? The same holds for the prefetch
cache.
\item The `{\tt .V}' condition was never used in any code other than my test
code. Suggest changing it to a `{\tt .LE}' condition, which seems
to be more useful.
\item {\bf Consider a more traditional Instruction Cache.} The current
pipelined instruction cache just reads a window of memory into
its cache. If the CPU leaves that window, the entire cache is
invalidated. A more traditional cache, however, might allow
common subroutines to stay within the cache without invalidating the
entire cache structure.
\iffalse
\item {\bf Adjust the Zip CPU so that conditional instructions do not set
flags}, although they may explicitly set condition codes if writing
to the CC register.
This is a simple change to the core, and may show up in new releases.
% Fixed, 20150918
\item Add in an {\bf unpredictable branch delay slot}, so that on any branch
the delay slot may or may not be executed before the branch.
Instructions that do not depend upon the branch, and that should be
executed were the branch not taken, could be placed into the delay
slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,
whereas it wouldn't affect the timing of the branch if taken. It would
just do something irrelevant.
% Changes made, 20150918, make this option no longer relevant
\item {\bf Re-engineer Branch Processing.} There's no reason why a {\tt BRA}
instruction should create five stall cycles. The decode stage, plus
the prefetch engine, should be able to drop this number of stalls via
better branch handling.
Indeed, this could turn into a simple means of branch prediction:
if {\tt BRA} suffered a single stall only, whereas {\tt BRA.C}
suffered five stalls, then {\tt BRA.!C} followed by {\tt BRA} would
be faster than a {\tt BRA.C} instruction. This would then allow a
compiler to do explicit branch optimizations.
Of course, longer branches using {\tt ADD X,PC} would still not be
optimized.
% DONE: 20150918 -- to include the ADD X,PC instructions
\item {\bf Request bus access for Load/Store two cycles earlier.} The problem
here is the contention for the bus between the memory unit and the
prefetch unit. Currently, the memory unit must ask the prefetch
unit to release the bus if it is in the middle of a bus cycle. At this
point, the prefetch drops the {\tt STB} line on the next clock and must
then wait for the last {\tt ACK} before releasing the bus. If the
request takes one clock, dropping the strobe line the next, waiting
for an acknowledgement takes another, and then the bus must be idle
for one cycle before starting again, these extra cycles add up.
It should be possible to tell the prefetch stage to give up the bus
as soon as the decoder knows the instruction will need the bus.
Indeed, if done in the decode stage, this might drop the seven cycle
access down by two cycles.
% FIXED: 20150918
\item {\bf Very Long Instruction Word (VLIW).} Now, to speed up operation, I
propose that the Zip CPU instruction set be modified towards a Very
Long Instruction Word (VLIW) implementation. In this implementation,
an instruction word may contain either one or two separate
instructions. The first instruction would take up the high order bits,
the second optional instruction the lower 16-bits. Further, I propose
that any of the ALU instructions (SUB through LSR) automatically have
a second instruction whenever their operand `B' is a register, and use
the full 20-bit immediate if not. This will effectively eliminate the
register plus immediate mode for all of these instructions.
This is the minimal required change to increase the number of
instructions per clock cycle. Other changes would need to take place
as well to support this. These include:
\begin{itemize}
\item Instruction words containing two instructions would take two
clocks to complete, while requiring only a single cycle
instruction fetch.
\item Instructions preceded by a label in the asseembler must always
start in the high order word.
\item VLIW's, once started, must always execute to completion. The
upper word may set the PC, the lower word may not. Regardless
of whether the upper word sets the PC, the lower word must
still be guaranteed to complete before the PC changes. On any
switch to (or from) interrupt context, both instructions must
complete or none of the instructions in the word shall
complete prior to the switch.
\item STEP commands and BREAK instructions will only take place after
the entire word is executed.
\end{itemize}
If done well, the assembler should be able to handle these changes
with the biggest impacts to the user being increased performance and
a loss of the register plus immediate ALU modes. (These weren't really
relevant for the XOR, OR, AND, etc. operations anyway.) Machine code
compatibility will not be maintained.
A proposed secondary instruction set might consist of: a four bit
operand (any of the prior instructions would be supported, with some
exceptions such as moves to and from user registers while in
supervisor mode not being supported), a 4-bit register result (PC not
allowed), a 3-bit conditional (identical to the conditional for the
upper word), a single bit for whether or not an immediate is present
or not, followed by either a 4-bit register or a 4-bit signed
immediate. The multiply instruction would steal the immediate flag to
be used as a sign indication, forcing both operands to be registers
without any immediate offsets.
{\em Initial conversion of several library functions to this secondary
instruction set has demonstrated little to no gain. The problem was
that the new instruction set was made by joining a rarely used
instruction (ALU with register and not immediate) with a more common
instruction. The utility was then limited by the utility of the rare
instrction, which limited the impact of the entire approach. }
\else
\item {\bf Very Long Instruction Word (VLIW).} The goal here would be to
create a new instruction set whereby two instructions would be encoded
in each 32--bit word. While this may speed up
CPU operation, it would necessitate an instruction redesign.
\fi
\end{itemize}
% Appendices
% Index
\end{document}
Go to most recent revision | Compare with Previous | Blame | View Log