Subversion Repositories zipcpu

################################################################################
#
# Filename:     Makefile
#
# Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
#
# Purpose:      This makefile builds a verilator simulation of the zipsystem.
#               It does not make the system within Vivado or Quartus.
#
#
# Creator:      Dan Gisselquist, Ph.D.
#               Gisselquist Technology, LLC
#
################################################################################
#
# Copyright (C) 2015, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of  the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
# for more details.
#
# License:      GPL, v3, as defined and found on www.gnu.org,
#               http://www.gnu.org/licenses/gpl.html
#
#
################################################################################
#
.PHONY: all
all: zipsystem zipbones cpudefs.h div

CORED:= core
PRPHD:= peripherals
AUXD := aux
VSRC := zipsystem.v cpudefs.v                                   \
                $(PRPHD)/wbdmac.v $(PRPHD)/icontrol.v           \
                $(PRPHD)/zipcounter.v $(PRPHD)/zipjiffies.v     \
                $(PRPHD)/ziptimer.v $(PRPHD)/ziptrap.v          \
        $(CORED)/zipcpu.v $(CORED)/cpuops.v $(CORED)/idecode.v  \
                $(CORED)/pipefetch.v $(CORED)/prefetch.v        \
                $(CORED)/pfcache.v                              \
                $(CORED)/memops.v $(CORED)/pipemem.v            \
        $(AUXD)/busdelay.v                                      \
                $(AUXD)/wbdblpriarb.v $(AUXD)/wbpriarbiter.v    \
        $(CORED)/idecode.v $(CORED)/cpuops.v
VZIP := zipbones.v cpudefs.v                                    \
        $(CORED)/zipcpu.v $(CORED)/cpuops.v $(CORED)/idecode.v  \
                $(CORED)/pipefetch.v $(CORED)/prefetch.v        \
                $(CORED)/pfcache.v                              \
                $(CORED)/memops.v $(CORED)/pipemem.v            \
        $(AUXD)/busdelay.v $(AUXD)/wbdblpriarb.v                \
        $(CORED)/idecode.v $(CORED)/cpuops.v

VOBJ := obj_dir

$(VOBJ)/Vzipsystem.cpp: $(VSRC)
        verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipsystem.v
$(VOBJ)/Vzipsystem.h: $(VOBJ)/Vzipsystem.cpp

$(VOBJ)/Vzipbones.cpp: $(VZIP)
        verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipbones.v
$(VOBJ)/Vzipbones.h: $(VOBJ)/Vzipbones.cpp

$(VOBJ)/Vdiv.cpp: $(CORED)/div.v
        verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) $(CORED)/div.v
$(VOBJ)/Vdiv.h: $(VOBJ)/Vdiv.cpp

$(VOBJ)/Vzipsystem__ALL.a: $(VOBJ)/Vzipsystem.cpp $(VOBJ)/Vzipsystem.h
        cd $(VOBJ); make --no-print-directory -f Vzipsystem.mk

$(VOBJ)/Vzipbones__ALL.a: $(VOBJ)/Vzipbones.cpp $(VOBJ)/Vzipbones.h
        cd $(VOBJ); make --no-print-directory -f Vzipbones.mk

$(VOBJ)/Vdiv__ALL.a: $(VOBJ)/Vdiv.cpp $(VOBJ)/Vdiv.h
        cd $(VOBJ); make --no-print-directory -f Vdiv.mk

cpudefs.h: cpudefs.v
        @echo "Building cpudefs.h"
        @echo "// " > $@
        @echo "// Do not edit this file, it is automatically generated!" >> $@
        @echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
        @echo "// " >> $@
        @grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@

.PHONY: zipsystem
zipsystem: $(VOBJ)/Vzipsystem__ALL.a

.PHONY: zipbones
zipbones: $(VOBJ)/Vzipbones__ALL.a

.PHONY: div
div: $(VOBJ)/Vdiv__ALL.a

.PHONY: clean
clean:
        rm -rf $(VOBJ) cpudefs.h