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///////////////////////////////////////////////////////////////////////////
//
// Filename:	cpuops.v
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:	This supports the instruction set reordering of operations
//		created by the second generation instruction set, as well as
//	the new operations of POPC (population count) and BREV (bit reversal).
//
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
module	cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
			o_illegal, o_busy);
	parameter	IMPLEMENT_MPY = 1;
	input		i_clk, i_rst, i_ce;
	input		[3:0]	i_op;
	input		[31:0]	i_a, i_b;
	input			i_valid;
	output	reg	[31:0]	o_c;
	output	wire	[3:0]	o_f;
	output	reg		o_valid;
	output	wire		o_illegal;
	output	wire		o_busy;
 
	// Rotate-left pre-logic
	wire	[63:0]	w_rol_tmp;
	assign	w_rol_tmp = { i_a, i_a } << i_b[4:0];
	wire	[31:0]	w_rol_result;
	assign	w_rol_result = w_rol_tmp[63:32]; // Won't set flags
 
	// Shift register pre-logic
	wire	[32:0]		w_lsr_result, w_asr_result;
	assign	w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
				: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
	assign	w_lsr_result = (|i_b[31:5])? 33'h00
				: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
	// Bit reversal pre-logic
	wire	[31:0]	w_brev_result;
	genvar	k;
	generate
	for(k=0; k<32; k=k+1)
	begin : bit_reversal_cpuop
		assign w_brev_result[k] = i_b[31-k];
	end endgenerate
 
	// Popcount pre-logic
	wire	[31:0]	w_popc_result;
	assign	w_popc_result[5:0]=
		 ({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
		+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
		+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
		+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
		+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
		+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
		+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
		+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
	assign	w_popc_result[31:6] = 26'h00;
 
	// Prelogic for our flags registers
	wire	z, n, v;
	reg	c, pre_sign, set_ovfl;
	always @(posedge i_clk)
		if (i_ce) // 1 LUT
			set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
				||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
				||(i_op == 4'h6) // LSL
				||(i_op == 4'h5)); // LSR
 
 
	// A 4-way multiplexer can be done in one 6-LUT.
	// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
	//	the Xilinx multiplexer fabric that follows. 
	// Given that we wish to apply this multiplexer approach to 33-bits,
	// this will cost a minimum of 132 6-LUTs.
	generate
	if (IMPLEMENT_MPY == 0)
	begin
		always @(posedge i_clk)
		if (i_ce)
		begin
			pre_sign <= (i_a[31]);
			c <= 1'b0;
			casez(i_op)
			4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
			4'b0001:   o_c   <= i_a & i_b;		// BTST/And
			4'b0010:{c,o_c } <= i_a + i_b;		// Add
			4'b0011:   o_c   <= i_a | i_b;		// Or
			4'b0100:   o_c   <= i_a ^ i_b;		// Xor
			4'b0101:{o_c,c } <= w_lsr_result[32:0];	// LSR
			4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];	// LSL
			4'b0111:{o_c,c } <= w_asr_result[32:0];	// ASR
			4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
			4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
			// 4'h1010: The unimplemented MPYU,
			// 4'h1011: and here for the unimplemented MPYS
			4'b1100:   o_c   <= w_brev_result;	// BREV
			4'b1101:   o_c   <= w_popc_result;	// POPC
			4'b1110:   o_c   <= w_rol_result;	// ROL
			default:   o_c   <= i_b;		// MOV, LDI
			endcase
		end
 
		assign o_busy = 1'b0;
 
		reg	r_illegal;
		always @(posedge i_clk)
			r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
		assign o_illegal = r_illegal;
	end else begin
		//
		// Multiply pre-logic
		//
		wire	signed	[16:0]	w_mpy_a_input, w_mpy_b_input;
		wire		[33:0]	w_mpy_result;
		reg		[31:0]	r_mpy_result;
		assign	w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
		assign	w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
		assign	w_mpy_result   = w_mpy_a_input * w_mpy_b_input;
		always @(posedge i_clk)
			if (i_ce)
				r_mpy_result  = w_mpy_result[31:0];
 
		//
		// The master ALU case statement
		//
		always @(posedge i_clk)
		if (i_ce)
		begin
			pre_sign <= (i_a[31]);
			c <= 1'b0;
			casez(i_op)
			4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
			4'b0001:   o_c   <= i_a & i_b;		// BTST/And
			4'b0010:{c,o_c } <= i_a + i_b;		// Add
			4'b0011:   o_c   <= i_a | i_b;		// Or
			4'b0100:   o_c   <= i_a ^ i_b;		// Xor
			4'b0101:{o_c,c } <= w_lsr_result[32:0];	// LSR
			4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];	// LSL
			4'b0111:{o_c,c } <= w_asr_result[32:0];	// ASR
			4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
			4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
			4'b1010:   o_c   <= r_mpy_result; // MPYU
			4'b1011:   o_c   <= r_mpy_result; // MPYS
			4'b1100:   o_c   <= w_brev_result;	// BREV
			4'b1101:   o_c   <= w_popc_result;	// POPC
			4'b1110:   o_c   <= w_rol_result;	// ROL
			default:   o_c   <= i_b;		// MOV, LDI
			endcase
		end else if (r_busy)
			o_c <= r_mpy_result;
 
		reg	r_busy;
		initial	r_busy = 1'b0;
		always @(posedge i_clk)
			r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
					&&(i_op[3:1] == 3'h5);
 
		assign o_busy = r_busy;
 
		assign o_illegal = 1'b0;
	end endgenerate
 
	assign	z = (o_c == 32'h0000);
	assign	n = (o_c[31]);
	assign	v = (set_ovfl)&&(pre_sign != o_c[31]);
 
	assign	o_f = { v, n, c, z };
 
	initial	o_valid = 1'b0;
	always @(posedge i_clk)
		if (i_rst)
			o_valid <= 1'b0;
		else
			o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
					||(o_busy);
endmodule