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;
; Filename:     test.S
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      A disorganized test, just showing some initial operation of
;               the CPU.  As a disorganized test, it doesn't prove anything
;               beyond the generic operation of the CPU.
;
; Status:       As of July, 2015, the assembler isn't sophisticated enough
;               to handle the address resolution needed to assemble this file.
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
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;
test:
        clr     r0
        mov     r0,r1
        mov     $1+r0,r2
        mov     $2+r0,r3
        mov     $22h+r0,r4
        mov     $377h+r0,ur5
        noop
        nop
        add     r2,r0
        add     $32,r0
        add     $-33,r0
        not.z   r0
        clrf    r0
        ldi     $5,r1
        cmp     $0+r0,r1
        not.lt  r0
        not.ge  r1
        lod     $-7+pc,r2
        ldihi   $deadh,r3
        ldihi   $beefh,r3

testbench:
        // Let's build a software test bench.
        clr     r12     ; R12 will point to our peripherals
        ldihi   $c000h,r12
        mov     r12,ur12
        mov     test_start,upc
        ldihi   $8001,r0
        ldilo   $-1,r0
        sto     r0,$1+r12
        rtu
        lod     r12,r0
        cmp     $0,r0
        bnz     $1
        halt
        busy

; Now for a series of tests.  If the test fails, call the trap
; interrupt with the test number that failed.  Upon completion,
; call the trap with #0.

; Now for a series of tests.  If the test fails, call the trap
; interrupt with the test number that failed.  Upon completion,
; call the trap with #0.

; Test LDI to PC
; Some data registers
        .dat    __here__+5
test_start:
        ldi     $2,r11
        lod     $-3+pc,pc
        clr     r11
        noop
        cmp     $0,r11
        sto.z   r11,(r12)
        add     $1,r0
        add     $1,r0

// Let's test whether overflow works
        ldi     $3,r11
        ldi     $-1,r0
        lsr     $1,r0
        add     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from subtraction
        ldi     $4,r11
        ldi     $1,r0
        .dat    0x5000001f              ; rol $31,r0
        sub     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from LSR
        ldi     $5,r11
        ldi     $1,r0
        .dat    0x5000001f              ; rol $31,r0
        lsr     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from LSL
        ldi     $6,r11
        ldi     $1,r0
        .dat    0x5000001e
        lsl     $1,r0
        bv      $1
        sto     r11,(r12)

// Overflow set from LSL, negative to positive
        ldi     $7,r11
        ldi     $1,r0
        .dat    0x5000001f; //  E: ROL $30,R0
        lsl     $1,r0
        bv      $1
        sto     r11,(r12)

// Test carry
        ldi     $0x010,r11
        ldi     $-1,r0
        add     $1,r0
        tst     $2,cc
        sto.z   r11,(r12)
// and carry from subtraction
        ldi     $17,r11
        sub     $1,r0
        tst     $2,cc
        sto.z   r11,(r12)

// Let's try a loop: for i=0; i<5; i++)
//      We'll use R0=i, Immediates for 5
for_loop:
        ldi     $18,r11
        clr     r0
        noop
        add     $1,r0
        cmp     $5,r0
        blt     for_loop
//
// Let's try a reverse loop.  Such loops are usually cheaper to
// implement, and this one is no different: 2 loop instructions 
// (minus setup instructions) vs 3 from before.
// R0 = 5; (from before)
// do {
// } while (R0 > 0);
bgt_loop:
        ldi     $19,r11
        noop
        sub     $1,r0
        bgt     bgt_loop

// How about the same thing with a >= comparison?
// R1 = 5; // Need to do this explicitly
// do {
// } while(R1 >= 0);
        ldi     $20,r00
        ldi     $5,r1
bge_loop:
        noop
        sub     $1,r1
        bge     bge_loop

// Let's try the reverse loop again, only this time we'll store our
// loop variable in memory.
// R0 = 5; (from before)
// do {
// } while (R0 > 0);
        ldi     $21,r11
        bra     $1
loop_var:
        .dat    0
mem_loop:
        mov     $-2+pc,r1
        clr     r2
        ldi     $5,r0
        sto     r1,(r0)
        add     $1,r2
        add     $14,r0
        lod     (r1),r0
        sub     $1,r0
        bgt     $-6
        cmp     $5,r2
        sto.ne  r11,(r12)

// Return success / Test the trap interrupt
        clr     r11
        sto     r11,(r12)
        noop
        noop

// Go into an infinite loop if the trap fails
// Permanent loop instruction -- a busy halt if you will
        busy

// And, in case we miss a halt ...
        halt