URL
https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
Subversion Repositories zx_ula
[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_for_digilent_spartan3_starter_kit_with_ps2_keyboard/] [master_clock.v] - Rev 19
Go to most recent revision | Compare with Previous | Blame | View Log
//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 12.4 // \ \ Application : xaw2verilog // / / Filename : master_clock.v // /___/ /\ Timestamp : 04/21/2012 19:26:35 // \ \ / \ // \___\/\___\ // //Command: xaw2verilog -st C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock.xaw C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock //Design Name: master_clock //Device: xc3s1000-ft256-4 // // Module master_clock // Generated by Xilinx Architecture Wizard // Written for synthesis tool: XST // Period Jitter (unit interval) for block DCM_INST = 0.05 UI // Period Jitter (Peak-to-Peak) for block DCM_INST = 1.92 ns `timescale 1ns / 1ps module master_clock(CLKIN_IN, CLKFX_OUT, CLKIN_IBUFG_OUT, CLK0_OUT); input CLKIN_IN; output CLKFX_OUT; output CLKIN_IBUFG_OUT; output CLK0_OUT; wire CLKFB_IN; wire CLKFX_BUF; wire CLKIN_IBUFG; wire CLK0_BUF; wire GND_BIT; assign GND_BIT = 0; assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; assign CLK0_OUT = CLKFB_IN; BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKFX_OUT)); IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), .O(CLKIN_IBUFG)); BUFG CLK0_BUFG_INST (.I(CLK0_BUF), .O(CLKFB_IN)); DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25), .CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), .FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) DCM_INST (.CLKFB(CLKFB_IN), .CLKIN(CLKIN_IBUFG), .DSSEN(GND_BIT), .PSCLK(GND_BIT), .PSEN(GND_BIT), .PSINCDEC(GND_BIT), .RST(GND_BIT), .CLKDV(), .CLKFX(CLKFX_BUF), .CLKFX180(), .CLK0(CLK0_BUF), .CLK2X(), .CLK2X180(), .CLK90(), .CLK180(), .CLK270(), .LOCKED(), .PSDONE(), .STATUS()); endmodule
Go to most recent revision | Compare with Previous | Blame | View Log