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`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Dept. Architecture and Computing Technology. University of Seville // Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es // // Create Date: 19:13:39 20-May-2011 // Design Name: 7-segment display for Spartan 3 Starter Board // Module Name: 7-segment display for Spartan 3 Starter Board // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 1.00 - File Created // Additional Comments: GPL License policies apply to the contents of this file. // ////////////////////////////////////////////////////////////////////////////////// module display( input clk, // some megahertzs are enough input load, // positive-edge load signal input [15:0] valor, // 16-bit (4 hex digit) value to show output [3:0] an, // 4 anodes (4 displays) output [6:0] seg // 7 cathodes per display ); reg [3:0] ranodo = 4'b1110; assign an = ranodo; reg [6:0] rseg = 7'b0000000; assign seg = rseg; reg [3:0] rvalor[0:3]; reg [1:0] digito = 2'b00; reg [15:0] contador = 16'h0000; wire clkdisplay = contador[15]; always @(posedge clk) contador <= contador + 1; always @(posedge load) begin rvalor[0] <= valor[3:0]; rvalor[1] <= valor[7:4]; rvalor[2] <= valor[11:8]; rvalor[3] <= valor[15:12]; end always @(posedge clkdisplay) begin digito = digito + 1; ranodo = {ranodo[2:0],ranodo[3]}; rseg = ~hex2seg(rvalor[digito]); end function [6:0] hex2seg (input [3:0] v); case (v) 0: hex2seg = 7'b1101111; 1: hex2seg = 7'b0100100; 2: hex2seg = 7'b1110011; 3: hex2seg = 7'b1110110; 4: hex2seg = 7'b0111100; 5: hex2seg = 7'b1011110; 6: hex2seg = 7'b1011111; 7: hex2seg = 7'b1101100; 8: hex2seg = 7'b1111111; 9: hex2seg = 7'b1111110; 10: hex2seg = 7'b1111101; 11: hex2seg = 7'b0011111; 12: hex2seg = 7'b1001011; 13: hex2seg = 7'b0110111; 14: hex2seg = 7'b1011011; 15: hex2seg = 7'b1011001; endcase endfunction endmodule