URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Rev 10

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Loading design for application trce from file P6809_P6809.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HE
Package:     TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
Thu Feb  6 15:36:11 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf 
Design file:     P6809_P6809.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.251ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)

   Delay:              24.583ns  (36.2% logic, 63.8% route), 18 logic levels.

 Constraint Details:

     24.583ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.251ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
                  --------
                   24.583   (36.2% logic, 63.8% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.309ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)

   Delay:              24.525ns  (36.0% logic, 64.0% route), 18 logic levels.

 Constraint Details:

     24.525ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.309ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
                  --------
                   24.525   (36.0% logic, 64.0% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.324ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)

   Delay:              24.510ns  (36.1% logic, 63.9% route), 19 logic levels.

 Constraint Details:

     24.510ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.324ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
                  --------
                   24.510   (36.1% logic, 63.9% route), 19 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.351ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)

   Delay:              24.483ns  (36.2% logic, 63.8% route), 19 logic levels.

 Constraint Details:

     24.483ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.351ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
                  --------
                   24.483   (36.2% logic, 63.8% route), 19 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.362ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[1]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)

   Delay:              24.472ns  (36.3% logic, 63.7% route), 18 logic levels.

 Constraint Details:

     24.472ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.362ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q1 SLICE_260 (from cpu_clkgen)
ROUTE        30     1.613     R18C14A.Q1 to     R18C24D.D1 cpu0/k_ind_ea[1]
CTOF_DEL    ---     0.495     R18C24D.D1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
                  --------
                   24.472   (36.3% logic, 63.7% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.382ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)

   Delay:              24.452ns  (36.0% logic, 64.0% route), 19 logic levels.

 Constraint Details:

     24.452ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.382ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
                  --------
                   24.452   (36.0% logic, 64.0% route), 19 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.391ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/regs/IY_pipe_14  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)

   Delay:              24.443ns  (39.4% logic, 60.6% route), 20 logic levels.

 Constraint Details:

     24.443ns physical path delay cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.391ns

 Physical Path Details:

      Data path cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R16C22A.CLK to     R16C22A.Q0 cpu0/regs/SLICE_323 (from cpu_clkgen)
ROUTE        16     1.390     R16C22A.Q0 to     R16C25A.A1 cpu0/regs/IY_1_sqmuxaf
CTOF_DEL    ---     0.495     R16C25A.A1 to     R16C25A.F1 cpu0/regs/SLICE_1012
ROUTE         1     0.693     R16C25A.F1 to     R16C25A.B0 cpu0/regs/N_665
CTOF_DEL    ---     0.495     R16C25A.B0 to     R16C25A.F0 cpu0/regs/SLICE_1012
ROUTE         3     1.435     R16C25A.F0 to     R21C25B.C1 cpu0/regs/IY[0]
CTOOFX_DEL  ---     0.721     R21C25B.C1 to   R21C25B.OFX0 cpu0/regs/ea/ea_reg_3[0]/SLICE_511
ROUTE         5     1.487   R21C25B.OFX0 to     R21C19D.D0 cpu0/regs/ea_reg[0]
CTOF_DEL    ---     0.495     R21C19D.D0 to     R21C19D.F0 cpu0/regs/SLICE_917
ROUTE         2     1.152     R21C19D.F0 to     R19C18A.C1 cpu0/regs/ea/N_72
C1TOFCO_DE  ---     0.889     R19C18A.C1 to    R19C18A.FCO cpu0/regs/ea/SLICE_45
ROUTE         1     0.000    R19C18A.FCO to    R19C18B.FCI cpu0/regs/ea/eamem_addr_o_cry_0
FCITOFCO_D  ---     0.162    R19C18B.FCI to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
                  --------
                   24.443   (39.4% logic, 60.6% route), 20 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to cpu0/regs/SLICE_323:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R16C22A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.396ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to cpu_clkgen +)

   Delay:              24.438ns  (36.4% logic, 63.6% route), 18 logic levels.

 Constraint Details:

     24.438ns physical path delay SLICE_260 to cpu0/regs/SLICE_64 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.396ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOF1_DE  ---     0.643    R19C19A.FCI to     R19C19A.F1 cpu0/regs/ea/SLICE_41
ROUTE         4     2.403     R19C19A.F1 to     R16C32D.D0 cpu0/regs/ea/regs_o_eamem_addr[8]
CTOF_DEL    ---     0.495     R16C32D.D0 to     R16C32D.F0 cpu0/regs/SLICE_922
ROUTE         1     0.645     R16C32D.F0 to     R14C32C.D0 cpu0/regs/ea/N_1412
CTOF_DEL    ---     0.495     R14C32C.D0 to     R14C32C.F0 cpu0/SLICE_900
ROUTE         2     1.704     R14C32C.F0 to     R12C25C.D0 cpu0/datamux_o_dest[8]
CTOF_DEL    ---     0.495     R12C25C.D0 to     R12C25C.F0 cpu0/regs/SLICE_361
ROUTE         6     0.469     R12C25C.F0 to     R12C25B.C1 cpu0/regs/left_1[8]
CTOF_DEL    ---     0.495     R12C25B.C1 to     R12C25B.F1 cpu0/regs/SLICE_1189
ROUTE         1     1.088     R12C25B.F1 to     R14C25C.B1 cpu0/regs/N_251
CTOF_DEL    ---     0.495     R14C25C.B1 to     R14C25C.F1 cpu0/regs/SLICE_955
ROUTE         1     0.626     R14C25C.F1 to     R14C25C.D0 cpu0/regs/SS_16[8]
CTOF_DEL    ---     0.495     R14C25C.D0 to     R14C25C.F0 cpu0/regs/SLICE_955
ROUTE         1     1.570     R14C25C.F0 to     R10C26B.C0 cpu0/regs/SS_231_i1_mux
C0TOFCO_DE  ---     1.023     R10C26B.C0 to    R10C26B.FCO cpu0/regs/SLICE_67
ROUTE         1     0.000    R10C26B.FCO to    R10C26C.FCI cpu0/regs/SS_cry[9]
FCITOFCO_D  ---     0.162    R10C26C.FCI to    R10C26C.FCO cpu0/regs/SLICE_66
ROUTE         1     0.000    R10C26C.FCO to    R10C26D.FCI cpu0/regs/SS_cry[11]
FCITOFCO_D  ---     0.162    R10C26D.FCI to    R10C26D.FCO cpu0/regs/SLICE_65
ROUTE         1     0.000    R10C26D.FCO to    R10C27A.FCI cpu0/regs/SS_cry[13]
FCITOF1_DE  ---     0.643    R10C27A.FCI to     R10C27A.F1 cpu0/regs/SLICE_64
ROUTE         1     0.000     R10C27A.F1 to    R10C27A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
                  --------
                   24.438   (36.4% logic, 63.6% route), 18 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R10C27A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.409ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)

   Delay:              24.425ns  (36.0% logic, 64.0% route), 19 logic levels.

 Constraint Details:

     24.425ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.409ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
                  --------
                   24.425   (36.0% logic, 64.0% route), 19 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.413ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        cpu0/regs/SU[13]  (to cpu_clkgen +)

   Delay:              24.421ns  (35.7% logic, 64.3% route), 17 logic levels.

 Constraint Details:

     24.421ns physical path delay SLICE_260 to cpu0/regs/SLICE_56 meets
     25.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.413ns

 Physical Path Details:

      Data path SLICE_260 to cpu0/regs/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
FCITOF1_DE  ---     0.643    R11C23D.FCI to     R11C23D.F1 cpu0/regs/SLICE_56
ROUTE         1     0.000     R11C23D.F1 to    R11C23D.DI1 cpu0/regs/SU_s[13] (to cpu_clkgen)
                  --------
                   24.421   (35.7% logic, 64.3% route), 17 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_260:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to cpu0/regs/SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     2.399       27.PADDI to    R11C23D.CLK cpu_clkgen
                  --------
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.

Report:   40.406MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
MHz ;                                   |   40.000 MHz|   40.406 MHz|  18  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
Thu Feb  6 15:36:12 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf 
Design file:     P6809_P6809.ncd
Preference file: P6809_P6809.prf
Device,speed:    LCMXO2-7000HE,m
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.217ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[6]  (from cpu_clkgen +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)

   Delay:               0.322ns  (40.7% logic, 59.3% route), 1 logic levels.

 Constraint Details:

      0.322ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.217ns

 Physical Path Details:

      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q0 SLICE_454 (from cpu_clkgen)
ROUTE         4     0.191     R14C17C.Q0 to *_R13C16.ADA11 textctrl/chars_data[6] (to cpu_clkgen)
                  --------
                    0.322   (40.7% logic, 59.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_454:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.846       27.PADDI to    R14C17C.CLK cpu_clkgen
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.899       27.PADDI to *R_R13C16.CLKA cpu_clkgen
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.234ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[7]  (from cpu_clkgen +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)

   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.

 Constraint Details:

      0.339ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.234ns

 Physical Path Details:

      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q1 SLICE_454 (from cpu_clkgen)
ROUTE         4     0.208     R14C17C.Q1 to *_R13C16.ADA12 textctrl/chars_data[7] (to cpu_clkgen)
                  --------
                    0.339   (38.6% logic, 61.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_454:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.846       27.PADDI to    R14C17C.CLK cpu_clkgen
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.899       27.PADDI to *R_R13C16.CLKA cpu_clkgen
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.344ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              reset_cnt[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        reset_cnt[0]  (to cpu_clkgen +)

   Delay:               0.288ns  (45.5% logic, 54.5% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay SLICE_444 to SLICE_444 meets
     -0.056ns LSR_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.056ns) by 0.344ns

 Physical Path Details:

      Data path SLICE_444 to SLICE_444:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131     R19C8D.CLK to      R19C8D.Q0 SLICE_444 (from cpu_clkgen)
ROUTE         5     0.157      R19C8D.Q0 to     R19C8D.LSR reset_cnt[0] (to cpu_clkgen)
                  --------
                    0.288   (45.5% logic, 54.5% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to SLICE_444:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.846       27.PADDI to     R19C8D.CLK cpu_clkgen
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to SLICE_444:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.846       27.PADDI to     R19C8D.CLK cpu_clkgen
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/blink_cnt[0]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/blink_cnt[0]  (to cpu_clkgen +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path textctrl/SLICE_29 to textctrl/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R25C10A.CLK to     R25C10A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
ROUTE         1     0.127     R25C10A.Q1 to     R25C10A.A1 textctrl/blink_cnt[0]
CTOF_DEL    ---     0.099     R25C10A.A1 to     R25C10A.F1 textctrl/SLICE_29
ROUTE         1     0.000     R25C10A.F1 to    R25C10A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10A.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10A.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/blink_cnt[4]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/blink_cnt[4]  (to cpu_clkgen +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path textctrl/SLICE_27 to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q1 textctrl/SLICE_27 (from cpu_clkgen)
ROUTE         1     0.127     R25C10C.Q1 to     R25C10C.A1 textctrl/blink_cnt[4]
CTOF_DEL    ---     0.099     R25C10C.A1 to     R25C10C.F1 textctrl/SLICE_27
ROUTE         1     0.000     R25C10C.F1 to    R25C10C.DI1 textctrl/blink_cnt_s[4] (to cpu_clkgen)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/blink_cnt[3]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/blink_cnt[3]  (to cpu_clkgen +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path textctrl/SLICE_27 to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
ROUTE         1     0.127     R25C10C.Q0 to     R25C10C.A0 textctrl/blink_cnt[3]
CTOF_DEL    ---     0.099     R25C10C.A0 to     R25C10C.F0 textctrl/SLICE_27
ROUTE         1     0.000     R25C10C.F0 to    R25C10C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/blink_cnt[1]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/blink_cnt[1]  (to cpu_clkgen +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path textctrl/SLICE_28 to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
ROUTE         1     0.127     R25C10B.Q0 to     R25C10B.A0 textctrl/blink_cnt[1]
CTOF_DEL    ---     0.099     R25C10B.A0 to     R25C10B.F0 textctrl/SLICE_28
ROUTE         1     0.000     R25C10B.F0 to    R25C10B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.370ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/blink_cnt[2]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/blink_cnt[2]  (to cpu_clkgen +)

   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.

 Constraint Details:

      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns

 Physical Path Details:

      Data path textctrl/SLICE_28 to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
ROUTE         1     0.127     R25C10B.Q1 to     R25C10B.A1 textctrl/blink_cnt[2]
CTOF_DEL    ---     0.099     R25C10B.A1 to     R25C10B.F1 textctrl/SLICE_28
ROUTE         1     0.000     R25C10B.F1 to    R25C10B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
                  --------
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.371ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/chars_data[3]  (from cpu_clkgen +)
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to cpu_clkgen +)

   Delay:               0.476ns  (27.5% logic, 72.5% route), 1 logic levels.

 Constraint Details:

      0.476ns physical path delay textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.053ns skew requirement (totaling 0.105ns) by 0.371ns

 Physical Path Details:

      Data path textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R19C14D.CLK to     R19C14D.Q1 textctrl/SLICE_1231 (from cpu_clkgen)
ROUTE         4     0.345     R19C14D.Q1 to *R_R20C16.ADA8 textctrl/chars_data[3] (to cpu_clkgen)
                  --------
                    0.476   (27.5% logic, 72.5% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_1231:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.846       27.PADDI to    R19C14D.CLK cpu_clkgen
                  --------
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.899       27.PADDI to *R_R20C16.CLKA cpu_clkgen
                  --------
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.


Passed: The following path meets requirements by 0.372ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              textctrl/x_cnt[3]  (from cpu_clkgen +)
   Destination:    FF         Data in        textctrl/x_cnt[3]  (to cpu_clkgen +)

   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.

 Constraint Details:

      0.359ns physical path delay textctrl/SLICE_13 to textctrl/SLICE_13 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns

 Physical Path Details:

      Data path textctrl/SLICE_13 to textctrl/SLICE_13:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.131    R22C10C.CLK to     R22C10C.Q0 textctrl/SLICE_13 (from cpu_clkgen)
ROUTE         3     0.129     R22C10C.Q0 to     R22C10C.A0 textctrl/x_cnt[3]
CTOF_DEL    ---     0.099     R22C10C.A0 to     R22C10C.F0 textctrl/SLICE_13
ROUTE         1     0.000     R22C10C.F0 to    R22C10C.DI0 textctrl/x_cnt_s[3] (to cpu_clkgen)
                  --------
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path clk40_i to textctrl/SLICE_13:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R22C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path clk40_i to textctrl/SLICE_13:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       367     0.828       27.PADDI to    R22C10C.CLK cpu_clkgen
                  --------
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
MHz ;                                   |            -|            -|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Rev 10
