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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_tw1.html] - Rev 9
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
Loading design for application trce from file P6809_P6809_map.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HE
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status: Final Version 1.36
Performance Hardware Data Status: Final) Version 23.4
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
Mon Jan 6 06:54:33 2014
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
Design file: P6809_P6809_map.ncd
Preference file: P6809_P6809.prf
Device,speed: LCMXO2-7000HE,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (672 errors)</FONT></A></LI>
</FONT> 4096 items scored, 672 timing errors detected.
Warning: 37.396MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
4096 items scored, 672 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.741ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
Delay: 26.575ns (42.4% logic, 57.6% route), 22 logic levels.
Constraint Details:
26.575ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 exceeds
25.000ns delay constraint less
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.741ns
Physical Path Details:
Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 *SLICE_229.CLK to */SLICE_229.Q0 cpu0/SLICE_229 (from cpu_clkgen)
ROUTE 26 e 1.234 */SLICE_229.Q0 to *SLICE_1227.A1 cpu0/alu/rb_in[0]
CTOF_DEL --- 0.495 *SLICE_1227.A1 to *SLICE_1227.F1 cpu0/alu/SLICE_1227
ROUTE 1 e 1.234 *SLICE_1227.F1 to */SLICE_167.A1 cpu0/alu/alu8/a8/rb_in_i[0]
C1TOFCO_DE --- 0.889 */SLICE_167.A1 to *SLICE_167.FCO cpu0/alu/alu8/a8/SLICE_167
ROUTE 1 e 0.001 *SLICE_167.FCO to *SLICE_166.FCI cpu0/alu/alu8/a8/un8_q_out_cry_0
FCITOF0_DE --- 0.585 *SLICE_166.FCI to */SLICE_166.F0 cpu0/alu/alu8/a8/SLICE_166
ROUTE 1 e 1.234 */SLICE_166.F0 to *SLICE_1216.A1 cpu0/alu/alu8/a8/un8_q_out[1]
CTOF_DEL --- 0.495 *SLICE_1216.A1 to *SLICE_1216.F1 cpu0/alu/SLICE_1216
ROUTE 1 e 1.234 *SLICE_1216.F1 to */SLICE_176.C0 cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO
C0TOFCO_DE --- 1.023 */SLICE_176.C0 to *SLICE_176.FCO cpu0/alu/alu8/a8/SLICE_176
ROUTE 1 e 0.001 *SLICE_176.FCO to *SLICE_175.FCI cpu0/alu/alu8/a8/q_out_2_cry_2
FCITOFCO_D --- 0.162 *SLICE_175.FCI to *SLICE_175.FCO cpu0/alu/alu8/a8/SLICE_175
ROUTE 1 e 0.001 *SLICE_175.FCO to *SLICE_174.FCI cpu0/alu/alu8/a8/q_out_2_cry_4
FCITOFCO_D --- 0.162 *SLICE_174.FCI to *SLICE_174.FCO cpu0/alu/alu8/a8/SLICE_174
ROUTE 1 e 0.001 *SLICE_174.FCO to *SLICE_173.FCI cpu0/alu/alu8/a8/q_out_2_cry_6
FCITOF0_DE --- 0.585 *SLICE_173.FCI to */SLICE_173.F0 cpu0/alu/alu8/a8/SLICE_173
ROUTE 1 e 1.234 */SLICE_173.F0 to */SLICE_639.A1 cpu0/alu/alu8/a8/N_2388
CTOF_DEL --- 0.495 */SLICE_639.A1 to */SLICE_639.F1 cpu0/alu/alu8/a8/SLICE_639
ROUTE 2 e 1.234 */SLICE_639.F1 to */SLICE_561.A0 cpu0/alu/alu8/arith_q[7]
CTOOFX_DEL --- 0.721 */SLICE_561.A0 to *LICE_561.OFX0 cpu0/alu/alu8/q_out_4[7]/SLICE_561
ROUTE 2 e 1.234 *LICE_561.OFX0 to *SLICE_1235.A0 cpu0/alu/alu8/N_160
CTOF_DEL --- 0.495 *SLICE_1235.A0 to *SLICE_1235.F0 cpu0/alu/alu8/SLICE_1235
ROUTE 2 e 1.234 *SLICE_1235.F0 to */SLICE_542.A1 cpu0/alu/q8_out[7]
CTOOFX_DEL --- 0.721 */SLICE_542.A1 to *LICE_542.OFX0 cpu0/alu/alu8/l8/datamux_o_dest[7]/SLICE_542
ROUTE 2 e 1.234 *LICE_542.OFX0 to */SLICE_361.B1 cpu0/datamux_o_dest[7]
CTOF_DEL --- 0.495 */SLICE_361.B1 to */SLICE_361.F1 cpu0/regs/SLICE_361
ROUTE 9 e 1.234 */SLICE_361.F1 to *SLICE_1126.B0 cpu0/regs/left_1[7]
CTOF_DEL --- 0.495 *SLICE_1126.B0 to *SLICE_1126.F0 cpu0/regs/SLICE_1126
ROUTE 1 e 1.234 *SLICE_1126.F0 to */SLICE_902.A1 cpu0/regs/N_286
CTOF_DEL --- 0.495 */SLICE_902.A1 to */SLICE_902.F1 cpu0/regs/SLICE_902
ROUTE 1 e 0.480 */SLICE_902.F1 to */SLICE_902.B0 cpu0/regs/SU_16[7]
CTOF_DEL --- 0.495 */SLICE_902.B0 to */SLICE_902.F0 cpu0/regs/SLICE_902
ROUTE 1 e 1.234 */SLICE_902.F0 to *s/SLICE_68.C1 cpu0/regs/SU_212_i1_mux
C1TOFCO_DE --- 0.889 *s/SLICE_68.C1 to */SLICE_68.FCO cpu0/regs/SLICE_68
ROUTE 1 e 0.001 */SLICE_68.FCO to */SLICE_67.FCI cpu0/regs/SU_cry[7]
FCITOFCO_D --- 0.162 */SLICE_67.FCI to */SLICE_67.FCO cpu0/regs/SLICE_67
ROUTE 1 e 0.001 */SLICE_67.FCO to */SLICE_66.FCI cpu0/regs/SU_cry[9]
FCITOFCO_D --- 0.162 */SLICE_66.FCI to */SLICE_66.FCO cpu0/regs/SLICE_66
ROUTE 1 e 0.001 */SLICE_66.FCO to */SLICE_65.FCI cpu0/regs/SU_cry[11]
FCITOFCO_D --- 0.162 */SLICE_65.FCI to */SLICE_65.FCO cpu0/regs/SLICE_65
ROUTE 1 e 0.001 */SLICE_65.FCO to */SLICE_64.FCI cpu0/regs/SU_cry[13]
FCITOF1_DE --- 0.643 */SLICE_64.FCI to *s/SLICE_64.F1 cpu0/regs/SLICE_64
ROUTE 1 e 0.001 *s/SLICE_64.F1 to */SLICE_64.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
--------
26.575 (42.4% logic, 57.6% route), 22 logic levels.
Warning: 37.396MHz is the maximum frequency for this preference.
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
MHz ; | 40.000 MHz| 37.396 MHz| 22 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
cpu0/alu/q8_out[7] | 2| 550| 81.85%
| | |
cpu0/alu/alu8/N_160 | 2| 550| 81.85%
| | |
cpu0/alu/alu8/a8/N_2388 | 1| 550| 81.85%
| | |
cpu0/alu/alu8/arith_q[7] | 2| 550| 81.85%
| | |
cpu0/regs/left_1[7] | 9| 550| 81.85%
| | |
cpu0/datamux_o_dest[7] | 2| 550| 81.85%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_6 | 1| 454| 67.56%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_4 | 1| 336| 50.00%
| | |
cpu0/alu/alu8/a8/un8_q_out_cry_2 | 1| 334| 49.70%
| | |
cpu0/regs/SS_cry[7] | 1| 323| 48.07%
| | |
cpu0/regs/SU_cry[7] | 1| 323| 48.07%
| | |
cpu0/regs/N_250 | 1| 275| 40.92%
| | |
cpu0/regs/N_286 | 1| 275| 40.92%
| | |
cpu0/regs/SS_228_i1_mux | 1| 275| 40.92%
| | |
cpu0/regs/SS_16[7] | 1| 275| 40.92%
| | |
cpu0/regs/SU_212_i1_mux | 1| 275| 40.92%
| | |
cpu0/regs/SU_16[7] | 1| 275| 40.92%
| | |
cpu0/regs/SS_cry[9] | 1| 267| 39.73%
| | |
cpu0/regs/SU_cry[9] | 1| 267| 39.73%
| | |
cpu0/alu/alu8/a8/un8_q_out_cry_4 | 1| 252| 37.50%
| | |
cpu0/alu/alu8/a8/un8_q_out_cry_0 | 1| 220| 32.74%
| | |
cpu0/alu/rb_in[0] | 26| 214| 31.85%
| | |
cpu0/alu/alu8/a8/rb_in_i[0] | 1| 208| 30.95%
| | |
cpu0/regs/SS_cry[11] | 1| 203| 30.21%
| | |
cpu0/regs/SU_cry[11] | 1| 203| 30.21%
| | |
cpu0/alu/alu8/a8/rb_in_i[1] | 1| 146| 21.73%
| | |
cpu0/alu/rb_in[1] | 26| 146| 21.73%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_2 | 1| 144| 21.43%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO | 1| 114| 16.96%
| | |
cpu0/alu/alu8/a8/un8_q_out[3] | 1| 114| 16.96%
| | |
cpu0/alu/alu8/a8/rb_in_i[2] | 1| 112| 16.67%
| | |
cpu0/alu/rb_in[2] | 23| 112| 16.67%
| | |
cpu0/regs/SS_cry[13] | 1| 112| 16.67%
| | |
cpu0/regs/SU_cry[13] | 1| 112| 16.67%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO_0 | 1| 108| 16.07%
| | |
cpu0/alu/alu8/a8/un8_q_out[6] | 1| 108| 16.07%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO_0 | 1| 106| 15.77%
| | |
cpu0/alu/alu8/a8/un8_q_out[4] | 1| 106| 15.77%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO | 1| 104| 15.48%
| | |
cpu0/alu/alu8/a8/un8_q_out[5] | 1| 104| 15.48%
| | |
cpu0/alu/alu8/a8/un8_q_out_cry_6 | 1| 96| 14.29%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_7_0_RNO | 1| 96| 14.29%
| | |
cpu0/alu/alu8/a8/un8_q_out[7] | 1| 96| 14.29%
| | |
cpu0/alu/alu8/a8/rb_in_i[3] | 1| 82| 12.20%
| | |
cpu0/alu/rb_in[3] | 24| 82| 12.20%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO_0 | 1| 74| 11.01%
| | |
cpu0/alu/alu8/a8/un8_q_out[2] | 1| 74| 11.01%
| | |
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO | 1| 70| 10.42%
| | |
cpu0/alu/alu8/a8/un8_q_out[1] | 1| 70| 10.42%
| | |
----------------------------------------------------------------------------
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 1 clocks:
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 672 Score: 491074
Cumulative negative slack: 491074
Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
Mon Jan 6 06:54:33 2014
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
Design file: P6809_P6809_map.ncd
Preference file: P6809_P6809.prf
Device,speed: LCMXO2-7000HE,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI> 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.443ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q cpu_clk (from cpu_clkgen +)
Destination: FF Data in cpu_clk (to cpu_clkgen +)
Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels.
Constraint Details:
0.430ns physical path delay SLICE_383 to SLICE_383 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns
Physical Path Details:
Data path SLICE_383 to SLICE_383:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 SLICE_383.CLK to SLICE_383.Q0 SLICE_383 (from cpu_clkgen)
ROUTE 101 e 0.199 SLICE_383.Q0 to SLICE_383.A0 cpu_clk
CTOF_DEL --- 0.099 SLICE_383.A0 to SLICE_383.F0 SLICE_383
ROUTE 1 e 0.001 SLICE_383.F0 to SLICE_383.DI0 cpu_clk_i (to cpu_clkgen)
--------
0.430 (53.5% logic, 46.5% route), 2 logic levels.
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 1 clocks:
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 672 (setup), 0 (hold)
Score: 491074 (setup), 0 (hold)
Cumulative negative slack: 491074 (491074+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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