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synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"*****************************************************************Warning: You are running on an unsupported platform'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and abovecurrent platform: CentOS release 6.4 (Final)Kernel \r on an \m*****************************************************************Running in Lattice modeStarting: /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatchInstall: /usr/local/diamond/2.2_x64/synpbaseDate: Thu Feb 6 15:34:32 2014Version: G-2012.09L-SP1Arguments: -product synplify_pro -batch P6809_P6809_synplify.tclProductType: synplify_prolog file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"Running proj_1|P6809Running Compile on proj_1|P6809Running Compile Process on proj_1|P6809Running Compile Input on proj_1|P6809Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srscompiler Completed with warningsReturn Code: 1Run Time:00h:00m:06sCopied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srfJob Compile Process completed on proj_1|P6809Running Premap on proj_1|P6809premap Completed with warningsReturn Code: 1Run Time:00h:00m:02sJob Compile completed on proj_1|P6809Running Map on proj_1|P6809Running Map & Optimize on proj_1|P6809fpga_mapper Completed with warningsReturn Code: 1Run Time:00h:00m:31sJob Map completed on proj_1|P6809Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srfJob Logic Synthesis completed on proj_1|P6809TCL script complete: "P6809_P6809_synplify.tcl"exit status=0Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.Lattice Diamond Version 2.2.0.101Child process exit with 0.==contents of P6809_P6809.srf#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013#install: /usr/local/diamond/2.2_x64/synpbase#OS: Linux#Hostname: node01.pacito.sys#Implementation: P6809$ Start of Compile#Thu Feb 6 15:34:32 2014Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013@N|Running in 64-bit modeCopyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"Verilog syntax check successful!File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompilingSelecting top level module CC3_top@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bit 1 of k_mem_dest[1:0]@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused@ENDProcess took 0h:00m:04s realtime, 0h:00m:02s cputime# Thu Feb 6 15:34:36 2014###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rptPrinting clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)Clock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group--------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0====================================================================================================================@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.syn_allowed_resources : blockrams=26 set on top level netlist CC3_topFinished Pre Mapping Phase.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Thu Feb 6 15:34:40 2014###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.Product Version G-2012.09L-SP1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)Available hyper_sources - for debug and ip modelsNone FoundFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 160MB)@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register zff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register cff pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_write_pc pushed in.@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":141:35:141:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":142:35:142:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 160MB)Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 596 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)264 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 596 div============================================================================================ Gated/Generated Clocks =====************** None **************----------------------------------==================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:16s; Memory used current: 170MB peak: 230MB)Writing EDIF Netlist and constraint filesG-2012.09L-SP1@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:17s; Memory used current: 174MB peak: 230MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"##### START OF TIMING REPORT #####[# Timing Report written on Thu Feb 6 15:35:10 2014#Top view: CC3_topRequested Frequency: 1.0 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: 978.937Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 47.5 MHz 1000.000 21.063 978.937 inferred Inferred_clkgroup_0========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise--------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack--------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.937 | No paths - | No paths - | No paths -==========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.296 978.937cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.296 979.080cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.284 979.092cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.288 979.231cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.284 979.235cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.299 979.502cpu0.alu.rb_in[5] CC3_top|clk40_i FD1P3AX Q rb_in[5] 1.284 979.533cpu0.alu.rb_in[6] CC3_top|clk40_i FD1P3AX Q rb_in[6] 1.272 979.545cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.299 979.645cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.299 979.645==============================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 978.937cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 978.937cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.937cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.937cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.080cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.080cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.080cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.080cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 979.223cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.223==============================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 1000.000- Setup time: 0.106+ Clock delay at ending point: 0.000 (ideal)= Required time: 999.894- Propagation time: 20.957- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : 978.937Number of logic level(s): 22Starting point: cpu0.alu.rb_in[0] / QEnding point: cpu0.regs.SS[15] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-----------------------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] FD1P3AX Q Out 1.296 1.296 -rb_in[0] Net - - - - 24cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.296 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.864 -rb_in_i[0] Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.864 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.408 -un8_q_out_cry_0 Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.408 -cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.957 -un8_q_out[2] Net - - - - 1cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.957 -cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.974 -q_out_2_cry_1_0_RNO_0 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.974 -cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.519 -q_out_2_cry_2 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_cry_3_0 CCU2D CIN In 0.000 7.519 -cpu0.alu.alu16.a16.q_out_2_cry_3_0 CCU2D COUT Out 0.143 7.661 -q_out_2_cry_4 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.661 -cpu0.alu.alu16.a16.q_out_2_cry_5_0 CCU2D COUT Out 0.143 7.804 -q_out_2_cry_6 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.804 -cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.353 -N_2370 Net - - - - 1cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.353 -cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.506 -arith_q[7] Net - - - - 3cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.506 -cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.523 -N_60 Net - - - - 1cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.523 -cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.809 -q16_out[7] Net - - - - 2cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 B In 0.000 11.809 -cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 Z Out 1.017 12.826 -datamux_o_dest_bm[7] Net - - - - 1cpu0.alu.alu8.datamux_o_dest[7] PFUMX ALUT In 0.000 12.826 -cpu0.alu.alu8.datamux_o_dest[7] PFUMX Z Out 0.286 13.112 -datamux_o_dest[7] Net - - - - 2cpu0.regs.left_1[7] ORCALUT4 A In 0.000 13.112 -cpu0.regs.left_1[7] ORCALUT4 Z Out 1.273 14.385 -left_1[7] Net - - - - 9cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.385 -cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.402 -N_250 Net - - - - 1cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.402 -cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.418 -SS_16[7] Net - - - - 1cpu0.regs.SS_230_m3 ORCALUT4 B In 0.000 16.418 -cpu0.regs.SS_230_m3 ORCALUT4 Z Out 1.017 17.435 -SS_230_i1_mux Net - - - - 1cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.435 -cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 18.980 -SS_cry[7] Net - - - - 1cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.980 -cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 19.122 -SS_cry[9] Net - - - - 1cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 19.122 -cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.265 -SS_cry[11] Net - - - - 1cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 19.265 -cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 19.408 -SS_cry[13] Net - - - - 1cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.408 -cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.957 -SS_s[15] Net - - - - 1cpu0.regs.SS[15] FD1P3AX D In 0.000 20.957 -===========================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 580 of 6864 (8%)PIC Latch: 0I/O cells: 69Block Rams : 10 of 26 (38%)Details:BB: 8CCU2D: 186DP8KC: 10FD1P3AX: 529FD1P3DX: 6FD1S3AX: 32FD1S3IX: 3GSR: 1IB: 1INV: 20L6MUX21: 16OB: 60OFS1P3DX: 9OFS1P3IX: 1ORCALUT4: 2014PFUMX: 226PUR: 1VHI: 14VLO: 20false: 1true: 7Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)Process took 0h:00m:30s realtime, 0h:00m:17s cputime# Thu Feb 6 15:35:11 2014###########################################################]Synthesis exit by 0.edif2ngd -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"edif2ngd: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...On or above line 300 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property is_pwr found - ignoring...On or above line 308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 1768 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 3762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 3915 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 4480 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 4636 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 8836 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 10966 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 13581 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 14376 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 15093 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 16549 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 17247 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 18117 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 18865 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 22005 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 32810 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 35408 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 38078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 38496 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 43706 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...On or above line 44658 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.ediWriting the design to P6809_P6809.ngo...ngdbuild -a "MachXO2" -d LCMXO2-7000HE -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "P6809_P6809.ngo" "P6809_P6809.ngd"ngdbuild: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Reading 'P6809_P6809.ngo' ...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...Running DRC...WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0_0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SU_cry_0_COUT[14]' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SS_cry_0_COUT[14]' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/regs/right_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S0' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S1' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_cry_10_0_COUT' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S0' has no loadWARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S1' has no loadWARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_COUT[5]' has no loadWARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_S0[0]' has no loadWARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_COUT[5]' has no loadWARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_S0[0]' has no loadWARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_COUT[9]' has no loadWARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_S0[0]' has no loadWARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_COUT[5]' has no loadWARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_S1[5]' has no loadWARNING - ngdbuild: logical net 'textctrl/blink_cnt_cry_0_S0[0]' has no loadWARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_COUT[9]' has no loadWARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_cry_0_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no loadWARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no loadWARNING - ngdbuild: DRC complete with 86 warningsDesign Results:3156 blocks expandedcomplete the first expansionWriting 'P6809_P6809.ngd' ...map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0map: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Process the file: P6809_P6809.ngdPicdevice="LCMXO2-7000HE"Pictype="TQFP144"Picspeed=4Remove unused logicDo not produce over sized NCDs.Part used: LCMXO2-7000HETQFP144, Performance used: 4.WARNING - map: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf (46): Error in LOCATE COMP "wenh_o" SITE "68" ;: COMP "wenh_o" not found in design. Disbale this preference.WARNING - map: Preference parsing results: 1 semantic error detectedWARNING - map: There are errors in the preference file, "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf".Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Running general design DRC...Removing unused logic...Optimizing...5 CCU2 constant inputs absorbed.WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.WARNING - map: IO buffer missing for top level port data_io[15:0](15)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](14)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](13)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](12)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](11)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](10)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](9)...logic will be discarded.WARNING - map: IO buffer missing for top level port data_io[15:0](8)...logic will be discarded.WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.Design Summary:Number of registers: 580PFU registers: 570PIO registers: 10Number of SLICEs: 1208 out of 3432 (35%)SLICEs(logic/ROM): 858 out of 858 (100%)SLICEs(logic/ROM/RAM): 350 out of 2574 (14%)As RAM: 0 out of 2574 (0%)As Logic/ROM: 350 out of 2574 (14%)Number of logic LUT4s: 2034Number of distributed RAM: 0 (0 LUT4s)Number of ripple logic: 186 (372 LUT4s)Number of shift registers: 0Total number of LUT4s: 2406Number of PIO sites used: 69 + 4(JTAG) out of 115 (63%)Number of block RAMs: 10 out of 26 (38%)Number of GSRs: 1 out of 1 (100%)EFB used : NoJTAG used : NoReadback used : NoOscillator used : NoStartup used : NoPOR : OnBandgap : OnNumber of Power Controller: 0 out of 1 (0%)Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)Number of DCCA: 0 out of 8 (0%)Number of DCMA: 0 out of 2 (0%)Number of PLLs: 0 out of 2 (0%)Number of DQSDLLs: 0 out of 2 (0%)Number of CLKDIVC: 0 out of 4 (0%)Number of ECLKSYNCA: 0 out of 4 (0%)Number of ECLKBRIDGECS: 0 out of 2 (0%)Notes:-1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.Number of clocks: 1Net cpu_clkgen: 367 loads, 367 rising, 0 falling (Driver: PIO clk40_i )Number of Clock Enables: 37Net cpu0_we: 8 loads, 0 LSLICEsNet textctrl/video_en_RNIFLVI: 8 loads, 0 LSLICEsNet textctrl/N_75_i: 4 loads, 4 LSLICEsNet textctrl/y_cnte: 4 loads, 4 LSLICEsNet textctrl/N_76_i: 4 loads, 4 LSLICEsNet textctrl/N_4: 6 loads, 6 LSLICEsNet textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEsNet textctrl/line_cnte: 2 loads, 2 LSLICEsNet textctrl/vsync_cnt_0_sqmuxa: 4 loads, 4 LSLICEsNet un1_bios_en_0: 4 loads, 0 LSLICEsNet cpu0/k_new_pc26_1_i_RNI1GUPD: 3 loads, 3 LSLICEsNet cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEsNet cpu0/next_state_0_sqmuxa_4_RNIMOT3B: 3 loads, 3 LSLICEsNet cpu0/G_9: 80 loads, 80 LSLICEsNet cpu0/k_ofshi_1_sqmuxa_RNIHOKL: 4 loads, 4 LSLICEsNet cpu0/k_pp_regs60_RNI18KD3: 4 loads, 4 LSLICEsNet cpu0/state82_RNI5IM34: 4 loads, 4 LSLICEsNet cpu0/k_memhi_0_sqmuxa_RNIN4F02: 4 loads, 4 LSLICEsNet cpu0/un1_state_23_1_RNI2Q3P1: 4 loads, 4 LSLICEsNet cpu0/PC_1_sqmuxa_2_RNIK4633: 37 loads, 37 LSLICEsNet cpu0/k_new_pc28_RNILK8D5: 4 loads, 4 LSLICEsNet cpu0/regs/cff_1_sqmuxa_2_RNI1FDN: 18 loads, 18 LSLICEsNet cpu0/regs/eflag_0_sqmuxa_0_RNIOVLR: 4 loads, 4 LSLICEsNet cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1: 25 loads, 25 LSLICEsNet cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3: 25 loads, 25 LSLICEsNet cpu0/regs/DP_1_sqmuxa_1_1_0_RNIIANF1: 9 loads, 9 LSLICEsNet cpu0/regs/ACCB_0_sqmuxa_1_RNILJP21: 9 loads, 9 LSLICEsNet cpu0/regs/ACCB22_RNIDCT43: 4 loads, 4 LSLICEsNet cpu0/un1_state_85_RNI07AH3: 2 loads, 2 LSLICEsNet cpu0/un1_state_18_2_RNINGR01: 4 loads, 4 LSLICEsNet cpu0/un1_state_7_3_RNIREBA3: 8 loads, 8 LSLICEsNet cpu0/state_3_sqmuxa_5_RNIE8SO9: 8 loads, 8 LSLICEsNet cpu0/un1_state_75_RNISTJ21: 2 loads, 2 LSLICEsNet cpu0/un1_state_21_RNI6VAF: 4 loads, 4 LSLICEsNet cpu0/k_new_pc29_RNILU7S1: 4 loads, 4 LSLICEsNet cpu0/un1_state_101_RNI9RM81: 2 loads, 2 LSLICEsNet cpu0/k_mem_dest_RNO[0]: 1 loads, 1 LSLICEsNumber of local set/reset loads for net reset_o_c merged into GSR: 6Number of LSRs: 2Net reset_cnt[0]: 1 loads, 1 LSLICEsNet textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEsNumber of nets driven by tri-state buffers: 0Top 10 highest fanout non-clock nets:Net cpu0/G_9: 93 loadsNet state_o_c[5]: 85 loadsNet state_o_c[4]: 79 loadsNet state_o_c[1]: 78 loadsNet cpu0/use_s_1: 75 loadsNet state_o_c[2]: 73 loadsNet cpu0/alu/rop_in[1]: 72 loadsNet state_o_c[3]: 69 loadsNet cpu0/alu/rop_in[0]: 67 loadsNet cpu0/k_opcode[3]: 59 loadsNumber of warnings: 22Number of errors: 0Total CPU Time: 1 secsTotal REAL Time: 5 secsPeak Memory Usage: 196 MBDumping design to file P6809_P6809_map.ncd.trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"trce: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Loading design for application trce from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Setup and Hold Report--------------------------------------------------------------------------------Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:35:22 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,4Report level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Setup):---------------Timing errors: 198 Score: 60114Cumulative negative slack: 60114Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)--------------------------------------------------------------------------------Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:35:22 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prfDesign file: P6809_P6809_map.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,MReport level: verbose report, limited to 1 item per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Hold):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)Timing summary (Setup and Hold):---------------Timing errors: 198 (setup), 0 (hold)Score: 60114 (setup), 0 (hold)Cumulative negative slack: 60114 (60114+0)----------------------------------------------------------------------------------------------------------------------------------------------------------------Total time: 3 secsmpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"---- MParTrce Tool ----Removing old design directory at request of -rem command line option to this program.WARNING - mpartrce: Unable to remove old design directory.Running par. Please wait . . .Lattice Place and Route Report for Design "P6809_P6809_map.ncd"Thu Feb 6 15:35:23 2014PAR: Place And Route Diamond (64-bit) 2.2.0.101.Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prfPreference file: P6809_P6809.prf.Placement level-cost: 5-1.Routing Iterations: 6Loading design for application par from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4License checked out.Ignore Preference Error(s): TrueDevice utilization summary:PIO (prelim) 69+4(JTAG)/336 20% used69+4(JTAG)/115 60% bondedIOLOGIC 10/336 2% usedSLICE 1208/3432 35% usedGSR 1/1 100% usedEBR 10/26 38% usedINFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.Number of Signals: 2917Number of Connections: 9622Pin Constraint Summary:68 out of 68 pins locked (100% locked).The following 1 signal is selected to use the primary clock routing resources:cpu_clkgen (driver: clk40_i, clk load #: 367)The following 6 signals are selected to use the secondary clock routing resources:cpu0/G_9 (driver: cpu0/SLICE_764, clk load #: 0, sr load #: 0, ce load #: 80)cpu0/PC_1_sqmuxa_2_RNIK4633 (driver: cpu0/regs/SLICE_982, clk load #: 0, sr load #: 0, ce load #: 37)cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1 (driver: cpu0/regs/SLICE_322, clk load #: 0, sr load #: 0, ce load #: 25)cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3 (driver: cpu0/regs/SLICE_927, clk load #: 0, sr load #: 0, ce load #: 25)cpu0/regs/cff_1_sqmuxa_2_RNI1FDN (driver: cpu0/regs/SLICE_1258, clk load #: 0, sr load #: 0, ce load #: 18)cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_754, clk load #: 0, sr load #: 0, ce load #: 16)Signal reset_o_c is selected as Global Set/Reset..Starting Placer Phase 0............Finished Placer Phase 0. REAL time: 9 secsStarting Placer Phase 1..........................Placer score = 922601.Finished Placer Phase 1. REAL time: 20 secsStarting Placer Phase 2..Placer score = 906811Finished Placer Phase 2. REAL time: 21 secs------------------ Clock Report ------------------Global Clock Resources:CLK_PIN : 1 out of 8 (12%)PLL : 0 out of 2 (0%)DCM : 0 out of 2 (0%)DCC : 0 out of 8 (0%)Quadrants All (TL, TR, BL, BR) - Global Clocks:PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 367SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_754" on site "R14C18D", clk load = 0, ce load = 16, sr load = 0SECONDARY "cpu0/G_9" from F0 on comp "cpu0/SLICE_764" on site "R21C18A", clk load = 0, ce load = 80, sr load = 0SECONDARY "cpu0/PC_1_sqmuxa_2_RNIK4633" from F0 on comp "cpu0/regs/SLICE_982" on site "R14C20A", clk load = 0, ce load = 37, sr load = 0SECONDARY "cpu0/regs/cff_1_sqmuxa_2_RNI1FDN" from F1 on comp "cpu0/regs/SLICE_1258" on site "R21C18C", clk load = 0, ce load = 18, sr load = 0SECONDARY "cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1" from F1 on comp "cpu0/regs/SLICE_322" on site "R14C20C", clk load = 0, ce load = 25, sr load = 0SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3" from F1 on comp "cpu0/regs/SLICE_927" on site "R14C20B", clk load = 0, ce load = 25, sr load = 0PRIMARY : 1 out of 8 (12%)SECONDARY: 6 out of 8 (75%)Edge Clocks:No edge clock selected.--------------- End of Clock Report ---------------I/O Usage Summary (final):69 out of 336 (20.5%) PIO sites used.69 out of 115 (60.0%) bonded PIO sites used.Number of PIO comps: 69; differential: 0Number of Vref pins used: 0I/O Bank Usage Summary:+----------+----------------+------------+-----------+| I/O Bank | Usage | Bank Vccio | Bank Vref |+----------+----------------+------------+-----------+| 0 | 11 / 28 ( 39%) | 2.5V | - || 1 | 13 / 29 ( 44%) | 2.5V | - || 2 | 20 / 29 ( 68%) | 2.5V | - || 3 | 8 / 9 ( 88%) | 2.5V | - || 4 | 7 / 10 ( 70%) | 2.5V | - || 5 | 10 / 10 (100%) | 2.5V | - |+----------+----------------+------------+-----------+Total placer CPU time: 15 secsDumping design to file P6809_P6809.dir/5_1.ncd.0 connections routed; 9622 unrouted.Starting router resource preassignmentCompleted router resource preassignment. Real time: 26 secsStart NBR router at Thu Feb 06 15:35:49 CET 2014*****************************************************************Info: NBR allows conflicts(one node used by more than one signal)in the earlier iterations. In each iteration, it tries tosolve the conflicts while keeping the critical connectionsrouted as short as possible. The routing process is said tobe completed when no conflicts exist and all connectionsare routed.Note: NBR uses a different method to calculate timing slacks. Theworst slack and total negative slack may not be the same asthat in TRCE report. You should always run TRCE to verifyyour design. Thanks.*****************************************************************Start NBR special constraint process at Thu Feb 06 15:35:49 CET 2014Start NBR section for initial routingLevel 1, iteration 1104(0.03%) conflicts; 8076(83.93%) untouched conns; 0 (nbr) score;Estimated worst slack/total negative slack: 0.246ns/0.000ns; real time: 29 secsLevel 2, iteration 175(0.02%) conflicts; 7564(78.61%) untouched conns; 0 (nbr) score;Estimated worst slack/total negative slack: 0.101ns/0.000ns; real time: 30 secsLevel 3, iteration 180(0.02%) conflicts; 6340(65.89%) untouched conns; 0 (nbr) score;Estimated worst slack/total negative slack: 0.302ns/0.000ns; real time: 31 secsLevel 4, iteration 1428(0.11%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.257ns/0.000ns; real time: 34 secsInfo: Initial congestion level at 75% usage is 3Info: Initial congestion area at 75% usage is 41 (4.10%)Start NBR section for normal routingLevel 1, iteration 111(0.00%) conflicts; 624(6.49%) untouched conns; 0 (nbr) score;Estimated worst slack/total negative slack: 0.167ns/0.000ns; real time: 35 secsLevel 4, iteration 1131(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 37 secsLevel 4, iteration 262(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secsLevel 4, iteration 324(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secsLevel 4, iteration 413(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secsLevel 4, iteration 55(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secsLevel 4, iteration 63(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secsLevel 4, iteration 72(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secsLevel 4, iteration 80(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secsStart NBR section for re-routingLevel 4, iteration 10(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secsStart NBR section for post-routingEnd NBR router with 0 unrouted connectionNBR Summary-----------Number of unrouted connections : 0 (0.00%)Number of connections with timing violations : 0 (0.00%)Estimated worst slack : 0.251nsTiming score : 0-----------Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.Hold time optimization iteration 0:All hold time violations have been successfully corrected in speed grade MTotal CPU time 31 secsTotal REAL time: 47 secsCompletely routed.End of route. 9622 routed (100.00%); 0 unrouted.Checking DRC ...No errors found.Hold time timing score: 0, hold timing errors: 0Timing score: 0Dumping design to file P6809_P6809.dir/5_1.ncd.PAR_SUMMARY::Run status = completedPAR_SUMMARY::Number of unrouted conns = 0PAR_SUMMARY::Worst slack<setup/<ns>> = 0.251PAR_SUMMARY::Timing score<setup/<ns>> = 0.000PAR_SUMMARY::Worst slack<hold /<ns>> = 0.217PAR_SUMMARY::Timing score<hold /<ns>> = 0.000Total CPU time to completion: 32 secsTotal REAL time to completion: 48 secspar done!Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Exiting par with exit code 0Exiting mpartrce with exit code 0trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"trce: version Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Loading design for application trce from file P6809_P6809.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Setup and Hold Report--------------------------------------------------------------------------------Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:36:11 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prfDesign file: P6809_P6809.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,4Report level: verbose report, limited to 10 items per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Setup):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)--------------------------------------------------------------------------------Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101Thu Feb 6 15:36:12 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prfDesign file: P6809_P6809.ncdPreference file: P6809_P6809.prfDevice,speed: LCMXO2-7000HE,mReport level: verbose report, limited to 10 items per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Hold):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)Timing summary (Setup and Hold):---------------Timing errors: 0 (setup), 0 (hold)Score: 0 (setup), 0 (hold)Cumulative negative slack: 0 (0+0)----------------------------------------------------------------------------------------------------------------------------------------------------------------Total time: 0 secsbitgen -f "P6809_P6809.t2b" -w "P6809_P6809.ncd" -jedec "P6809_P6809.prf"BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.Loading design for application Bitgen from file P6809_P6809.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Running DRC.INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.DRC detected 0 errors and 0 warnings.Reading Preference File from P6809_P6809.prf...Preference Summary:+---------------------------------+---------------------------------+| Preference | Current Setting |+---------------------------------+---------------------------------+| RamCfg | Reset** |+---------------------------------+---------------------------------+| MCCLK_FREQ | 2.08** |+---------------------------------+---------------------------------+| CONFIG_SECURE | OFF** |+---------------------------------+---------------------------------+| JTAG_PORT | ENABLE** |+---------------------------------+---------------------------------+| SDM_PORT | DISABLE** |+---------------------------------+---------------------------------+| SLAVE_SPI_PORT | DISABLE** |+---------------------------------+---------------------------------+| MASTER_SPI_PORT | DISABLE** |+---------------------------------+---------------------------------+| I2C_PORT | DISABLE** |+---------------------------------+---------------------------------+| MUX_CONFIGURATION_PORTS | DISABLE** |+---------------------------------+---------------------------------+| CONFIGURATION | CFG** |+---------------------------------+---------------------------------+| COMPRESS_CONFIG | ON** |+---------------------------------+---------------------------------+| MY_ASSP | OFF** |+---------------------------------+---------------------------------+| ONE_TIME_PROGRAM | OFF** |+---------------------------------+---------------------------------+| ENABLE_TRANSFR | DISABLE** |+---------------------------------+---------------------------------+| SHAREDEBRINIT | DISABLE** |+---------------------------------+---------------------------------+* Default setting.** The specified setting matches the default setting.Creating bit map...Bitstream Status: Final Version 1.83Saving bit stream in "P6809_P6809.jed".===========UFM Summary===========UFM Size: 2046 Pages (128*2046 Bits)UFM Utilization: General Purpose Flash MemoryAvailable General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)Initialized UFM Pages: 0 Page
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