URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [automake.log] - Rev 12
Compare with Previous | Blame | View Log
synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"Copyright (C) 1992-2014 Lattice Semiconductor Corporation. All rights reserved.Lattice Diamond Version 3.1.0.96==contents of P6809_P6809.srf#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013#install: C:\lscc\diamond\3.1_x64\synpbase#OS: Windows 7 6.1#Hostname: ALE-PC#Implementation: P6809$ Start of Compile#Sun Jul 06 07:46:25 2014Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013@N|Running in 64-bit modeCopyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"Verilog syntax check successful!File C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v changed - recompilingSelecting top level module CC3_top@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":66:7:66:12|Synthesizing module logic8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":89:7:89:12|Synthesizing module arith8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":162:7:162:12|Synthesizing module shift8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":202:7:202:10|Synthesizing module alu8@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":323:0:323:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:12:239:13|No assignment to n8@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:20:239:21|No assignment to z8@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":133:7:133:13|Synthesizing module arith16@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":329:7:329:11|Synthesizing module alu16@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":155:7:155:15|Synthesizing module decode_op@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":286:7:286:15|Synthesizing module decode_ea@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":312:7:312:16|Synthesizing module decode_alu@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":385:7:385:20|Synthesizing module test_condition@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":456:6:456:13|Ignoring system task $display@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1125:0:1125:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:23|No assignment to wire alu8_o_result@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":71:11:71:20|No assignment to wire alu8_o_CCR@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_indirect_loaded -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit k_mem_dest[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[2] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 2 to 1 of next_mem_state[5:0]@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bit 1 of k_mem_dest[1:0]@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 5 to 3 of next_push_state[5:0]@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":389:18:389:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":314:18:314:26|Input port bits 5 to 4 of postbyte0[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":287:18:287:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":333:18:333:20|Input port bits 7 to 4 of CCR[7:0] are unused@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":206:18:206:20|Input port bits 3 to 2 of CCR[7:0] are unused@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":203:12:203:17|Input clk_in is unused@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":164:18:164:21|Input b_in is unused@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]@ENDAt c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 99MB)Process took 0h:00m:02s realtime, 0h:00m:02s cputime# Sun Jul 06 07:46:27 2014###########################################################]Premap ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rptPrinting clock summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)syn_allowed_resources : blockrams=26 set on top level netlist CC3_topClock Summary**************Start Requested Requested Clock ClockClock Frequency Period Type Group--------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0====================================================================================================================@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 146MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Sun Jul 06 07:46:29 2014###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.Product Version I-2013.09LMapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabledDesign Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)Available hyper_sources - for debug and ip modelsNone FoundFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputsFinished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB)@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputsFinished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 170MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 177MB)@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":616:12:617:75|Pipelining module pipe0_1[11:0]@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe0[11:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe1[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rop_in[4:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register ra_in[15:0] pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Register reg_n_in pushed in.@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rb_in[15:0] pushed in.@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":145:35:145:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_i_m2[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":146:35:146:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2_i_m2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":288:2:288:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.k_new_pc_2[15:0] from cpu0.un1_regs_o_pc[15:0]Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 164MB peak: 177MB)Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 164MB peak: 177MB)Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 246MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------------------------------------------------------------------Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 182MB peak: 246MB)@N: FX164 |The option to pack flops in the IOB has not been specifiedFinished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 183MB peak: 246MB)#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 505 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)301 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk40_i port 505 cpu_clk=======================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 185MB peak: 246MB)Writing EDIF Netlist and constraint files@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated@W: MT558 |Unable to locate source for clock CC3_top|cpu_clk_derived_clock. Clock will not be forward annotatedI-2013.09L@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 189MB peak: 246MB)@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"##### START OF TIMING REPORT #####[# Timing Report written on Sun Jul 06 07:46:48 2014#Top view: CC3_topRequested Frequency: 1.0 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: 979.573Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i 1.0 MHz 49.0 MHz 1000.000 20.427 979.573 inferred Inferred_clkgroup_0========================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise--------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack--------------------------------------------------------------------------------------------------------------------------CC3_top|clk40_i CC3_top|clk40_i | 1000.000 979.573 | No paths - | No paths - | No paths -==========================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: CC3_top|clk40_i====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock------------------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.228 979.573cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.228 979.716cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.228 979.716cpu0.k_opcode[6] CC3_top|clk40_i FD1P3AX Q k_opcode[6] 1.347 979.827cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.339 979.836cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.232 979.855cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.228 979.859cpu0.alu.rb_in_pipe_2 CC3_top|clk40_i FD1P3AX Q rb_in_pipe_2 1.268 979.883cpu0.k_opcode[3] CC3_top|clk40_i FD1P3AX Q k_opcode[3] 1.369 979.909cpu0.k_opcode[2] CC3_top|clk40_i FD1P3AX Q k_opcode[2] 1.368 979.911======================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 979.573cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 979.573cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 979.573cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 979.573cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.716cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.716cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.716cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.716cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 979.859cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.859==============================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 1000.000- Setup time: 0.106+ Clock delay at ending point: 0.000 (ideal)= Required time: 999.894- Propagation time: 20.321- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : 979.573Number of logic level(s): 22Starting point: cpu0.alu.rb_in[0] / QEnding point: cpu0.regs.SS[15] / DThe start point is clocked by CC3_top|clk40_i [rising] on pin CKThe end point is clocked by CC3_top|clk40_i [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)----------------------------------------------------------------------------------------------------------------cpu0.alu.rb_in[0] FD1P3AX Q Out 1.228 1.228 -rb_in[0] Net - - - - 9cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.228 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.796 -rb_in_i[0] Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.796 -cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.545 3.340 -un8_q_out_cry_0 Net - - - - 1cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.340 -cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.889 -un8_q_out[2] Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.889 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.906 -q_out_2_i_m2_cry_1_0_RNO_0 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D C1 In 0.000 5.906 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D COUT Out 1.545 7.451 -q_out_2_i_m2_cry_2 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D CIN In 0.000 7.451 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D COUT Out 0.143 7.593 -q_out_2_i_m2_cry_4 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D CIN In 0.000 7.593 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D COUT Out 0.143 7.736 -q_out_2_i_m2_cry_6 Net - - - - 1cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D CIN In 0.000 7.736 -cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D S0 Out 1.549 9.285 -N_186 Net - - - - 1cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.285 -cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.438 -arith_q[7] Net - - - - 3cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.438 -cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.455 -N_63 Net - - - - 1cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.455 -cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.741 -q16_out[7] Net - - - - 2cpu0.alu.q_out[7] ORCALUT4 B In 0.000 11.741 -cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 12.190 -alu_o_result[7] Net - - - - 1cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX ALUT In 0.000 12.190 -cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX Z Out 0.286 12.476 -datamux_o_dest[7] Net - - - - 2cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 B In 0.000 12.476 -cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 Z Out 1.273 13.749 -left_1[7] Net - - - - 9cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 13.749 -cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 14.766 -N_252 Net - - - - 1cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 14.766 -cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 15.782 -SS_16[7] Net - - - - 1cpu0.regs.SS_222_m3 ORCALUT4 B In 0.000 15.782 -cpu0.regs.SS_222_m3 ORCALUT4 Z Out 1.017 16.799 -SS_222_i1_mux Net - - - - 1cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 16.799 -cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.545 18.344 -SS_cry[7] Net - - - - 1cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.344 -cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 18.486 -SS_cry[9] Net - - - - 1cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 18.486 -cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 18.629 -SS_cry[11] Net - - - - 1cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 18.629 -cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 18.772 -SS_cry[13] Net - - - - 1cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 18.772 -cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.321 -SS_s[15] Net - - - - 1cpu0.regs.SS[15] FD1P3AX D In 0.000 20.321 -================================================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lcmxo2_7000he-4Register bits: 489 of 6864 (7%)PIC Latch: 0I/O cells: 69Block Rams : 10 of 26 (38%)Details:BB: 8CCU2D: 183DP8KC: 10FD1P3AX: 438FD1P3DX: 6FD1S3AX: 33FD1S3IX: 2GSR: 1IB: 1INV: 12L6MUX21: 30OB: 60OFS1P3DX: 9OFS1P3IX: 1ORCALUT4: 2078PFUMX: 239PUR: 1VHI: 14VLO: 20false: 1true: 7Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 58MB peak: 246MB)Process took 0h:00m:18s realtime, 0h:00m:17s cputime# Sun Jul 06 07:46:48 2014###########################################################]Synthesis exit by 0.edif2ngd -l "MachXO2" -d LCMXO2-7000HE -path "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809" -path "C:/02_Elektronik/020_V6809/trunk/syn/lattice" "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"edif2ngd: version Diamond (64-bit) 3.1.0.96Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Writing the design to P6809_P6809.ngo...Total CPU Time: 0 secsTotal REAL Time: 0 secsngdbuild -a "MachXO2" -d LCMXO2-7000HE -p "C:/lscc/diamond/3.1_x64/ispfpga/xo2c00/data" -p "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809" -p "C:/02_Elektronik/020_V6809/trunk/syn/lattice" "P6809_P6809.ngo" "P6809_P6809.ngd"ngdbuild: version Diamond (64-bit) 3.1.0.96Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Reading 'P6809_P6809.ngo' ...Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00/data/xo2clib.ngl'...Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/mg5g00/data/mg5glib.ngl'...Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/or5g00/data/orc5glib.ngl'...Running DRC...<postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0_0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_1_i_m2_cry_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_1_i_m2_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_2_i_m2_cry_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/a16/q_out_2_i_m2_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/a8/un9_q_out_cry_7_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/ea_reg_post_o_s_15_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/eamem_addr_o_s_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/eamem_addr_o_s_15_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/eamem_addr_o_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/ea/eamem_addr_o_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/k_new_pc_2_s_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/k_new_pc_2_s_15_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/k_new_pc_2_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu16/k_new_pc_2_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/neg8_w_s_7_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/neg8_w_s_7_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/neg8_w_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/neg8_w_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/un5_daa_p0_r_1_cry_5_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/un5_daa_p0_r_1_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/alu8/un5_daa_p0_r_1_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_6_cry_8_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_6_cry_8_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_6_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_6_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_0_cry_14_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_0_cry_5_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe1_1_0_cry_5_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_s_11_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_s_11_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_cry_0_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_4_cry_8_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_4_cry_1_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_4_cry_1_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_5_cry_8_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_5_cry_1_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/alu/mulu/pipe0_1_5_cry_1_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SU_cry_0_COUT[14]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SU_lcry_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SU_lcry_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SS_cry_0_COUT[14]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SS_lcry_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/SS_lcry_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/right_s_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/right_s_15_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/regs/right_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_5_s_6_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_5_s_6_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_5_cry_1_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_5_cry_1_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_4_cry_7_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_4_cry_2_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_4_cry_2_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_cry_10_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_cry_5_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/yptr_cry_5_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/x_cnt_cry_0_COUT[5]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/x_cnt_cry_0_S0[0]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/y_cnt_cry_0_COUT[5]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/y_cnt_cry_0_S0[0]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/vsync_cnt_cry_0_COUT[9]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/vsync_cnt_cry_0_S0[0]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/blink_cnt_s_0_COUT[5]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/blink_cnt_s_0_S1[5]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/blink_cnt_cry_0_S0[0]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/hsync_cnt_cry_0_COUT[9]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="textctrl/hsync_cnt_cry_0_S0[0]" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/un1_k_cpu_addr_1_s_15_0_COUT" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/un1_k_cpu_addr_1_s_15_0_S1" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/un1_k_cpu_addr_1_cry_0_0_S0" /><postMsg mid="1166052" type="Warning" dynamic="2" navigation="0" arg0="logical" arg1="cpu0/un1_k_cpu_addr_1_cry_0_0_S1" /><postMsg mid="1163101" type="Warning" dynamic="1" navigation="0" arg0="85" />Design Results:3145 blocks expandedcomplete the first expansionWriting 'P6809_P6809.ngd' ...Total CPU Time: 0 secsTotal REAL Time: 0 secsmap -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf" -c 0map: version Diamond (64-bit) 3.1.0.96Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Process the file: P6809_P6809.ngdPicdevice="LCMXO2-7000HE"Pictype="TQFP144"Picspeed=4Remove unused logicDo not produce over sized NCDs.Part used: LCMXO2-7000HETQFP144, Performance used: 4.<postMsg mid="1100523" type="Warning" dynamic="2" navigation="2" arg0="C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf(94): Semantic error in "FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;": " arg1="cpu_clkgen matches no clock nets in the design. " arg2="C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf" arg3="94" /><postMsg mid="1100679" type="Warning" dynamic="2" navigation="2" arg0="C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf(46): Semantic error in "LOCATE COMP "wenh_o" SITE "68" ;": " arg1="wenh_o" arg2="C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf" arg3="46" /><postMsg mid="1104062" type="Warning" dynamic="2" navigation="0" arg0="" arg1="2 semantic errors" />Loading device for application map from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.Package Status: Final Version 1.36Running general design DRC...Removing unused logic...Optimizing...5 CCU2 constant inputs absorbed.<postMsg mid="51001030" type="Warning" dynamic="1" navigation="0" arg0="reset_o_c" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](15)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](14)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](13)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](12)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](11)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](10)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](9)" /><postMsg mid="51001046" type="Warning" dynamic="1" navigation="0" arg0="data_io[15:0](8)" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/chars/textmem4k_0_0_3" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/chars/textmem4k_0_1_2" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/chars/textmem4k_0_2_1" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/chars/textmem4k_0_3_0" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/font/fontrom_0_0_3" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/font/fontrom_0_1_2" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/font/fontrom_0_2_1" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="textctrl/font/fontrom_0_3_0" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="bios/bios2k_0_1_0" /><postMsg mid="51001051" type="Warning" dynamic="1" navigation="0" arg0="bios/bios2k_0_0_1" />Design Summary:Number of registers: 489 out of 7209 (7%)PFU registers: 479 out of 6864 (7%)PIO registers: 10 out of 345 (3%)Number of SLICEs: 1234 out of 3432 (36%)SLICEs as Logic/ROM: 1234 out of 3432 (36%)SLICEs as RAM: 0 out of 2574 (0%)SLICEs as Carry: 183 out of 3432 (5%)Number of LUT4s: 2457 out of 6864 (36%)Number of logic LUTs: 2091Number of distributed RAM: 0 (0 LUT4s)Number of ripple logic: 183 (366 LUT4s)Number of shift registers: 0Number of PIO sites used: 69 + 4(JTAG) out of 115 (63%)Number of block RAMs: 10 out of 26 (38%)Number of GSRs: 1 out of 1 (100%)EFB used : NoJTAG used : NoReadback used : NoOscillator used : NoStartup used : NoPOR : OnBandgap : OnNumber of Power Controller: 0 out of 1 (0%)Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)Number of DCCA: 0 out of 8 (0%)Number of DCMA: 0 out of 2 (0%)Number of PLLs: 0 out of 2 (0%)Number of DQSDLLs: 0 out of 2 (0%)Number of CLKDIVC: 0 out of 4 (0%)Number of ECLKSYNCA: 0 out of 4 (0%)Number of ECLKBRIDGECS: 0 out of 2 (0%)Notes:-1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.Number of clocks: 1Net clk40_i_c: 318 loads, 318 rising, 0 falling (Driver: PIO clk40_i )Number of Clock Enables: 38Net cpu0_we: 8 loads, 0 LSLICEsNet textctrl/video_en_RNIFLVI: 8 loads, 0 LSLICEsNet textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEsNet textctrl/N_77_i: 4 loads, 4 LSLICEsNet textctrl/y_cnte: 4 loads, 4 LSLICEsNet textctrl/x_cnte: 4 loads, 4 LSLICEsNet textctrl/N_4: 6 loads, 6 LSLICEsNet textctrl/line_cnte: 2 loads, 2 LSLICEsNet textctrl/vsync_cnt_0_sqmuxa: 4 loads, 4 LSLICEsNet un1_bios_en_0: 4 loads, 0 LSLICEsNet cpu0/un1_dec_o_ea_ofs8_1_i_RNI5818M: 3 loads, 3 LSLICEsNet cpu0/k_ealo_cnv_0[0]: 17 loads, 17 LSLICEsNet cpu0/state57_RNIVE7GE[0]: 2 loads, 2 LSLICEsNet cpu0/un1_state_75_1_RNIFQ0HB: 4 loads, 4 LSLICEsNet cpu0/G_9: 111 loads, 111 LSLICEsNet cpu0/un1_next_state_2_sqmuxa_4_9_RNIH3541: 3 loads, 3 LSLICEsNet cpu0/un1_next_state_2_sqmuxa_2_RNI9IU0S: 2 loads, 2 LSLICEsNet cpu0/un1_state_53_RNIHGM19: 4 loads, 4 LSLICEsNet cpu0/k_new_pc27_RNILUNB8: 4 loads, 4 LSLICEsNet cpu0/k_ind_ea_1_sqmuxa_1_RNIDOOO1: 4 loads, 4 LSLICEsNet cpu0/un1_state_17_1_RNI0AA81: 4 loads, 4 LSLICEsNet cpu0/regs/cff_0_sqmuxa_1_i_o2_RNI101G: 1 loads, 1 LSLICEsNet cpu0/un1_state_18_RNIBNKS: 4 loads, 4 LSLICEsNet cpu0/k_cpu_we_3_RNIEO9N: 8 loads, 8 LSLICEsNet cpu0/regs/cff_0_sqmuxa_1_i_o2_RNITELD: 5 loads, 5 LSLICEsNet cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEsNet cpu0/regs/PC_0_sqmuxa_1_i_o2_RNIHDJD1: 16 loads, 16 LSLICEsNet cpu0/regs/IY_0_sqmuxa_i_a2_0_RNIK8531: 8 loads, 8 LSLICEsNet cpu0/regs/ACCB_1_sqmuxa_i_a2_1_RNI30EL1: 8 loads, 8 LSLICEsNet cpu0/regs/DP_0_sqmuxa_i_a2_1_RNIARVN: 4 loads, 4 LSLICEsNet cpu0/regs/ACCB_1_sqmuxa_i_a2_RNIAEJ01: 4 loads, 4 LSLICEsNet cpu0/regs/ACCB22_i_a2_RNIOV3S3: 4 loads, 4 LSLICEsNet cpu0/k_memhi_0_sqmuxa_RNIC8VU1: 4 loads, 4 LSLICEsNet cpu0/un1_state_71_RNIBU403: 2 loads, 2 LSLICEsNet cpu0/k_pp_regs_0_sqmuxa_2_RNIPNRUH: 8 loads, 8 LSLICEsNet cpu0/k_ofslo_cnv[0]: 4 loads, 4 LSLICEsNet cpu0/k_ofshi_cnv[0]: 4 loads, 4 LSLICEsNet cpu0/k_mem_dest_RNO[0]: 1 loads, 1 LSLICEsNumber of local set/reset loads for net reset_o_c merged into GSR: 6Number of LSRs: 1Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEsNumber of nets driven by tri-state buffers: 0Top 10 highest fanout non-clock nets:Net cpu0/G_9: 126 loadsNet state_o_c[1]: 84 loadsNet state_o_c[0]: 81 loadsNet state_o_c[5]: 80 loadsNet state_o_c[2]: 78 loadsNet cpu0/alu/rop_in[0]: 77 loadsNet cpu0/use_s_1: 77 loadsNet cpu0/alu/rop_in[1]: 74 loadsNet state_o_c[4]: 68 loadsNet cpu0/k_opcode[0]: 66 loads<postMsg mid="51001230" type="Warning" dynamic="1" navigation="0" arg0="C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809.lpf" />Number of warnings: 23Number of errors: 0Total CPU Time: 1 secsTotal REAL Time: 2 secsPeak Memory Usage: 75 MBDumping design to file P6809_P6809_map.ncd.ldbanno "P6809_P6809_map.ncd" -n Verilog -o "P6809_P6809_mapvo.vo" -w -negldbanno: version Diamond (64-bit) 3.1.0.96Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Writing a Verilog netlist using the orca library type based on the P6809_P6809_map design file.Loading design for application ldbanno from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application ldbanno from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Converting design "P6809_P6809_map.ncd" into .ldb format.Writing Verilog netlist to file P6809_P6809_mapvo.voWriting SDF timing to file P6809_P6809_mapvo.sdf<postMsg mid="35400250" type="Info" dynamic="1" navigation="0" arg0="0" />mpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"---- MParTrce Tool ----Removing old design directory at request of -rem command line option to this program.Running par. Please wait . . .Lattice Place and Route Report for Design "P6809_P6809_map.ncd"Sun Jul 06 07:47:00 2014PAR: Place And Route Diamond (64-bit) 3.1.0.96.Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prfPreference file: P6809_P6809.prf.Placement level-cost: 5-1.Routing Iterations: 6Loading design for application par from file P6809_P6809_map.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4License checked out.Ignore Preference Error(s): TrueDevice utilization summary:PIO (prelim) 69+4(JTAG)/336 22% used69+4(JTAG)/115 63% bondedIOLOGIC 10/336 2% usedSLICE 1234/3432 35% usedGSR 1/1 100% usedEBR 10/26 38% usedINFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.Number of Signals: 2876Number of Connections: 9723Pin Constraint Summary:68 out of 68 pins locked (100% locked).The following 1 signal is selected to use the primary clock routing resources:clk40_i_c (driver: clk40_i, clk load #: 318)The following 3 signals are selected to use the secondary clock routing resources:cpu0/G_9 (driver: cpu0/SLICE_837, clk load #: 0, sr load #: 0, ce load #: 111)cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_744, clk load #: 0, sr load #: 0, ce load #: 17)cpu0/regs/PC_0_sqmuxa_1_i_o2_RNIHDJD1 (driver: cpu0/regs/SLICE_887, clk load #: 0, sr load #: 0, ce load #: 16)Signal reset_o_c is selected as Global Set/Reset..Starting Placer Phase 0.............Finished Placer Phase 0. REAL time: 2 secsStarting Placer Phase 1.........................Placer score = 779607.Finished Placer Phase 1. REAL time: 6 secsStarting Placer Phase 2..Placer score = 774076Finished Placer Phase 2. REAL time: 7 secs------------------ Clock Report ------------------Global Clock Resources:CLK_PIN : 1 out of 8 (12%)PLL : 0 out of 2 (0%)DCM : 0 out of 2 (0%)DCC : 0 out of 8 (0%)Quadrants All (TL, TR, BL, BR) - Global Clocks:PRIMARY "clk40_i_c" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 318SECONDARY "cpu0/G_9" from F0 on comp "cpu0/SLICE_837" on site "R21C18A", clk load = 0, ce load = 111, sr load = 0SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_744" on site "R21C18B", clk load = 0, ce load = 17, sr load = 0SECONDARY "cpu0/regs/PC_0_sqmuxa_1_i_o2_RNIHDJD1" from F1 on comp "cpu0/regs/SLICE_887" on site "R14C20A", clk load = 0, ce load = 16, sr load = 0PRIMARY : 1 out of 8 (12%)SECONDARY: 3 out of 8 (37%)Edge Clocks:No edge clock selected.--------------- End of Clock Report ---------------I/O Usage Summary (final):69 + 4(JTAG) out of 336 (21.7%) PIO sites used.69 + 4(JTAG) out of 115 (63.5%) bonded PIO sites used.Number of PIO comps: 69; differential: 0Number of Vref pins used: 0I/O Bank Usage Summary:+----------+----------------+------------+-----------+| I/O Bank | Usage | Bank Vccio | Bank Vref |+----------+----------------+------------+-----------+| 0 | 11 / 28 ( 39%) | 2.5V | - || 1 | 13 / 29 ( 44%) | 2.5V | - || 2 | 20 / 29 ( 68%) | 2.5V | - || 3 | 8 / 9 ( 88%) | 2.5V | - || 4 | 7 / 10 ( 70%) | 2.5V | - || 5 | 10 / 10 (100%) | 2.5V | - |+----------+----------------+------------+-----------+Total placer CPU time: 6 secsDumping design to file P6809_P6809.dir/5_1.ncd.-----------------------------------------------------------------INFO - par: ASE feature is off due to non timing-driven settings.-----------------------------------------------------------------0 connections routed; 9723 unrouted.Starting router resource preassignmentCompleted router resource preassignment. Real time: 9 secsStart NBR router at 07:47:09 07/06/14*****************************************************************Info: NBR allows conflicts(one node used by more than one signal)in the earlier iterations. In each iteration, it tries tosolve the conflicts while keeping the critical connectionsrouted as short as possible. The routing process is said tobe completed when no conflicts exist and all connectionsare routed.Note: NBR uses a different method to calculate timing slacks. Theworst slack and total negative slack may not be the same asthat in TRCE report. You should always run TRCE to verifyyour design. Thanks.*****************************************************************Start NBR special constraint process at 07:47:09 07/06/14Start NBR section for initial routingLevel 4, iteration 1290(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secsInfo: Initial congestion level at 75% usage is 0Info: Initial congestion area at 75% usage is 5 (0.50%)Start NBR section for normal routingLevel 4, iteration 1125(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secsLevel 4, iteration 246(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secsLevel 4, iteration 317(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 411(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 58(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 64(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 72(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 82(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 91(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 102(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsLevel 4, iteration 110(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsStart NBR section for re-routingLevel 4, iteration 10(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secsStart NBR section for post-routingEnd NBR router with 0 unrouted connectionNBR Summary-----------Number of unrouted connections : 0 (0.00%)Number of connections with timing violations : 0 (0.00%)Estimated worst slack<setup> : <n/a>Timing score<setup> : 0-----------Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.Total CPU time 12 secsTotal REAL time: 12 secsCompletely routed.End of route. 9723 routed (100.00%); 0 unrouted.Checking DRC ...No errors found.Hold time timing score: 0, hold timing errors: 0Timing score: 0Dumping design to file P6809_P6809.dir/5_1.ncd.PAR_SUMMARY::Number of errors = 0Total CPU time to completion: 13 secsTotal REAL time to completion: 14 secspar done!Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Exiting par with exit code 0Exiting mpartrce with exit code 0trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"trce: version Diamond (64-bit) 3.1.0.96Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Loading design for application trce from file p6809_p6809.ncd.Design name: CC3_topNCD version: 3.2Vendor: LATTICEDevice: LCMXO2-7000HEPackage: TQFP144Performance: 4Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.Package Status: Final Version 1.36Performance Hardware Data Status: Final) Version 23.4Setup and Hold Report--------------------------------------------------------------------------------Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.1.0.96Sun Jul 06 07:47:15 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prfDesign file: p6809_p6809.ncdPreference file: p6809_p6809.prfDevice,speed: LCMXO2-7000HE,4Report level: verbose report, limited to 10 items per preference--------------------------------------------------------------------------------Report Type: based on TRACE automatically generated preferencesBLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Setup):---------------Timing errors: 4096 Score: 88089612Cumulative negative slack: 88089612Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)--------------------------------------------------------------------------------Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.1.0.96Sun Jul 06 07:47:16 2014Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.Copyright (c) 1995 AT&T Corp. All rights reserved.Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.Copyright (c) 2001 Agere Systems All rights reserved.Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.Report Information------------------Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prfDesign file: p6809_p6809.ncdPreference file: p6809_p6809.prfDevice,speed: LCMXO2-7000HE,mReport level: verbose report, limited to 10 items per preference--------------------------------------------------------------------------------BLOCK ASYNCPATHSBLOCK RESETPATHS--------------------------------------------------------------------------------Timing summary (Hold):---------------Timing errors: 0 Score: 0Cumulative negative slack: 0Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)Timing summary (Setup and Hold):---------------Timing errors: 4096 (setup), 0 (hold)Score: 88089612 (setup), 0 (hold)Cumulative negative slack: 88089612 (88089612+0)----------------------------------------------------------------------------------------------------------------------------------------------------------------Total time: 2 secs