Subversion Repositories 6809_6309_compatible_core

Starting process: Module

Starting process: 

SCUBA, Version Diamond_2.2_Production (99)
Thu Feb  6 15:31:10 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 8 -baddr_width 11 -widthb 8 -anum_words 2048 -bnum_words 2048 -cascade -1 -memfile /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e 
    Circuit name     : bios2k
    Module type      : RAM_DP_TRUE
    Module Version   : 7.2
    Ports            : 
        Inputs       : DataInA[7:0], DataInB[7:0], AddressA[10:0], AddressB[10:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
        Outputs      : QA[7:0], QB[7:0]
    I/O buffer       : not inserted
    Memory file      : /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem
    EDIF output      : suppressed
    Verilog output   : bios2k.v
    Verilog template : bios2k_tmpl.v
    Verilog testbench: tb_bios2k_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : bios2k.srp
    Estimated Resource Usage:
            EBR : 2

END   SCUBA Module Synthesis

File: bios2k.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0