URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [fontrom_generate.log] - Rev 8
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Starting process: Module
Starting process:
SCUBA, Version Diamond_2.2_Production (99)
Wed Jan 1 20:10:25 2014
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis
Issued command : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fontrom -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-7000HE -addr_width 12 -data_width 8 -num_words 4096 -cascade -1 -memfile font256x16l.mem -memformat orca -e
Circuit name : fontrom
Module type : EBR_ROM
Module Version : 5.1
Ports :
Inputs : Address[11:0], OutClock, OutClockEn, Reset
Outputs : Q[7:0]
I/O buffer : not inserted
Memory file : font256x16l.mem
EDIF output : suppressed
Verilog output : fontrom.v
Verilog template : fontrom_tmpl.v
Verilog testbench: tb_fontrom_tmpl.v
Verilog purpose : for synthesis and simulation
Bus notation : big endian
Report output : fontrom.srp
Estimated Resource Usage:
EBR : 4
END SCUBA Module Synthesis
File: fontrom.lpc created.
End process: completed successfully.
Total Warnings: 0
Total Errors: 0