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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 2.2.0.101.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Wed Dec 25 17:50:32 2013
/usr/local/diamond/2.2_x64/ispfpga/bin/lin64/par -f P6809_P6809.p2t
P6809_P6809_map.ncd P6809_P6809.dir P6809_P6809.prf
Preference file: P6809_P6809.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Time Status
---------- -------- ----- -------- ----- ------
5_1 * 0 -4.091 12558270 28 Complete
* : Design saved.
Total (real) run time for 1-seed: 28 secs
par done!
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
Wed Dec 25 17:50:32 2013
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
Preference file: P6809_P6809.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file P6809_P6809_map.ncd.
Design name: CC3_top
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HE
Package: TQFP144
Performance: 4
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
Package Status: Final Version 1.36
Performance Hardware Data Status: Final) Version 23.4
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 49+4(JTAG)/336 14% used
49+4(JTAG)/115 42% bonded
IOLOGIC 8/336 2% used
SLICE 1163/3432 33% used
GSR 1/1 100% used
EBR 2/26 7% used
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 2675
Number of Connections: 8924
Pin Constraint Summary:
49 out of 49 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
cpu_clkgen (driver: clk40_i, clk load #: 315)
The following 6 signals are selected to use the secondary clock routing resources:
cpu_clk (driver: SLICE_477, clk load #: 0, sr load #: 0, ce load #: 95)
cpu0/cff_1_sqmuxa_0_RNIL5DT (driver: cpu0/SLICE_865, clk load #: 0, sr load #: 0, ce load #: 43)
cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1 (driver: cpu0/regs/SLICE_829, clk load #: 0, sr load #: 0, ce load #: 12)
cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1 (driver: cpu0/regs/SLICE_830, clk load #: 0, sr load #: 0, ce load #: 12)
cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2 (driver: cpu0/regs/SLICE_887, clk load #: 0, sr load #: 0, ce load #: 12)
cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2 (driver: cpu0/regs/SLICE_886, clk load #: 0, sr load #: 0, ce load #: 12)
Signal cpu0.cpu_reset_i_2_i is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0. REAL time: 4 secs
Starting Placer Phase 1.
......................
Placer score = 808498.
Finished Placer Phase 1. REAL time: 12 secs
Starting Placer Phase 2.
.
Placer score = 797364
Finished Placer Phase 2. REAL time: 13 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
PLL : 0 out of 2 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 315
SECONDARY "cpu_clk" from Q0 on comp "SLICE_477" on site "R21C20B", clk load = 0, ce load = 95, sr load = 0
SECONDARY "cpu0/cff_1_sqmuxa_0_RNIL5DT" from F0 on comp "cpu0/SLICE_865" on site "R14C18A", clk load = 0, ce load = 43, sr load = 0
SECONDARY "cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1" from F1 on comp "cpu0/regs/SLICE_829" on site "R21C18C", clk load = 0, ce load = 12, sr load = 0
SECONDARY "cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1" from F1 on comp "cpu0/regs/SLICE_830" on site "R14C18D", clk load = 0, ce load = 12, sr load = 0
SECONDARY "cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2" from F0 on comp "cpu0/regs/SLICE_887" on site "R14C18B", clk load = 0, ce load = 12, sr load = 0
SECONDARY "cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2" from F0 on comp "cpu0/regs/SLICE_886" on site "R14C18C", clk load = 0, ce load = 12, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 6 out of 8 (75%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
49 out of 336 (14.6%) PIO sites used.
49 out of 115 (42.6%) bonded PIO sites used.
Number of PIO comps: 49; differential: 0
Number of Vref pins used: 0
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 12 / 28 ( 42%) | 2.5V | - |
| 1 | 13 / 29 ( 44%) | 2.5V | - |
| 2 | 23 / 29 ( 79%) | 2.5V | - |
| 3 | 1 / 9 ( 11%) | 2.5V | - |
| 4 | 0 / 10 ( 0%) | - | - |
| 5 | 0 / 10 ( 0%) | - | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 12 secs
Dumping design to file P6809_P6809.dir/5_1.ncd.
0 connections routed; 8924 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 16 secs
Start NBR router at Wed Dec 25 17:50:48 CET 2013
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design. Thanks.
*****************************************************************
Start NBR special constraint process at Wed Dec 25 17:50:48 CET 2013
Start NBR section for initial routing
Level 1, iteration 1
137(0.04%) conflicts; 7446(83.44%) untouched conns; 1425225 (nbr) score;
Estimated worst slack/total negative slack: -3.332ns/-1425.225ns; real time: 18 secs
Level 2, iteration 1
162(0.04%) conflicts; 6336(71.00%) untouched conns; 1178362 (nbr) score;
Estimated worst slack/total negative slack: -3.339ns/-1178.363ns; real time: 19 secs
Level 3, iteration 1
89(0.02%) conflicts; 5385(60.34%) untouched conns; 1500920 (nbr) score;
Estimated worst slack/total negative slack: -3.347ns/-1500.921ns; real time: 20 secs
Level 4, iteration 1
349(0.09%) conflicts; 0(0.00%) untouched conn; 1551317 (nbr) score;
Estimated worst slack/total negative slack: -3.425ns/-1551.318ns; real time: 21 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 5 (0.50%)
Start NBR section for normal routing
Level 1, iteration 1
88(0.02%) conflicts; 402(4.50%) untouched conns; 1210645 (nbr) score;
Estimated worst slack/total negative slack: -3.167ns/-1210.645ns; real time: 21 secs
Level 4, iteration 1
237(0.06%) conflicts; 0(0.00%) untouched conn; 1243629 (nbr) score;
Estimated worst slack/total negative slack: -3.155ns/-1243.630ns; real time: 22 secs
Level 4, iteration 2
131(0.03%) conflicts; 0(0.00%) untouched conn; 1252609 (nbr) score;
Estimated worst slack/total negative slack: -3.245ns/-1252.609ns; real time: 23 secs
Level 4, iteration 3
97(0.03%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score;
Estimated worst slack/total negative slack: -3.416ns/-1308.084ns; real time: 23 secs
Level 4, iteration 4
71(0.02%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score;
Estimated worst slack/total negative slack: -3.416ns/-1308.084ns; real time: 23 secs
Level 4, iteration 5
71(0.02%) conflicts; 0(0.00%) untouched conn; 1426563 (nbr) score;
Estimated worst slack/total negative slack: -3.558ns/-1426.563ns; real time: 24 secs
Level 4, iteration 6
50(0.01%) conflicts; 0(0.00%) untouched conn; 1426563 (nbr) score;
Estimated worst slack/total negative slack: -3.558ns/-1426.563ns; real time: 24 secs
Level 4, iteration 7
30(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1480.394ns; real time: 24 secs
Level 4, iteration 8
23(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1480.394ns; real time: 24 secs
Level 4, iteration 9
17(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs
Level 4, iteration 10
16(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs
Level 4, iteration 11
15(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score;
Estimated worst slack/total negative slack: -3.656ns/-1549.790ns; real time: 25 secs
Level 4, iteration 12
17(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score;
Estimated worst slack/total negative slack: -3.656ns/-1549.790ns; real time: 25 secs
Level 4, iteration 13
9(0.00%) conflicts; 0(0.00%) untouched conn; 1540315 (nbr) score;
Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs
Level 4, iteration 14
7(0.00%) conflicts; 0(0.00%) untouched conn; 1540315 (nbr) score;
Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs
Level 4, iteration 15
6(0.00%) conflicts; 0(0.00%) untouched conn; 1564368 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1564.369ns; real time: 25 secs
Level 4, iteration 16
6(0.00%) conflicts; 0(0.00%) untouched conn; 1564368 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1564.369ns; real time: 25 secs
Level 4, iteration 17
6(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score;
Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs
Level 4, iteration 18
7(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score;
Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs
Level 4, iteration 19
6(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1539.701ns; real time: 25 secs
Level 4, iteration 20
4(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score;
Estimated worst slack/total negative slack: -3.626ns/-1539.701ns; real time: 25 secs
Level 4, iteration 21
4(0.00%) conflicts; 0(0.00%) untouched conn; 1541625 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 25 secs
Level 4, iteration 22
2(0.00%) conflicts; 0(0.00%) untouched conn; 1541625 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 26 secs
Level 4, iteration 23
1(0.00%) conflict; 0(0.00%) untouched conn; 1553537 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs
Level 4, iteration 24
5(0.00%) conflicts; 0(0.00%) untouched conn; 1553537 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs
Level 4, iteration 25
3(0.00%) conflicts; 0(0.00%) untouched conn; 1631557 (nbr) score;
Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs
Level 4, iteration 26
1(0.00%) conflict; 0(0.00%) untouched conn; 1631557 (nbr) score;
Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs
Level 4, iteration 27
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 28
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 29
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 30
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 31
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 32
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 33
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Level 4, iteration 34
0(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
Start NBR section for performance tunning (iteration 1)
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 1791659 (nbr) score;
Estimated worst slack/total negative slack: -4.091ns/-1791.660ns; real time: 27 secs
Start NBR section for re-routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 1793776 (nbr) score;
Estimated worst slack/total negative slack: -4.091ns/-1793.777ns; real time: 27 secs
Start NBR section for post-routing
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 938 (10.51%)
Estimated worst slack : -4.091ns
Timing score : 12558270
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
------------------------------------------------------------------------------------------------------------------------------------
WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-4.091ns) is worse than the default value(0.000ns).
------------------------------------------------------------------------------------------------------------------------------------
Total CPU time 28 secs
Total REAL time: 28 secs
Completely routed.
End of route. 8924 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
Hold time timing score: 0, hold timing errors: 0
Timing score: 12558270
Dumping design to file P6809_P6809.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = -4.091
PAR_SUMMARY::Timing score<setup/<ns>> = 12558.270
PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
Total CPU time to completion: 28 secs
Total REAL time to completion: 28 secs
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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