OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [toplevel.ucf] - Rev 108

Go to most recent revision | Compare with Previous | Blame | View Log

#--------------------------------------------------------------------------------
#-- Copyright (C) 2004 Trenz Electronic GmbH
#-- www.trenz-electronic.de
#-- Author:      Kolja Sulimma
#--------------------------------------------------------------------------------
#-- Project:     TE-XC3S Application Note: Pong Demo
#-- File:        toplevel.ucf
#-- Description: Pin assignments for the Pong Demo
#-- History:     V1.0 2004-10-11 KS created
#--------------------------------------------------------------------------------
#-- This program is free software; you can redistribute it and/or
#-- modify it under the terms of the GNU General Public License
#-- as published by the Free Software Foundation; either version 2
#-- of the License, or (at your option) any later version.

#-- This program is distributed in the hope that it will be useful,
#-- but WITHOUT ANY WARRANTY; without even the implied warranty of
#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#-- GNU General Public License for more details.

#-- You should have received a copy of the GNU General Public License
#-- along with this program; if not, write to the Free Software
#-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.

#Reset
NET "reset_sw"    LOC = "R16" | PULLUP;

#led on micromodule
NET "mm_led"     LOC = "N6"  ;

#mandatory umti signals to get a clock
NET "utmi_clkout"      LOC = "D9"  ;
NET "utmi_databus16_8" LOC = "B14"  ;

#utmi signals only used with USB function
NET "utmi_opmode1"     LOC = "C6"  ;
NET "utmi_reset"       LOC = "B4"  ;
NET "utmi_termselect"  LOC = "B6"  ;
NET "utmi_txvalid"     LOC = "B12"  ;
NET "utmi_xcvrselect"  LOC = "D6"  ;

#vga output
NET "fpga_b<0>"  LOC = "M16" | DRIVE = 24 ;
NET "fpga_b<1>"  LOC = "M15" | DRIVE = 24 ;
NET "fpga_b<2>"  LOC = "M14" | DRIVE = 24 ;
NET "fpga_g<0>"  LOC = "N16" | DRIVE = 24 ;
NET "fpga_g<1>"  LOC = "M13" | DRIVE = 24 ;
NET "fpga_g<2>"  LOC = "L13" | DRIVE = 24 ;
NET "fpga_r<0>"  LOC = "P16" | DRIVE = 24 ;
NET "fpga_r<1>"  LOC = "N14" | DRIVE = 24 ;
NET "fpga_r<2>"  LOC = "N15" | DRIVE = 24 ;
NET "hsync_b"    LOC = "J13"  ;
NET "vsync_b"    LOC = "R1"  ;

#keyboard/mouse interfaces
NET "ps2_clk1"   LOC = "C1"  ;
#NET "ps2_clk2"   LOC = "B1"  ;
NET "ps2_data1"  LOC = "C2"  ;
#NET "ps2_data2"  LOC = "C3"  ;

#joystick and buttons
NET "joy_down"   LOC = "P15"  ;
NET "joy_fire"   LOC = "T14"  ;
NET "joy_left"   LOC = "K13"  ;
NET "joy_right"  LOC = "R13"  ;
NET "joy_up"     LOC = "P14"  ;

#leds on baseboard
NET "led<0>"     LOC = "T13"  ;
NET "led<1>"     LOC = "R12"  ;
NET "led<2>"     LOC = "T12"  ;
NET "led<3>"     LOC = "R11"  ;

#audio
NET "aud_out<1>" LOC = "D10";
NET "aud_out<2>" LOC = "E10";
NET "aud_out<3>" LOC = "D11";
NET "aud_out<4>" LOC = "D12";

#lcd
NET "lcd_d<3>"    LOC = "M1";
NET "lcd_d<2>"    LOC = "L4";
NET "lcd_d<1>"    LOC = "L5";
NET "lcd_d<0>"     LOC = "N1";
NET "lcd_e"               LOC = "N2";
NET "lcd_rw"      LOC = "N3";
NET "lcd_rs"      LOC = "P1";

#rs232
NET "fpga_cts"   LOC = "K12"  ;
NET "fpga_rts"   LOC = "E11"  ;
NET "fpga_rxd"   LOC = "L12"  ;
NET "fpga_txd"   LOC = "J14"  ;

#ram, flash
NET "ram_a<0>"   LOC = "D14"  ;
NET "ram_a<1>"   LOC = "K15"  ;
NET "ram_a<2>"   LOC = "M3"  ;
NET "ram_a<3>"   LOC = "L2"  ;
NET "ram_a<4>"   LOC = "L3"  ;
NET "ram_a<5>"   LOC = "K1"  ;
NET "ram_a<6>"   LOC = "K2"  ;
NET "ram_a<7>"   LOC = "J2"  ;
NET "ram_a<8>"   LOC = "J1"  ;
NET "ram_a<9>"   LOC = "G4"  ;
NET "ram_a<10>"  LOC = "F2"  ;
NET "ram_a<11>"  LOC = "F3"  ;
NET "ram_a<12>"  LOC = "E1"  ;
NET "ram_a<13>"  LOC = "E2"  ;
NET "ram_a<14>"  LOC = "E3"  ;
NET "ram_a<15>"  LOC = "D1"  ;
NET "ram_a<16>"  LOC = "D2"  ;
NET "ram_a<17>"  LOC = "B16"  ;
NET "ram_a<18>"  LOC = "H4"  ;
NET "ram_a<19>"  LOC = "H3";
NET "ram_a<20>"  LOC = "G3";
NET "ram_io<0>"  LOC = "H15"  ;
NET "ram_io<1>"  LOC = "H14"  ;
NET "ram_io<2>"  LOC = "G16"  ;
NET "ram_io<3>"  LOC = "G14"  ;
NET "ram_io<4>"  LOC = "F14"  ;
NET "ram_io<5>"  LOC = "E15"  ;
NET "ram_io<6>"  LOC = "D16"  ;
NET "ram_io<7>"  LOC = "E13"  ;
NET "ram_io<8>"  LOC = "H16"  ;
NET "ram_io<9>"  LOC = "H13"  ;
NET "ram_io<10>" LOC = "G15"  ;
NET "ram_io<11>" LOC = "F15"  ;
NET "ram_io<12>" LOC = "E16"  ;
NET "ram_io<13>" LOC = "E14"  ;
NET "ram_io<14>" LOC = "D15"  ;
NET "ram_io<15>" LOC = "C16"  ;
NET "ram_bhen"   LOC = "L14"  ;
NET "ram_blen"   LOC = "L15"  ;
NET "ram_cen"    LOC = "M2"  ;
NET "ram_oen"    LOC = "K16"  ;
NET "ram_wen"    LOC = "G1"  ;

#flash memory
NET "fl_resetn"  LOC = "G2" ;
NET "fl_cen"     LOC = "K14";
NET "fl_oen"     LOC = "J16";
NET "fl_byten"   LOC = "C15";
NET "fl_busyn"   LOC = "H1" ;

#compact flash
NET "cf_we"               LOC = "D8";
NET "cf_reg"      LOC = "G5";
NET "cf_cs0"      LOC = "D7";
NET "cf_cs1"      LOC = "D5";
NET "cf_reset"    LOC = "E6";
NET "cf_irq"      LOC = "E4" | PULLUP;
NET "cf_iord"     LOC = "F4";
NET "cf_iowr"     LOC = "F5";
NET "cf_wait"     LOC = "E7" | PULLUP;
NET "cf_dasp"     LOC = "J4" | PULLUP;
NET "cf_pdiag"    LOC = "J3" | PULLUP;
NET "cf_cd1"      LOC = "K5" | PULLUP;
NET "cf_cd2"      LOC = "K4" | PULLUP;
NET "iois16"      LOC = "K3" | PULLUP;
NET "cf_oe"               LOC = "M4";
NET "cf_pwr_en"  LOC = "P2";

#ir_data                                
NET "ir_data"    LOC = "D3"  ;



#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.