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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [077a94985ac208e4.logs/] [runme.log] - Rev 2
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*** Running vivado
with args -log axi_uartlite_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_uartlite_module.tcl
****** Vivado v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source axi_uartlite_module.tcl -notrace
Command: synth_design -top axi_uartlite_module -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5822
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1398.680 ; gain = 86.000 ; free physical = 1033 ; free virtual = 93527
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_BAUDRATE bound to: 38400 - type: integer
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_USE_PARITY bound to: 0 - type: integer
Parameter C_ODD_PARITY bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'axi_uartlite' declared at '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2090' bound to instance 'U0' of component 'axi_uartlite' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:161]
INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_BAUDRATE bound to: 38400 - type: integer
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_USE_PARITY bound to: 0 - type: integer
Parameter C_ODD_PARITY bound to: 0 - type: integer
INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2109]
INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2110]
INFO: [Synth 8-638] synthesizing module 'uartlite_core' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
Parameter C_BAUDRATE bound to: 38400 - type: integer
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_USE_PARITY bound to: 0 - type: integer
Parameter C_ODD_PARITY bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'baudrate' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
Parameter C_RATIO bound to: 163 - type: integer
INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
INFO: [Synth 8-3919] null assignment ignored [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1881]
INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_USE_PARITY bound to: 0 - type: integer
Parameter C_ODD_PARITY bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
Parameter C_DEPTH bound to: 16 - type: integer
Parameter C_DWIDTH bound to: 1 - type: integer
Parameter C_INIT_VALUE bound to: 1'b0
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f' (3#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
Parameter C_DWIDTH bound to: 8 - type: integer
Parameter C_DEPTH bound to: 16 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
Parameter C_DWIDTH bound to: 8 - type: integer
Parameter C_DEPTH bound to: 16 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
Parameter C_SIZE bound to: 5 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (4#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
Parameter C_DEPTH bound to: 16 - type: integer
Parameter C_DWIDTH bound to: 8 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (5#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (6#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (7#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (8#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_USE_PARITY bound to: 0 - type: integer
Parameter C_ODD_PARITY bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f__parameterized0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
Parameter C_DEPTH bound to: 16 - type: integer
Parameter C_DWIDTH bound to: 1 - type: integer
Parameter C_INIT_VALUE bound to: 16'b1000000000000000
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f__parameterized0' (8#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (9#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (10#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000000001111
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_IPIF_ABUS_WIDTH bound to: 4 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
Parameter C_BUS_AWIDTH bound to: 4 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b00
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b01
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b10
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b11
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (12#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
WARNING: [Synth 8-6014] Unused sequential element is_read_reg was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2447]
WARNING: [Synth 8-6014] Unused sequential element is_write_reg was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2448]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (13#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (14#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (15#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (16#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[31]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[30]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[29]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[28]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[27]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[26]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[25]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[24]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[23]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[22]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[21]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[20]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[19]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[18]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[17]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[16]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[15]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[14]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[13]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[12]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[11]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[10]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[9]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[8]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[7]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[6]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[5]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[4]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[3]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[2]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
WARNING: [Synth 8-3331] design uartlite_core has unconnected port bus2ip_cs
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1441.219 ; gain = 128.539 ; free physical = 1041 ; free virtual = 93536
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1441.219 ; gain = 128.539 ; free physical = 1040 ; free virtual = 93536
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 6 instances were transformed.
FDR => FDRE: 6 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1866.391 ; gain = 1.000 ; free physical = 764 ; free virtual = 93145
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 947 ; free virtual = 93323
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 947 ; free virtual = 93323
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 948 ; free virtual = 93325
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "EN_16x_Baud" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
INFO: [Synth 8-5546] ROM "fifo_full_p1" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
INFO: [Synth 8-5544] ROM "mux_sel_is_zero" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 940 ; free virtual = 93317
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
3 Input 5 Bit Adders := 2
2 Input 3 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
5 Bit Registers := 2
4 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 46
+---Muxes :
2 Input 8 Bit Muxes := 3
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 43
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module baudrate
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module cntr_incr_decr_addn_f
Detailed RTL Component Info :
+---Adders :
3 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
Module srl_fifo_rbu_f
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 3
Module uartlite_rx
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 15
+---Muxes :
2 Input 1 Bit Muxes := 12
Module uartlite_tx
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 10
Module uartlite_core
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
+---Muxes :
2 Input 8 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module pselect_f
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module pselect_f__parameterized0
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module pselect_f__parameterized1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module pselect_f__parameterized2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 6
Module slave_attachment
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 5
+---Muxes :
2 Input 4 Bit Muxes := 1
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-6014] Unused sequential element AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN[0].cs_out_i_reg was removed. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2004]
INFO: [Synth 8-5546] ROM "UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[31]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[30]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[29]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[28]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[27]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[26]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[25]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[24]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[23]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[22]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[21]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[20]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[19]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[18]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[17]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[16]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[15]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[14]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[13]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[12]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[11]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[10]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[9]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[8]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[3]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[2]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[1]
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[0]
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_uartlite.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:01:00 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 930 ; free virtual = 93306
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:01:11 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 804 ; free virtual = 93181
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93177
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[15][0] | 16 | 1 | NO | NO | YES | 1 | 0 |
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[15][0] | 16 | 1 | NO | NO | YES | 1 | 0 |
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Dynamic Shift Register Report:
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | INFERRED_GEN.data_reg[15] | 16 | 1 | 1 | 0 | 0 | 0 | 0 |
|dsrl__1 | INFERRED_GEN.data_reg[15] | 16 | 8 | 8 | 0 | 0 | 0 | 0 |
|dsrl__2 | INFERRED_GEN.data_reg[15] | 16 | 1 | 1 | 0 | 0 | 0 | 0 |
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |LUT1 | 1|
|2 |LUT2 | 14|
|3 |LUT3 | 19|
|4 |LUT4 | 17|
|5 |LUT5 | 44|
|6 |LUT6 | 17|
|7 |SRL16E | 18|
|8 |FDR | 4|
|9 |FDRE | 72|
|10 |FDSE | 16|
+------+-------+------+
Report Instance Areas:
+------+--------------------------------------------------------------------------+-----------------------------+------+
| |Instance |Module |Cells |
+------+--------------------------------------------------------------------------+-----------------------------+------+
|1 |top | | 222|
|2 | U0 |axi_uartlite | 222|
|3 | AXI_LITE_IPIF_I |axi_lite_ipif | 65|
|4 | I_SLAVE_ATTACHMENT |slave_attachment | 65|
|5 | I_DECODER |address_decoder | 37|
|6 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |pselect_f | 1|
|7 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |pselect_f__parameterized1 | 1|
|8 | UARTLITE_CORE_I |uartlite_core | 157|
|9 | BAUD_RATE_I |baudrate | 22|
|10 | UARTLITE_RX_I |uartlite_rx | 77|
|11 | DELAY_16_I |dynshreg_i_f | 17|
|12 | INPUT_DOUBLE_REGS3 |cdc_sync | 5|
|13 | SRL_FIFO_I |srl_fifo_f_0 | 28|
|14 | I_SRL_FIFO_RBU_F |srl_fifo_rbu_f_1 | 28|
|15 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f_2 | 17|
|16 | DYNSHREG_F_I |dynshreg_f_3 | 9|
|17 | UARTLITE_TX_I |uartlite_tx | 49|
|18 | MID_START_BIT_SRL16_I |dynshreg_i_f__parameterized0 | 3|
|19 | SRL_FIFO_I |srl_fifo_f | 31|
|20 | I_SRL_FIFO_RBU_F |srl_fifo_rbu_f | 31|
|21 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f | 17|
|22 | DYNSHREG_F_I |dynshreg_f | 13|
+------+--------------------------------------------------------------------------+-----------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 77 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1866.391 ; gain = 128.539 ; free physical = 855 ; free virtual = 93231
Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:01:13 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 855 ; free virtual = 93231
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 4 instances were transformed.
FDR => FDRE: 4 instances
INFO: [Common 17-83] Releasing license: Synthesis
82 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:40 ; elapsed = 00:01:14 . Memory (MB): peak = 1866.391 ; gain = 589.535 ; free physical = 843 ; free virtual = 93220
INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.