URL
https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
Subversion Repositories aes-128-ecb-encoder
[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [9f55fc6c5f1def66/] [microblaze_0_stub.vhdl] - Rev 2
Compare with Previous | Blame | View Log
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -- Date : Thu Jul 23 11:02:36 2020 -- Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ microblaze_0_stub.vhdl -- Design : microblaze_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( Clk : in STD_LOGIC; Reset : in STD_LOGIC; Interrupt : in STD_LOGIC; Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 ); Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 ); Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 ); Instr : in STD_LOGIC_VECTOR ( 0 to 31 ); IFetch : out STD_LOGIC; I_AS : out STD_LOGIC; IReady : in STD_LOGIC; IWAIT : in STD_LOGIC; ICE : in STD_LOGIC; IUE : in STD_LOGIC; Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 ); Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 ); Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 ); D_AS : out STD_LOGIC; Read_Strobe : out STD_LOGIC; Write_Strobe : out STD_LOGIC; DReady : in STD_LOGIC; DWait : in STD_LOGIC; DCE : in STD_LOGIC; DUE : in STD_LOGIC; Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 ); M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_DP_AWVALID : out STD_LOGIC; M_AXI_DP_AWREADY : in STD_LOGIC; M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_DP_WVALID : out STD_LOGIC; M_AXI_DP_WREADY : in STD_LOGIC; M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_DP_BVALID : in STD_LOGIC; M_AXI_DP_BREADY : out STD_LOGIC; M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_DP_ARVALID : out STD_LOGIC; M_AXI_DP_ARREADY : in STD_LOGIC; M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_DP_RVALID : in STD_LOGIC; M_AXI_DP_RREADY : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "Clk,Reset,Interrupt,Interrupt_Address[0:31],Interrupt_Ack[0:1],Instr_Addr[0:31],Instr[0:31],IFetch,I_AS,IReady,IWAIT,ICE,IUE,Data_Addr[0:31],Data_Read[0:31],Data_Write[0:31],D_AS,Read_Strobe,Write_Strobe,DReady,DWait,DCE,DUE,Byte_Enable[0:3],M_AXI_DP_AWADDR[31:0],M_AXI_DP_AWPROT[2:0],M_AXI_DP_AWVALID,M_AXI_DP_AWREADY,M_AXI_DP_WDATA[31:0],M_AXI_DP_WSTRB[3:0],M_AXI_DP_WVALID,M_AXI_DP_WREADY,M_AXI_DP_BRESP[1:0],M_AXI_DP_BVALID,M_AXI_DP_BREADY,M_AXI_DP_ARADDR[31:0],M_AXI_DP_ARPROT[2:0],M_AXI_DP_ARVALID,M_AXI_DP_ARREADY,M_AXI_DP_RDATA[31:0],M_AXI_DP_RRESP[1:0],M_AXI_DP_RVALID,M_AXI_DP_RREADY"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "MicroBlaze,Vivado 2017.4"; begin end;