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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [9f55fc6c5f1def66.logs/] [runme.log] - Rev 2
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*** Running vivadowith args -log microblaze_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source microblaze_0.tcl****** Vivado v2017.4 (64-bit)**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.source microblaze_0.tcl -notraceCommand: synth_design -top microblaze_0 -part xc7k325tffg900-2 -mode out_of_contextStarting synth_designAttempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'INFO: Launching helper process for spawning children vivado processesINFO: Helper process launched with PID 18140---------------------------------------------------------------------------------Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1400.574 ; gain = 88.004 ; free physical = 807 ; free virtual = 93482---------------------------------------------------------------------------------INFO: [Synth 8-638] synthesizing module 'microblaze_0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:107]Parameter C_SCO bound to: 0 - type: integerParameter C_FREQ bound to: 0 - type: integerParameter C_USE_CONFIG_RESET bound to: 0 - type: integerParameter C_NUM_SYNC_FF_CLK bound to: 2 - type: integerParameter C_NUM_SYNC_FF_CLK_IRQ bound to: 1 - type: integerParameter C_NUM_SYNC_FF_CLK_DEBUG bound to: 2 - type: integerParameter C_NUM_SYNC_FF_DBG_CLK bound to: 1 - type: integerParameter C_NUM_SYNC_FF_DBG_TRACE_CLK bound to: 2 - type: integerParameter C_FAULT_TOLERANT bound to: 0 - type: integerParameter C_ECC_USE_CE_EXCEPTION bound to: 0 - type: integerParameter C_LOCKSTEP_SLAVE bound to: 0 - type: integerParameter C_LOCKSTEP_MASTER bound to: 0 - type: integerParameter C_ENDIANNESS bound to: 1 - type: integerParameter C_FAMILY bound to: kintex7 - type: stringParameter C_DATA_SIZE bound to: 32 - type: integerParameter C_INSTR_SIZE bound to: 32 - type: integerParameter C_IADDR_SIZE bound to: 32 - type: integerParameter C_PIADDR_SIZE bound to: 32 - type: integerParameter C_DADDR_SIZE bound to: 32 - type: integerParameter C_INSTANCE bound to: microblaze_0 - type: stringParameter C_AVOID_PRIMITIVES bound to: 0 - type: integerParameter C_AREA_OPTIMIZED bound to: 0 - type: integerParameter C_OPTIMIZATION bound to: 0 - type: integerParameter C_INTERCONNECT bound to: 2 - type: integerParameter C_BASE_VECTORS bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000Parameter C_M_AXI_DP_THREAD_ID_WIDTH bound to: 1 - type: integerParameter C_M_AXI_DP_DATA_WIDTH bound to: 32 - type: integerParameter C_M_AXI_DP_ADDR_WIDTH bound to: 32 - type: integerParameter C_M_AXI_DP_EXCLUSIVE_ACCESS bound to: 0 - type: integerParameter C_M_AXI_D_BUS_EXCEPTION bound to: 0 - type: integerParameter C_M_AXI_IP_THREAD_ID_WIDTH bound to: 1 - type: integerParameter C_M_AXI_IP_DATA_WIDTH bound to: 32 - type: integerParameter C_M_AXI_IP_ADDR_WIDTH bound to: 32 - type: integerParameter C_M_AXI_I_BUS_EXCEPTION bound to: 0 - type: integerParameter C_D_LMB bound to: 1 - type: integerParameter C_D_AXI bound to: 1 - type: integerParameter C_I_LMB bound to: 1 - type: integerParameter C_I_AXI bound to: 0 - type: integerParameter C_USE_MSR_INSTR bound to: 0 - type: integerParameter C_USE_PCMP_INSTR bound to: 0 - type: integerParameter C_USE_BARREL bound to: 0 - type: integerParameter C_USE_DIV bound to: 0 - type: integerParameter C_USE_HW_MUL bound to: 1 - type: integerParameter C_USE_FPU bound to: 0 - type: integerParameter C_USE_REORDER_INSTR bound to: 0 - type: integerParameter C_UNALIGNED_EXCEPTIONS bound to: 0 - type: integerParameter C_ILL_OPCODE_EXCEPTION bound to: 0 - type: integerParameter C_DIV_ZERO_EXCEPTION bound to: 0 - type: integerParameter C_FPU_EXCEPTION bound to: 0 - type: integerParameter C_FSL_LINKS bound to: 0 - type: integerParameter C_USE_EXTENDED_FSL_INSTR bound to: 0 - type: integerParameter C_FSL_EXCEPTION bound to: 0 - type: integerParameter C_USE_STACK_PROTECTION bound to: 0 - type: integerParameter C_IMPRECISE_EXCEPTIONS bound to: 0 - type: integerParameter C_USE_INTERRUPT bound to: 0 - type: integerParameter C_USE_EXT_BRK bound to: 1 - type: integerParameter C_USE_EXT_NM_BRK bound to: 1 - type: integerParameter C_USE_NON_SECURE bound to: 1 - type: integerParameter C_USE_MMU bound to: 0 - type: integerParameter C_MMU_DTLB_SIZE bound to: 4 - type: integerParameter C_MMU_ITLB_SIZE bound to: 2 - type: integerParameter C_MMU_TLB_ACCESS bound to: 3 - type: integerParameter C_MMU_ZONES bound to: 2 - type: integerParameter C_MMU_PRIVILEGED_INSTR bound to: 0 - type: integerParameter C_USE_BRANCH_TARGET_CACHE bound to: 0 - type: integerParameter C_BRANCH_TARGET_CACHE_SIZE bound to: 0 - type: integerParameter C_PC_WIDTH bound to: 32 - type: integerParameter C_PVR bound to: 0 - type: integerParameter C_PVR_USER1 bound to: 8'b00000000Parameter C_PVR_USER2 bound to: 32'b00000000000000000000000000000000Parameter C_DYNAMIC_BUS_SIZING bound to: 0 - type: integerParameter C_RESET_MSR bound to: 32'b00000000000000000000000000000000Parameter C_OPCODE_0x0_ILLEGAL bound to: 0 - type: integerParameter C_DEBUG_ENABLED bound to: 0 - type: integerParameter C_DEBUG_INTERFACE bound to: 0 - type: integerParameter C_NUMBER_OF_PC_BRK bound to: 2 - type: integerParameter C_NUMBER_OF_RD_ADDR_BRK bound to: 0 - type: integerParameter C_NUMBER_OF_WR_ADDR_BRK bound to: 0 - type: integerParameter C_DEBUG_EVENT_COUNTERS bound to: 5 - type: integerParameter C_DEBUG_LATENCY_COUNTERS bound to: 1 - type: integerParameter C_DEBUG_COUNTER_WIDTH bound to: 32 - type: integerParameter C_DEBUG_TRACE_SIZE bound to: 8192 - type: integerParameter C_DEBUG_EXTERNAL_TRACE bound to: 0 - type: integerParameter C_DEBUG_TRACE_ASYNC_RESET bound to: 0 - type: integerParameter C_DEBUG_PROFILE_SIZE bound to: 0 - type: integerParameter C_INTERRUPT_IS_EDGE bound to: 0 - type: integerParameter C_EDGE_IS_POSITIVE bound to: 1 - type: integerParameter C_ASYNC_INTERRUPT bound to: 1 - type: integerParameter C_ASYNC_WAKEUP bound to: 1 - type: integerParameter C_M0_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S0_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M1_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S1_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M2_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S2_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M3_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S3_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M4_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S4_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M5_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S5_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M6_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S6_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M7_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S7_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M8_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S8_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M9_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S9_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M10_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S10_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M11_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S11_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M12_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S12_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M13_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S13_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M14_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S14_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_M15_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_S15_AXIS_DATA_WIDTH bound to: 32 - type: integerParameter C_ICACHE_BASEADDR bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000Parameter C_ICACHE_HIGHADDR bound to: 64'b0000000000000000000000000000000000111111111111111111111111111111Parameter C_USE_ICACHE bound to: 0 - type: integerParameter C_ALLOW_ICACHE_WR bound to: 1 - type: integerParameter C_ADDR_TAG_BITS bound to: 0 - type: integerParameter C_CACHE_BYTE_SIZE bound to: 8192 - type: integerParameter C_ICACHE_LINE_LEN bound to: 8 - type: integerParameter C_ICACHE_ALWAYS_USED bound to: 0 - type: integerParameter C_ICACHE_STREAMS bound to: 0 - type: integerParameter C_ICACHE_VICTIMS bound to: 0 - type: integerParameter C_ICACHE_FORCE_TAG_LUTRAM bound to: 0 - type: integerParameter C_ICACHE_DATA_WIDTH bound to: 0 - type: integerParameter C_M_AXI_IC_THREAD_ID_WIDTH bound to: 1 - type: integerParameter C_M_AXI_IC_DATA_WIDTH bound to: 32 - type: integerParameter C_M_AXI_IC_ADDR_WIDTH bound to: 32 - type: integerParameter C_M_AXI_IC_USER_VALUE bound to: 31 - type: integerParameter C_M_AXI_IC_AWUSER_WIDTH bound to: 5 - type: integerParameter C_M_AXI_IC_ARUSER_WIDTH bound to: 5 - type: integerParameter C_M_AXI_IC_WUSER_WIDTH bound to: 1 - type: integerParameter C_M_AXI_IC_RUSER_WIDTH bound to: 1 - type: integerParameter C_M_AXI_IC_BUSER_WIDTH bound to: 1 - type: integerParameter C_DCACHE_BASEADDR bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000Parameter C_DCACHE_HIGHADDR bound to: 64'b0000000000000000000000000000000000111111111111111111111111111111Parameter C_USE_DCACHE bound to: 0 - type: integerParameter C_ALLOW_DCACHE_WR bound to: 1 - type: integerParameter C_DCACHE_ADDR_TAG bound to: 0 - type: integerParameter C_DCACHE_BYTE_SIZE bound to: 8192 - type: integerParameter C_DCACHE_LINE_LEN bound to: 4 - type: integerParameter C_DCACHE_ALWAYS_USED bound to: 0 - type: integerParameter C_DCACHE_USE_WRITEBACK bound to: 0 - type: integerParameter C_DCACHE_VICTIMS bound to: 0 - type: integerParameter C_DCACHE_FORCE_TAG_LUTRAM bound to: 0 - type: integerParameter C_DCACHE_DATA_WIDTH bound to: 0 - type: integerParameter C_M_AXI_DC_THREAD_ID_WIDTH bound to: 1 - type: integerParameter C_M_AXI_DC_DATA_WIDTH bound to: 32 - type: integerParameter C_M_AXI_DC_ADDR_WIDTH bound to: 32 - type: integerParameter C_M_AXI_DC_EXCLUSIVE_ACCESS bound to: 0 - type: integerParameter C_M_AXI_DC_USER_VALUE bound to: 31 - type: integerParameter C_M_AXI_DC_AWUSER_WIDTH bound to: 5 - type: integerParameter C_M_AXI_DC_ARUSER_WIDTH bound to: 5 - type: integerParameter C_M_AXI_DC_WUSER_WIDTH bound to: 1 - type: integerParameter C_M_AXI_DC_RUSER_WIDTH bound to: 1 - type: integerParameter C_M_AXI_DC_BUSER_WIDTH bound to: 1 - type: integerINFO: [Synth 8-3491] module 'MicroBlaze' declared at '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/hdl/microblaze_v10_0_vh_rfs.vhd:157134' bound to instance 'U0' of component 'MicroBlaze' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:786]INFO: [Synth 8-256] done synthesizing module 'microblaze_0' (49#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:107]WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_BID[0]WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_BRESP[0]WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RID[0]WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RRESP[0]WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RLASTWARNING: [Synth 8-3331] design DAXI_interface has unconnected port MEM_DataBus_ExclusiveWARNING: [Synth 8-3331] design DAXI_interface has unconnected port MEM_UModeWARNING: [Synth 8-3331] design MMU has unconnected port ClkWARNING: [Synth 8-3331] design MMU has unconnected port ResetWARNING: [Synth 8-3331] design MMU has unconnected port IB_VModeWARNING: [Synth 8-3331] design MMU has unconnected port IB_UModeWARNING: [Synth 8-3331] design MMU has unconnected port EX_VModeWARNING: [Synth 8-3331] design MMU has unconnected port EX_UModeWARNING: [Synth 8-3331] design MMU has unconnected port EX_DataBus_WriteWARNING: [Synth 8-3331] design MMU has unconnected port EX_Write_DCache_InstrWARNING: [Synth 8-3331] design MMU has unconnected port EX_Unmask_EAWARNING: [Synth 8-3331] design MMU has unconnected port ICACHE_Valid_AddrWARNING: [Synth 8-3331] design MMU has unconnected port OF_PipeRunWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_PIDWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_ZPRWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBXWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBLOWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBHIWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBSXWARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_EAWARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[0]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[1]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[2]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[3]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[4]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[5]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[6]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[7]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[8]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[9]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[10]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[11]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[12]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[13]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[14]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[15]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[16]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[17]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[18]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[19]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[20]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[21]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[22]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[23]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[24]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[25]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[26]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[27]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[28]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[29]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[30]WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[31]WARNING: [Synth 8-3331] design MMU has unconnected port EX_PipeRunWARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_TLBLOWARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_TLBHIWARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_EAWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_PIDWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_ZPRWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBXWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBLOWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBHIWARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_EAWARNING: [Synth 8-3331] design MMU has unconnected port MEM_PipeRunWARNING: [Synth 8-3331] design MMU has unconnected port MEM_potential_exceptionWARNING: [Synth 8-3331] design MMU has unconnected port WB_exceptionWARNING: [Synth 8-3331] design MMU has unconnected port Snoop_Req_TLB_DoneWARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_InvalidateWARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[0]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[1]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[2]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[3]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[4]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[5]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[6]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[7]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[8]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[9]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[10]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[11]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[12]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[13]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[14]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[15]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[16]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[17]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[18]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[19]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[20]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[21]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[22]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[23]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[24]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[25]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[26]WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[27]INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.---------------------------------------------------------------------------------Finished RTL Elaboration : Time (s): cpu = 00:00:19 ; elapsed = 00:00:36 . Memory (MB): peak = 1693.844 ; gain = 381.273 ; free physical = 578 ; free virtual = 93255---------------------------------------------------------------------------------Report Check Netlist:+------+------------------+-------+---------+-------+------------------+| |Item |Errors |Warnings |Status |Description |+------+------------------+-------+---------+-------+------------------+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |+------+------------------+-------+---------+-------+------------------+---------------------------------------------------------------------------------Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:37 . Memory (MB): peak = 1693.844 ; gain = 381.273 ; free physical = 586 ; free virtual = 93262---------------------------------------------------------------------------------INFO: [Netlist 29-17] Analyzing 589 Unisim elements for replacementINFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU secondsINFO: [Device 21-403] Loading part xc7k325tffg900-2INFO: [Project 1-570] Preparing netlist for logic optimizationProcessing XDC ConstraintsInitializing timing engineParsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc_debug.xdc] for cell 'U0'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc_debug.xdc] for cell 'U0'Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc.xdc] for cell 'U0'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc.xdc] for cell 'U0'Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc] for cell 'U0'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc] for cell 'U0'INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/microblaze_0_propImpl.xdc].Resolution: To avoid this warning, move constraints listed in [.Xil/microblaze_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc]Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc]Completed Processing XDC ConstraintsINFO: [Project 1-111] Unisim Transformation Summary:A total of 384 instances were transformed.FDE => FDRE: 32 instancesFDR => FDRE: 126 instancesFDS => FDSE: 1 instancesLUT6_2 => LUT6_2 (LUT5, LUT6): 80 instancesMULT_AND => LUT2: 1 instancesMUXCY_L => MUXCY: 128 instancesRAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instancesConstraint Validation Runtime : Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2004.602 ; gain = 1.000 ; free physical = 301 ; free virtual = 92977---------------------------------------------------------------------------------Finished Constraint Validation : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 451 ; free virtual = 93127------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Loading Part and Timing Information---------------------------------------------------------------------------------Loading part: xc7k325tffg900-2---------------------------------------------------------------------------------Finished Loading Part and Timing Information : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 451 ; free virtual = 93127------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Applying 'set_property' XDC Constraints---------------------------------------------------------------------------------Applied set_property DONT_TOUCH = true for U0. (constraint file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc, line 9).---------------------------------------------------------------------------------Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 453 ; free virtual = 93129---------------------------------------------------------------------------------INFO: [Synth 8-5546] ROM "ext_nm_brk_hold_clr" won't be mapped to RAM because it is too sparseINFO: [Synth 8-5544] ROM "EX_Pattern_Cmp_Sel" won't be mapped to Block RAM because address size (2) smaller than threshold (5)INFO: [Synth 8-5546] ROM "ex_gpr_write" won't be mapped to RAM because it is too sparseINFO: [Synth 8-5544] ROM "ex_move_to_MSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)INFO: [Synth 8-5544] ROM "ex_move_to_FSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)INFO: [Synth 8-5546] ROM "ext_nm_brk_hold_clr" won't be mapped to RAM because it is too sparseINFO: [Synth 8-5544] ROM "EX_Pattern_Cmp_Sel" won't be mapped to Block RAM because address size (2) smaller than threshold (5)INFO: [Synth 8-5546] ROM "ex_gpr_write" won't be mapped to RAM because it is too sparseINFO: [Synth 8-5544] ROM "ex_move_to_MSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)INFO: [Synth 8-5544] ROM "ex_move_to_FSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)INFO: [Synth 8-5544] ROM "of_Sel_SPR_MSR" won't be mapped to Block RAM because address size (3) smaller than threshold (5)INFO: [Synth 8-5544] ROM "dbg_stop_instr_fetch" won't be mapped to Block RAM because address size (2) smaller than threshold (5)---------------------------------------------------------------------------------Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:54 ; elapsed = 00:01:35 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 535 ; free virtual = 93211---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start RTL Component Statistics---------------------------------------------------------------------------------Detailed RTL Component Info :+---XORs :2 Input 2 Bit XORs := 12 Input 1 Bit XORs := 23 Input 1 Bit XORs := 1+---Registers :4096 Bit Registers := 132 Bit Registers := 2716 Bit Registers := 115 Bit Registers := 113 Bit Registers := 26 Bit Registers := 15 Bit Registers := 44 Bit Registers := 63 Bit Registers := 32 Bit Registers := 81 Bit Registers := 171+---Muxes :2 Input 32 Bit Muxes := 124 Input 32 Bit Muxes := 32 Input 16 Bit Muxes := 12 Input 15 Bit Muxes := 92 Input 13 Bit Muxes := 12 Input 8 Bit Muxes := 92 Input 5 Bit Muxes := 36 Input 5 Bit Muxes := 17 Input 4 Bit Muxes := 12 Input 3 Bit Muxes := 12 Input 2 Bit Muxes := 103 Input 2 Bit Muxes := 18 Input 1 Bit Muxes := 17 Input 1 Bit Muxes := 62 Input 1 Bit Muxes := 814 Input 1 Bit Muxes := 13 Input 1 Bit Muxes := 4---------------------------------------------------------------------------------Finished RTL Component Statistics------------------------------------------------------------------------------------------------------------------------------------------------------------------Start RTL Hierarchical Component Statistics---------------------------------------------------------------------------------Hierarchical RTL Component reportModule mb_sync_bitDetailed RTL Component Info :+---Registers :2 Bit Registers := 1Module PC_Module_gtiDetailed RTL Component Info :+---Registers :32 Bit Registers := 3+---Muxes :2 Input 32 Bit Muxes := 1Module PreFetch_Buffer_gtiDetailed RTL Component Info :+---Registers :1 Bit Registers := 1+---Muxes :2 Input 2 Bit Muxes := 1Module jump_logicDetailed RTL Component Info :+---Registers :1 Bit Registers := 9+---Muxes :8 Input 1 Bit Muxes := 17 Input 1 Bit Muxes := 52 Input 1 Bit Muxes := 2Module Decode_gtiDetailed RTL Component Info :+---Registers :32 Bit Registers := 46 Bit Registers := 15 Bit Registers := 44 Bit Registers := 23 Bit Registers := 32 Bit Registers := 41 Bit Registers := 142+---Muxes :2 Input 5 Bit Muxes := 26 Input 5 Bit Muxes := 12 Input 2 Bit Muxes := 53 Input 2 Bit Muxes := 12 Input 1 Bit Muxes := 544 Input 1 Bit Muxes := 13 Input 1 Bit Muxes := 47 Input 1 Bit Muxes := 1Module Operand_Select_gtiDetailed RTL Component Info :+---Registers :32 Bit Registers := 416 Bit Registers := 1+---Muxes :2 Input 32 Bit Muxes := 64 Input 32 Bit Muxes := 3Module ALU_Bit__parameterized2Detailed RTL Component Info :+---XORs :2 Input 1 Bit XORs := 1Module Shift_Logic_Module_gtiDetailed RTL Component Info :+---Muxes :2 Input 32 Bit Muxes := 12 Input 8 Bit Muxes := 42 Input 1 Bit Muxes := 5Module mul_unitDetailed RTL Component Info :+---Registers :32 Bit Registers := 1Module Byte_Doublet_Handle_gtiDetailed RTL Component Info :+---XORs :2 Input 2 Bit XORs := 12 Input 1 Bit XORs := 13 Input 1 Bit XORs := 1+---Registers :32 Bit Registers := 14 Bit Registers := 12 Bit Registers := 2+---Muxes :2 Input 32 Bit Muxes := 22 Input 16 Bit Muxes := 12 Input 8 Bit Muxes := 57 Input 4 Bit Muxes := 12 Input 2 Bit Muxes := 3Module Data_Flow_LogicDetailed RTL Component Info :+---Registers :32 Bit Registers := 14 Bit Registers := 21 Bit Registers := 2Module msr_reg_gtiDetailed RTL Component Info :+---Registers :15 Bit Registers := 1+---Muxes :2 Input 15 Bit Muxes := 92 Input 2 Bit Muxes := 12 Input 1 Bit Muxes := 8Module exception_registers_gtiDetailed RTL Component Info :+---Registers :32 Bit Registers := 813 Bit Registers := 2+---Muxes :2 Input 13 Bit Muxes := 12 Input 5 Bit Muxes := 12 Input 3 Bit Muxes := 12 Input 1 Bit Muxes := 1Module Data_Flow_gtiDetailed RTL Component Info :+---Muxes :2 Input 32 Bit Muxes := 2Module DAXI_interfaceDetailed RTL Component Info :+---Registers :32 Bit Registers := 11 Bit Registers := 10+---Muxes :2 Input 1 Bit Muxes := 7Module MicroBlaze_GTiDetailed RTL Component Info :+---Registers :32 Bit Registers := 44 Bit Registers := 11 Bit Registers := 4Module MicroBlaze_CoreDetailed RTL Component Info :+---Registers :1 Bit Registers := 3+---Muxes :2 Input 1 Bit Muxes := 4Module MicroBlazeDetailed RTL Component Info :+---Registers :4096 Bit Registers := 1---------------------------------------------------------------------------------Finished RTL Hierarchical Component Statistics------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Part Resource Summary---------------------------------------------------------------------------------Part Resources:DSPs: 840 (col length:140)BRAMs: 890 (col length: RAMB18 140 RAMB36 70)---------------------------------------------------------------------------------Finished Part Resource Summary------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Cross Boundary and Area Optimization---------------------------------------------------------------------------------INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_IE_hold_reg )INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[9]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[3]'INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_bs_instr_reg' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg'INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_fpu_instr_reg )INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[8]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[2]'INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst/Using_FPGA.Native )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/mem_access_failed_reg )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_MSR_set_decode_reg )INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[10]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[4]'INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Sel_SPR_EA_I_reg )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Instr_Excep_combo_reg )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4095] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4094] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4093] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4092] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4091] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4090] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4089] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4088] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4087] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4086] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4085] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4084] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4083] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4082] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4081] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4080] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4079] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4078] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4077] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4076] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4075] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4074] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4073] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4072] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4071] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4070] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4069] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4068] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4067] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4066] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4065] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4064] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4063] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4062] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4061] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4060] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4059] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4058] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4057] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4056] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4055] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4054] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4053] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4052] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4051] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4050] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4049] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4048] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4047] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4046] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4045] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4044] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4043] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4042] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4041] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4040] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4039] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4038] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4037] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4036] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4035] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4034] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4033] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4032] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4031] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4030] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4029] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4028] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4027] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4026] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4025] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4024] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4023] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4022] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4021] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4020] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4019] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4018] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4017] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4016] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4015] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4014] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4013] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4012] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4011] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4010] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4009] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4008] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4007] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4006] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4005] )INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4004] )INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[715]' (FDR) to 'U0/LOCKSTEP_Out_reg[549]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[663]' (FDR) to 'U0/LOCKSTEP_Out_reg[497]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[662]' (FDR) to 'U0/LOCKSTEP_Out_reg[496]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[661]' (FDR) to 'U0/LOCKSTEP_Out_reg[495]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[660]' (FDR) to 'U0/LOCKSTEP_Out_reg[494]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[659]' (FDR) to 'U0/LOCKSTEP_Out_reg[493]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[658]' (FDR) to 'U0/LOCKSTEP_Out_reg[492]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[657]' (FDR) to 'U0/LOCKSTEP_Out_reg[491]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[656]' (FDR) to 'U0/LOCKSTEP_Out_reg[490]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[655]' (FDR) to 'U0/LOCKSTEP_Out_reg[489]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[654]' (FDR) to 'U0/LOCKSTEP_Out_reg[488]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[653]' (FDR) to 'U0/LOCKSTEP_Out_reg[487]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[652]' (FDR) to 'U0/LOCKSTEP_Out_reg[486]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[651]' (FDR) to 'U0/LOCKSTEP_Out_reg[485]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[650]' (FDR) to 'U0/LOCKSTEP_Out_reg[484]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[649]' (FDR) to 'U0/LOCKSTEP_Out_reg[483]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[648]' (FDR) to 'U0/LOCKSTEP_Out_reg[482]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[647]' (FDR) to 'U0/LOCKSTEP_Out_reg[481]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[646]' (FDR) to 'U0/LOCKSTEP_Out_reg[480]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[645]' (FDR) to 'U0/LOCKSTEP_Out_reg[479]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[644]' (FDR) to 'U0/LOCKSTEP_Out_reg[478]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[643]' (FDR) to 'U0/LOCKSTEP_Out_reg[477]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[642]' (FDR) to 'U0/LOCKSTEP_Out_reg[476]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[641]' (FDR) to 'U0/LOCKSTEP_Out_reg[475]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[640]' (FDR) to 'U0/LOCKSTEP_Out_reg[474]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[639]' (FDR) to 'U0/LOCKSTEP_Out_reg[473]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[638]' (FDR) to 'U0/LOCKSTEP_Out_reg[472]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[637]' (FDR) to 'U0/LOCKSTEP_Out_reg[471]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[636]' (FDR) to 'U0/LOCKSTEP_Out_reg[470]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[635]' (FDR) to 'U0/LOCKSTEP_Out_reg[469]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[634]' (FDR) to 'U0/LOCKSTEP_Out_reg[468]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[633]' (FDR) to 'U0/LOCKSTEP_Out_reg[467]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[632]' (FDR) to 'U0/LOCKSTEP_Out_reg[466]'INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA_2.ex_reverse_mem_access_inst/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_exception_kind_i_reg[27]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_MSR_set_decode_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Sel_SPR_EA_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[1]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Sign_Extend_Sel_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Pattern_Cmp_Sel_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_SWAP_BYTE_Instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Sel_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_IE_hold_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_set_MSR_IE_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_EE_hold_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_set_MSR_EE_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_move_to_FSR_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_start_div_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_fpu_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Left_Shift_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Arith_Shift_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Bit_Insert_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Bit_Extract_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[22]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[23]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[24]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[25]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[26]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[27]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_start_fpu_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Not_FPU_Instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_FSR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_potential_exception_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_SLR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_SHR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_is_fpu_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_PVR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_SPR_PVR_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_load_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_DataBus_Read_Data_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_MEM_Res_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_mul_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_is_mul_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[0]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[1]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[2]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[3]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[0]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[1]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[2]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[3]) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EA_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_write_icache_done_i_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_read_imm_reg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_read_imm_reg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Read_Imm_Reg_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_read_imm_reg_1_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_read_imm_reg_1_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Read_Imm_Reg_1_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_PC_Valid_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Dbg_Clean_Stop_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_BTR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_ESR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EAR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EDR_I_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_store_instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_SW_Instr_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_word_access_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Word_Access_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_jump_hit_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Trace_WB_Jump_Hit_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Instr_Excep_combo_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_EX_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[17].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[18].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[19].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[20].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[21].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[22].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[23].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[24].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[25].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[26].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[27].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[31].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[17].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[17].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[18].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[18].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[19].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[19].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[20].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[20].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[21].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[21].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[22].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[722]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[717]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[713]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[712]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[708]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[705]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[630]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[628]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[551]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[547]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[546]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[542]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'---------------------------------------------------------------------------------Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:02 ; elapsed = 00:01:44 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 518 ; free virtual = 93194---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Applying XDC Timing Constraints------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:12 ; elapsed = 00:01:58 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 370 ; free virtual = 93047------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Timing Optimization------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Timing Optimization : Time (s): cpu = 00:01:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2152.676 ; gain = 840.105 ; free physical = 903 ; free virtual = 92876---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Technology Mapping------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Technology Mapping : Time (s): cpu = 00:01:54 ; elapsed = 00:02:43 . Memory (MB): peak = 2152.676 ; gain = 840.105 ; free physical = 901 ; free virtual = 92875---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Flattening Before IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Flattening Before IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Final Netlist Cleanup------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Final Netlist Cleanup------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished IO Insertion : Time (s): cpu = 00:01:54 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 902 ; free virtual = 92875---------------------------------------------------------------------------------Report Check Netlist:+------+------------------+-------+---------+-------+------------------+| |Item |Errors |Warnings |Status |Description |+------+------------------+-------+---------+-------+------------------+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |+------+------------------+-------+---------+-------+------------------+---------------------------------------------------------------------------------Start Renaming Generated Instances------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Instances : Time (s): cpu = 00:01:54 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 902 ; free virtual = 92875---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Rebuilding User Hierarchy------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:55 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Renaming Generated Ports------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Ports : Time (s): cpu = 00:01:55 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Handling Custom Attributes------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Handling Custom Attributes : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Renaming Generated Nets------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Nets : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873------------------------------------------------------------------------------------------------------------------------------------------------------------------Start ROM, RAM, DSP and Shift Register Reporting---------------------------------------------------------------------------------Dynamic Shift Register Report:+------------+------------------+--------+------------+--------+---------+--------+--------+--------+|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |+------------+------------------+--------+------------+--------+---------+--------+--------+--------+|dsrl | PC_Buffer_reg[3] | 4 | 32 | 32 | 0 | 0 | 0 | 0 ||dsrl__1 | ibuffer_reg[3] | 4 | 43 | 43 | 0 | 0 | 0 | 0 |+------------+------------------+--------+------------+--------+---------+--------+--------+--------+---------------------------------------------------------------------------------Finished ROM, RAM, DSP and Shift Register Reporting------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Writing Synthesis Report---------------------------------------------------------------------------------Report BlackBoxes:+-+--------------+----------+| |BlackBox name |Instances |+-+--------------+----------++-+--------------+----------+Report Cell Usage:+------+----------+------+| |Cell |Count |+------+----------+------+|1 |AND2B1L | 1||2 |DSP48E1 | 1||3 |DSP48E1_1 | 1||4 |DSP48E1_2 | 1||5 |LUT1 | 16||6 |LUT2 | 75||7 |LUT3 | 195||8 |LUT4 | 134||9 |LUT5 | 240||10 |LUT6 | 254||11 |LUT6_2 | 64||12 |MULT_AND | 1||13 |MUXCY_L | 126||14 |MUXF7 | 108||15 |RAM32M | 16||16 |SRL16E | 75||17 |XORCY | 94||18 |FDE | 32||19 |FDR | 88||20 |FDRE | 1106||21 |FDS | 1||22 |FDSE | 36|+------+----------+------+Report Instance Areas:+------+------------------------------------------------------------------------------+------------------------------+------+| |Instance |Module |Cells |+------+------------------------------------------------------------------------------+------------------------------+------+|1 |top | | 2665||2 | U0 |MicroBlaze | 2665||3 | MicroBlaze_Core_I |MicroBlaze_Core | 2300||4 | \Performance.Core |MicroBlaze_GTi | 2290||5 | Data_Flow_I |Data_Flow_gti | 743||6 | ALU_I |ALU | 143||7 | \Use_Carry_Decoding.CarryIn_MUXCY |MB_MUXCY_433 | 1||8 | \Using_FPGA.ALL_Bits[0].ALU_Bit_I1 |ALU_Bit__parameterized2 | 6||9 | \Last_Bit.I_ALU_LUT_2 |MB_LUT4 | 1||10 | \Last_Bit.I_ALU_LUT_V5 |MB_LUT6__parameterized12 | 1||11 | \Last_Bit.MULT_AND_I |MB_MULT_AND | 1||12 | \Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_525 | 2||13 | \Last_Bit.Pre_MUXCY_I |MB_MUXCY_526 | 1||14 | \Using_FPGA.ALL_Bits[10].ALU_Bit_I1 |ALU_Bit | 5||15 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_523 | 1||16 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_524 | 4||17 | \Using_FPGA.ALL_Bits[11].ALU_Bit_I1 |ALU_Bit_434 | 5||18 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_521 | 1||19 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_522 | 4||20 | \Using_FPGA.ALL_Bits[12].ALU_Bit_I1 |ALU_Bit_435 | 5||21 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_519 | 1||22 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_520 | 4||23 | \Using_FPGA.ALL_Bits[13].ALU_Bit_I1 |ALU_Bit_436 | 5||24 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_517 | 1||25 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_518 | 4||26 | \Using_FPGA.ALL_Bits[14].ALU_Bit_I1 |ALU_Bit_437 | 4||27 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_515 | 1||28 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_516 | 3||29 | \Using_FPGA.ALL_Bits[15].ALU_Bit_I1 |ALU_Bit_438 | 5||30 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_513 | 1||31 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_514 | 4||32 | \Using_FPGA.ALL_Bits[16].ALU_Bit_I1 |ALU_Bit_439 | 5||33 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_511 | 1||34 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_512 | 4||35 | \Using_FPGA.ALL_Bits[17].ALU_Bit_I1 |ALU_Bit_440 | 4||36 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_509 | 1||37 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_510 | 3||38 | \Using_FPGA.ALL_Bits[18].ALU_Bit_I1 |ALU_Bit_441 | 5||39 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_507 | 1||40 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_508 | 4||41 | \Using_FPGA.ALL_Bits[19].ALU_Bit_I1 |ALU_Bit_442 | 4||42 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_505 | 1||43 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_506 | 3||44 | \Using_FPGA.ALL_Bits[1].ALU_Bit_I1 |ALU_Bit_443 | 5||45 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_503 | 1||46 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_504 | 4||47 | \Using_FPGA.ALL_Bits[20].ALU_Bit_I1 |ALU_Bit_444 | 5||48 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_501 | 1||49 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_502 | 4||50 | \Using_FPGA.ALL_Bits[21].ALU_Bit_I1 |ALU_Bit_445 | 5||51 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_499 | 1||52 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_500 | 4||53 | \Using_FPGA.ALL_Bits[22].ALU_Bit_I1 |ALU_Bit_446 | 5||54 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_497 | 1||55 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_498 | 4||56 | \Using_FPGA.ALL_Bits[23].ALU_Bit_I1 |ALU_Bit_447 | 4||57 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_495 | 1||58 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_496 | 3||59 | \Using_FPGA.ALL_Bits[24].ALU_Bit_I1 |ALU_Bit_448 | 3||60 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_493 | 1||61 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_494 | 2||62 | \Using_FPGA.ALL_Bits[25].ALU_Bit_I1 |ALU_Bit_449 | 3||63 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_491 | 1||64 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_492 | 2||65 | \Using_FPGA.ALL_Bits[26].ALU_Bit_I1 |ALU_Bit_450 | 3||66 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_489 | 1||67 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_490 | 2||68 | \Using_FPGA.ALL_Bits[27].ALU_Bit_I1 |ALU_Bit_451 | 3||69 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_487 | 1||70 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_488 | 2||71 | \Using_FPGA.ALL_Bits[28].ALU_Bit_I1 |ALU_Bit_452 | 3||72 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_485 | 1||73 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_486 | 2||74 | \Using_FPGA.ALL_Bits[29].ALU_Bit_I1 |ALU_Bit_453 | 3||75 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_483 | 1||76 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_484 | 2||77 | \Using_FPGA.ALL_Bits[2].ALU_Bit_I1 |ALU_Bit_454 | 5||78 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_481 | 1||79 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_482 | 4||80 | \Using_FPGA.ALL_Bits[30].ALU_Bit_I1 |ALU_Bit_455 | 3||81 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_479 | 1||82 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_480 | 2||83 | \Using_FPGA.ALL_Bits[31].ALU_Bit_I1 |ALU_Bit_456 | 3||84 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_477 | 1||85 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_478 | 2||86 | \Using_FPGA.ALL_Bits[3].ALU_Bit_I1 |ALU_Bit_457 | 5||87 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_475 | 1||88 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_476 | 4||89 | \Using_FPGA.ALL_Bits[4].ALU_Bit_I1 |ALU_Bit_458 | 5||90 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_473 | 1||91 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_474 | 4||92 | \Using_FPGA.ALL_Bits[5].ALU_Bit_I1 |ALU_Bit_459 | 5||93 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_471 | 1||94 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_472 | 4||95 | \Using_FPGA.ALL_Bits[6].ALU_Bit_I1 |ALU_Bit_460 | 5||96 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_469 | 1||97 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_470 | 4||98 | \Using_FPGA.ALL_Bits[7].ALU_Bit_I1 |ALU_Bit_461 | 4||99 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_467 | 1||100 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_468 | 3||101 | \Using_FPGA.ALL_Bits[8].ALU_Bit_I1 |ALU_Bit_462 | 6||102 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2_465 | 1||103 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_466 | 5||104 | \Using_FPGA.ALL_Bits[9].ALU_Bit_I1 |ALU_Bit_463 | 5||105 | \Not_Last_Bit.I_ALU_LUT_V5 |MB_LUT6_2 | 1||106 | \Not_Last_Bit.MUXCY_XOR_I |MB_MUXCY_XORCY_464 | 4||107 | Byte_Doublet_Handle_gti_I |Byte_Doublet_Handle_gti | 50||108 | Data_Flow_Logic_I |Data_Flow_Logic | 65||109 | \Gen_Bits[0].MEM_EX_Result_Inst |MB_FDRE_401 | 1||110 | \Gen_Bits[10].MEM_EX_Result_Inst |MB_FDRE_402 | 1||111 | \Gen_Bits[11].MEM_EX_Result_Inst |MB_FDRE_403 | 1||112 | \Gen_Bits[12].MEM_EX_Result_Inst |MB_FDRE_404 | 1||113 | \Gen_Bits[13].MEM_EX_Result_Inst |MB_FDRE_405 | 1||114 | \Gen_Bits[14].MEM_EX_Result_Inst |MB_FDRE_406 | 1||115 | \Gen_Bits[15].MEM_EX_Result_Inst |MB_FDRE_407 | 1||116 | \Gen_Bits[16].MEM_EX_Result_Inst |MB_FDRE_408 | 1||117 | \Gen_Bits[17].MEM_EX_Result_Inst |MB_FDRE_409 | 1||118 | \Gen_Bits[18].MEM_EX_Result_Inst |MB_FDRE_410 | 1||119 | \Gen_Bits[19].MEM_EX_Result_Inst |MB_FDRE_411 | 1||120 | \Gen_Bits[1].MEM_EX_Result_Inst |MB_FDRE_412 | 1||121 | \Gen_Bits[20].MEM_EX_Result_Inst |MB_FDRE_413 | 1||122 | \Gen_Bits[21].MEM_EX_Result_Inst |MB_FDRE_414 | 1||123 | \Gen_Bits[22].MEM_EX_Result_Inst |MB_FDRE_415 | 1||124 | \Gen_Bits[23].MEM_EX_Result_Inst |MB_FDRE_416 | 1||125 | \Gen_Bits[24].MEM_EX_Result_Inst |MB_FDRE_417 | 1||126 | \Gen_Bits[25].MEM_EX_Result_Inst |MB_FDRE_418 | 1||127 | \Gen_Bits[26].MEM_EX_Result_Inst |MB_FDRE_419 | 1||128 | \Gen_Bits[27].MEM_EX_Result_Inst |MB_FDRE_420 | 1||129 | \Gen_Bits[28].MEM_EX_Result_Inst |MB_FDRE_421 | 1||130 | \Gen_Bits[29].MEM_EX_Result_Inst |MB_FDRE_422 | 1||131 | \Gen_Bits[2].MEM_EX_Result_Inst |MB_FDRE_423 | 1||132 | \Gen_Bits[30].MEM_EX_Result_Inst |MB_FDRE_424 | 1||133 | \Gen_Bits[31].MEM_EX_Result_Inst |MB_FDRE_425 | 1||134 | \Gen_Bits[3].MEM_EX_Result_Inst |MB_FDRE_426 | 1||135 | \Gen_Bits[4].MEM_EX_Result_Inst |MB_FDRE_427 | 1||136 | \Gen_Bits[5].MEM_EX_Result_Inst |MB_FDRE_428 | 1||137 | \Gen_Bits[6].MEM_EX_Result_Inst |MB_FDRE_429 | 1||138 | \Gen_Bits[7].MEM_EX_Result_Inst |MB_FDRE_430 | 1||139 | \Gen_Bits[8].MEM_EX_Result_Inst |MB_FDRE_431 | 1||140 | \Gen_Bits[9].MEM_EX_Result_Inst |MB_FDRE_432 | 1||141 | MUL_Unit_I |mul_unit | 20||142 | \Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2 |dsp_module__parameterized1 | 1||143 | \Using_DSP48E1.DSP48E1_I1 |MB_DSP48E1__parameterized1 | 1||144 | \Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3 |dsp_module__parameterized3 | 1||145 | \Using_DSP48E1.DSP48E1_I1 |MB_DSP48E1__parameterized3 | 1||146 | \Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1 |dsp_module | 1||147 | \Using_DSP48E1.DSP48E1_I1 |MB_DSP48E1 | 1||148 | Operand_Select_I |Operand_Select_gti | 246||149 | \Gen_Bit[0].MUXF7_I1 |MB_MUXF7_369 | 1||150 | \Gen_Bit[10].MUXF7_I1 |MB_MUXF7_370 | 2||151 | \Gen_Bit[11].MUXF7_I1 |MB_MUXF7_371 | 2||152 | \Gen_Bit[12].MUXF7_I1 |MB_MUXF7_372 | 2||153 | \Gen_Bit[13].MUXF7_I1 |MB_MUXF7_373 | 2||154 | \Gen_Bit[14].MUXF7_I1 |MB_MUXF7_374 | 2||155 | \Gen_Bit[15].MUXF7_I1 |MB_MUXF7_375 | 2||156 | \Gen_Bit[16].MUXF7_I1 |MB_MUXF7_376 | 2||157 | \Gen_Bit[17].MUXF7_I1 |MB_MUXF7_377 | 2||158 | \Gen_Bit[18].MUXF7_I1 |MB_MUXF7_378 | 2||159 | \Gen_Bit[19].MUXF7_I1 |MB_MUXF7_379 | 2||160 | \Gen_Bit[1].MUXF7_I1 |MB_MUXF7_380 | 2||161 | \Gen_Bit[20].MUXF7_I1 |MB_MUXF7_381 | 2||162 | \Gen_Bit[21].MUXF7_I1 |MB_MUXF7_382 | 2||163 | \Gen_Bit[22].MUXF7_I1 |MB_MUXF7_383 | 2||164 | \Gen_Bit[23].MUXF7_I1 |MB_MUXF7_384 | 2||165 | \Gen_Bit[24].MUXF7_I1 |MB_MUXF7_385 | 3||166 | \Gen_Bit[25].MUXF7_I1 |MB_MUXF7_386 | 3||167 | \Gen_Bit[26].MUXF7_I1 |MB_MUXF7_387 | 2||168 | \Gen_Bit[27].MUXF7_I1 |MB_MUXF7_388 | 2||169 | \Gen_Bit[28].MUXF7_I1 |MB_MUXF7_389 | 3||170 | \Gen_Bit[29].MUXF7_I1 |MB_MUXF7_390 | 2||171 | \Gen_Bit[2].MUXF7_I1 |MB_MUXF7_391 | 2||172 | \Gen_Bit[30].MUXF7_I1 |MB_MUXF7_392 | 2||173 | \Gen_Bit[31].MUXF7_I1 |MB_MUXF7_393 | 2||174 | \Gen_Bit[3].MUXF7_I1 |MB_MUXF7_394 | 2||175 | \Gen_Bit[4].MUXF7_I1 |MB_MUXF7_395 | 2||176 | \Gen_Bit[5].MUXF7_I1 |MB_MUXF7_396 | 2||177 | \Gen_Bit[6].MUXF7_I1 |MB_MUXF7_397 | 2||178 | \Gen_Bit[7].MUXF7_I1 |MB_MUXF7_398 | 2||179 | \Gen_Bit[8].MUXF7_I1 |MB_MUXF7_399 | 2||180 | \Gen_Bit[9].MUXF7_I1 |MB_MUXF7_400 | 2||181 | Register_File_I |Register_File_gti | 23||182 | \Using_LUT6.All_RAM32M[0].ram32m_i |MB_RAM32M | 2||183 | \Using_LUT6.All_RAM32M[10].ram32m_i |MB_RAM32M_354 | 1||184 | \Using_LUT6.All_RAM32M[11].ram32m_i |MB_RAM32M_355 | 2||185 | \Using_LUT6.All_RAM32M[12].ram32m_i |MB_RAM32M_356 | 1||186 | \Using_LUT6.All_RAM32M[13].ram32m_i |MB_RAM32M_357 | 1||187 | \Using_LUT6.All_RAM32M[14].ram32m_i |MB_RAM32M_358 | 1||188 | \Using_LUT6.All_RAM32M[15].ram32m_i |MB_RAM32M_359 | 1||189 | \Using_LUT6.All_RAM32M[1].ram32m_i |MB_RAM32M_360 | 1||190 | \Using_LUT6.All_RAM32M[2].ram32m_i |MB_RAM32M_361 | 2||191 | \Using_LUT6.All_RAM32M[3].ram32m_i |MB_RAM32M_362 | 1||192 | \Using_LUT6.All_RAM32M[4].ram32m_i |MB_RAM32M_363 | 2||193 | \Using_LUT6.All_RAM32M[5].ram32m_i |MB_RAM32M_364 | 1||194 | \Using_LUT6.All_RAM32M[6].ram32m_i |MB_RAM32M_365 | 2||195 | \Using_LUT6.All_RAM32M[7].ram32m_i |MB_RAM32M_366 | 1||196 | \Using_LUT6.All_RAM32M[8].ram32m_i |MB_RAM32M_367 | 2||197 | \Using_LUT6.All_RAM32M[9].ram32m_i |MB_RAM32M_368 | 2||198 | Shift_Logic_Module_I |Shift_Logic_Module_gti | 0||199 | \Using_DAXI_ALU_Carry.Direct_MUXCY_I |MB_MUXCY_243 | 1||200 | \Using_DAXI_ALU_Carry.Post_MUXCY_I |MB_MUXCY_244 | 1||201 | \Using_DAXI_ALU_Carry.direct_lut_INST |MB_LUT6_2__parameterized1 | 1||202 | Zero_Detect_I |Zero_Detect_gti | 12||203 | Part_Of_Zero_Carry_Start |MB_MUXCY_347 | 1||204 | \Zero_Detecting[0].I_Part_Of_Zero_Detect |MB_MUXCY_348 | 1||205 | \Zero_Detecting[1].I_Part_Of_Zero_Detect |MB_MUXCY_349 | 1||206 | \Zero_Detecting[2].I_Part_Of_Zero_Detect |MB_MUXCY_350 | 1||207 | \Zero_Detecting[3].I_Part_Of_Zero_Detect |MB_MUXCY_351 | 1||208 | \Zero_Detecting[4].I_Part_Of_Zero_Detect |MB_MUXCY_352 | 1||209 | \Zero_Detecting[5].I_Part_Of_Zero_Detect |MB_MUXCY_353 | 1||210 | exception_registers_I1 |exception_registers_gti | 161||211 | CarryIn_MUXCY |MB_MUXCY_252 | 1||212 | \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB |MB_LUT6_2__parameterized5 | 1||213 | \Using_FPGA_LUT6.Gen_Ret_Addr[0].MUXCY_XOR_I |MB_MUXCY_XORCY_253 | 2||214 | \Using_FPGA_LUT6.Gen_Ret_Addr[0].WB_PC_FDE |MB_FDE | 1||215 | \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_254 | 1||216 | \Using_FPGA_LUT6.Gen_Ret_Addr[10].MUXCY_XOR_I |MB_MUXCY_XORCY_255 | 4||217 | \Using_FPGA_LUT6.Gen_Ret_Addr[10].WB_PC_FDE |MB_FDE_256 | 1||218 | \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_257 | 1||219 | \Using_FPGA_LUT6.Gen_Ret_Addr[11].MUXCY_XOR_I |MB_MUXCY_XORCY_258 | 4||220 | \Using_FPGA_LUT6.Gen_Ret_Addr[11].WB_PC_FDE |MB_FDE_259 | 1||221 | \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_260 | 1||222 | \Using_FPGA_LUT6.Gen_Ret_Addr[12].MUXCY_XOR_I |MB_MUXCY_XORCY_261 | 3||223 | \Using_FPGA_LUT6.Gen_Ret_Addr[12].WB_PC_FDE |MB_FDE_262 | 1||224 | \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_263 | 1||225 | \Using_FPGA_LUT6.Gen_Ret_Addr[13].MUXCY_XOR_I |MB_MUXCY_XORCY_264 | 3||226 | \Using_FPGA_LUT6.Gen_Ret_Addr[13].WB_PC_FDE |MB_FDE_265 | 1||227 | \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_266 | 1||228 | \Using_FPGA_LUT6.Gen_Ret_Addr[14].MUXCY_XOR_I |MB_MUXCY_XORCY_267 | 3||229 | \Using_FPGA_LUT6.Gen_Ret_Addr[14].WB_PC_FDE |MB_FDE_268 | 1||230 | \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_269 | 1||231 | \Using_FPGA_LUT6.Gen_Ret_Addr[15].MUXCY_XOR_I |MB_MUXCY_XORCY_270 | 3||232 | \Using_FPGA_LUT6.Gen_Ret_Addr[15].WB_PC_FDE |MB_FDE_271 | 1||233 | \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_272 | 1||234 | \Using_FPGA_LUT6.Gen_Ret_Addr[16].MUXCY_XOR_I |MB_MUXCY_XORCY_273 | 3||235 | \Using_FPGA_LUT6.Gen_Ret_Addr[16].WB_PC_FDE |MB_FDE_274 | 1||236 | \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_275 | 1||237 | \Using_FPGA_LUT6.Gen_Ret_Addr[17].MUXCY_XOR_I |MB_MUXCY_XORCY_276 | 3||238 | \Using_FPGA_LUT6.Gen_Ret_Addr[17].WB_PC_FDE |MB_FDE_277 | 1||239 | \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_278 | 1||240 | \Using_FPGA_LUT6.Gen_Ret_Addr[18].MUXCY_XOR_I |MB_MUXCY_XORCY_279 | 3||241 | \Using_FPGA_LUT6.Gen_Ret_Addr[18].WB_PC_FDE |MB_FDE_280 | 1||242 | \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_281 | 1||243 | \Using_FPGA_LUT6.Gen_Ret_Addr[19].MUXCY_XOR_I |MB_MUXCY_XORCY_282 | 3||244 | \Using_FPGA_LUT6.Gen_Ret_Addr[19].WB_PC_FDE |MB_FDE_283 | 1||245 | \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_284 | 1||246 | \Using_FPGA_LUT6.Gen_Ret_Addr[1].MUXCY_XOR_I |MB_MUXCY_XORCY_285 | 3||247 | \Using_FPGA_LUT6.Gen_Ret_Addr[1].WB_PC_FDE |MB_FDE_286 | 1||248 | \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_287 | 1||249 | \Using_FPGA_LUT6.Gen_Ret_Addr[20].MUXCY_XOR_I |MB_MUXCY_XORCY_288 | 4||250 | \Using_FPGA_LUT6.Gen_Ret_Addr[20].WB_PC_FDE |MB_FDE_289 | 1||251 | \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_290 | 1||252 | \Using_FPGA_LUT6.Gen_Ret_Addr[21].MUXCY_XOR_I |MB_MUXCY_XORCY_291 | 4||253 | \Using_FPGA_LUT6.Gen_Ret_Addr[21].WB_PC_FDE |MB_FDE_292 | 1||254 | \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_293 | 1||255 | \Using_FPGA_LUT6.Gen_Ret_Addr[22].MUXCY_XOR_I |MB_MUXCY_XORCY_294 | 3||256 | \Using_FPGA_LUT6.Gen_Ret_Addr[22].WB_PC_FDE |MB_FDE_295 | 1||257 | \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_296 | 1||258 | \Using_FPGA_LUT6.Gen_Ret_Addr[23].MUXCY_XOR_I |MB_MUXCY_XORCY_297 | 3||259 | \Using_FPGA_LUT6.Gen_Ret_Addr[23].WB_PC_FDE |MB_FDE_298 | 1||260 | \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_299 | 1||261 | \Using_FPGA_LUT6.Gen_Ret_Addr[24].MUXCY_XOR_I |MB_MUXCY_XORCY_300 | 2||262 | \Using_FPGA_LUT6.Gen_Ret_Addr[24].WB_PC_FDE |MB_FDE_301 | 1||263 | \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_302 | 1||264 | \Using_FPGA_LUT6.Gen_Ret_Addr[25].MUXCY_XOR_I |MB_MUXCY_XORCY_303 | 4||265 | \Using_FPGA_LUT6.Gen_Ret_Addr[25].WB_PC_FDE |MB_FDE_304 | 1||266 | \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_305 | 1||267 | \Using_FPGA_LUT6.Gen_Ret_Addr[26].MUXCY_XOR_I |MB_MUXCY_XORCY_306 | 3||268 | \Using_FPGA_LUT6.Gen_Ret_Addr[26].WB_PC_FDE |MB_FDE_307 | 1||269 | \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_308 | 1||270 | \Using_FPGA_LUT6.Gen_Ret_Addr[27].MUXCY_XOR_I |MB_MUXCY_XORCY_309 | 2||271 | \Using_FPGA_LUT6.Gen_Ret_Addr[27].WB_PC_FDE |MB_FDE_310 | 1||272 | \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_311 | 1||273 | \Using_FPGA_LUT6.Gen_Ret_Addr[28].MUXCY_XOR_I |MB_MUXCY_XORCY_312 | 2||274 | \Using_FPGA_LUT6.Gen_Ret_Addr[28].WB_PC_FDE |MB_FDE_313 | 1||275 | \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_314 | 1||276 | \Using_FPGA_LUT6.Gen_Ret_Addr[29].MUXCY_XOR_I |MB_MUXCY_XORCY_315 | 2||277 | \Using_FPGA_LUT6.Gen_Ret_Addr[29].WB_PC_FDE |MB_FDE_316 | 1||278 | \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_317 | 1||279 | \Using_FPGA_LUT6.Gen_Ret_Addr[2].MUXCY_XOR_I |MB_MUXCY_XORCY_318 | 3||280 | \Using_FPGA_LUT6.Gen_Ret_Addr[2].WB_PC_FDE |MB_FDE_319 | 1||281 | \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_320 | 1||282 | \Using_FPGA_LUT6.Gen_Ret_Addr[30].MUXCY_XOR_I |MB_MUXCY_XORCY_321 | 3||283 | \Using_FPGA_LUT6.Gen_Ret_Addr[30].WB_PC_FDE |MB_FDE_322 | 1||284 | \Using_FPGA_LUT6.Gen_Ret_Addr[31].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_323 | 1||285 | \Using_FPGA_LUT6.Gen_Ret_Addr[31].MUXCY_XOR_I |MB_MUXCY_XORCY_324 | 2||286 | \Using_FPGA_LUT6.Gen_Ret_Addr[31].WB_PC_FDE |MB_FDE_325 | 1||287 | \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_326 | 1||288 | \Using_FPGA_LUT6.Gen_Ret_Addr[3].MUXCY_XOR_I |MB_MUXCY_XORCY_327 | 3||289 | \Using_FPGA_LUT6.Gen_Ret_Addr[3].WB_PC_FDE |MB_FDE_328 | 1||290 | \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_329 | 1||291 | \Using_FPGA_LUT6.Gen_Ret_Addr[4].MUXCY_XOR_I |MB_MUXCY_XORCY_330 | 3||292 | \Using_FPGA_LUT6.Gen_Ret_Addr[4].WB_PC_FDE |MB_FDE_331 | 1||293 | \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_332 | 1||294 | \Using_FPGA_LUT6.Gen_Ret_Addr[5].MUXCY_XOR_I |MB_MUXCY_XORCY_333 | 3||295 | \Using_FPGA_LUT6.Gen_Ret_Addr[5].WB_PC_FDE |MB_FDE_334 | 1||296 | \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_335 | 1||297 | \Using_FPGA_LUT6.Gen_Ret_Addr[6].MUXCY_XOR_I |MB_MUXCY_XORCY_336 | 3||298 | \Using_FPGA_LUT6.Gen_Ret_Addr[6].WB_PC_FDE |MB_FDE_337 | 1||299 | \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_338 | 1||300 | \Using_FPGA_LUT6.Gen_Ret_Addr[7].MUXCY_XOR_I |MB_MUXCY_XORCY_339 | 3||301 | \Using_FPGA_LUT6.Gen_Ret_Addr[7].WB_PC_FDE |MB_FDE_340 | 1||302 | \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_341 | 1||303 | \Using_FPGA_LUT6.Gen_Ret_Addr[8].MUXCY_XOR_I |MB_MUXCY_XORCY_342 | 4||304 | \Using_FPGA_LUT6.Gen_Ret_Addr[8].WB_PC_FDE |MB_FDE_343 | 1||305 | \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB |MB_LUT6_2__parameterized5_344 | 1||306 | \Using_FPGA_LUT6.Gen_Ret_Addr[9].MUXCY_XOR_I |MB_MUXCY_XORCY_345 | 3||307 | \Using_FPGA_LUT6.Gen_Ret_Addr[9].WB_PC_FDE |MB_FDE_346 | 1||308 | msr_reg_i |msr_reg_gti | 20||309 | \MEM_MSR_Bits[28].Using_FDR.MSR_I |MB_FDR_245 | 2||310 | \MEM_MSR_Bits[29].Using_FDR.MSR_I |MB_FDR_246 | 3||311 | \MEM_MSR_Bits[30].Using_FDR.MSR_I |MB_FDR_247 | 3||312 | \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I |MB_FDR_248 | 1||313 | \OF_EX_MSR_Bits[28].Using_FDR.MSR_of_I |MB_FDR_249 | 1||314 | \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I |MB_FDR_250 | 2||315 | \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I |MB_FDR_251 | 2||316 | Decode_I |Decode_gti | 1358||317 | PC_Module_I |PC_Module_gti | 343||318 | \Instruction_Prefetch_Mux[0].Gen_Instr_DFF |MB_FDR_150 | 2||319 | \Instruction_Prefetch_Mux[0].PC_Mux_MUXF7 |MB_MUXF7_151 | 2||320 | \Instruction_Prefetch_Mux[10].Gen_Instr_DFF |MB_FDR_152 | 3||321 | \Instruction_Prefetch_Mux[10].PC_Mux_MUXF7 |MB_MUXF7_153 | 2||322 | \Instruction_Prefetch_Mux[11].Gen_Instr_DFF |MB_FDR_154 | 3||323 | \Instruction_Prefetch_Mux[11].PC_Mux_MUXF7 |MB_MUXF7_155 | 2||324 | \Instruction_Prefetch_Mux[12].Gen_Instr_DFF |MB_FDR_156 | 3||325 | \Instruction_Prefetch_Mux[12].PC_Mux_MUXF7 |MB_MUXF7_157 | 2||326 | \Instruction_Prefetch_Mux[13].Gen_Instr_DFF |MB_FDR_158 | 3||327 | \Instruction_Prefetch_Mux[13].PC_Mux_MUXF7 |MB_MUXF7_159 | 2||328 | \Instruction_Prefetch_Mux[14].Gen_Instr_DFF |MB_FDR_160 | 3||329 | \Instruction_Prefetch_Mux[14].PC_Mux_MUXF7 |MB_MUXF7_161 | 2||330 | \Instruction_Prefetch_Mux[15].Gen_Instr_DFF |MB_FDR_162 | 3||331 | \Instruction_Prefetch_Mux[15].PC_Mux_MUXF7 |MB_MUXF7_163 | 2||332 | \Instruction_Prefetch_Mux[16].Gen_Instr_DFF |MB_FDR_164 | 3||333 | \Instruction_Prefetch_Mux[16].PC_Mux_MUXF7 |MB_MUXF7_165 | 2||334 | \Instruction_Prefetch_Mux[17].Gen_Instr_DFF |MB_FDR_166 | 3||335 | \Instruction_Prefetch_Mux[17].PC_Mux_MUXF7 |MB_MUXF7_167 | 2||336 | \Instruction_Prefetch_Mux[18].Gen_Instr_DFF |MB_FDR_168 | 3||337 | \Instruction_Prefetch_Mux[18].PC_Mux_MUXF7 |MB_MUXF7_169 | 2||338 | \Instruction_Prefetch_Mux[19].Gen_Instr_DFF |MB_FDR_170 | 3||339 | \Instruction_Prefetch_Mux[19].PC_Mux_MUXF7 |MB_MUXF7_171 | 2||340 | \Instruction_Prefetch_Mux[1].Gen_Instr_DFF |MB_FDR_172 | 3||341 | \Instruction_Prefetch_Mux[1].PC_Mux_MUXF7 |MB_MUXF7_173 | 2||342 | \Instruction_Prefetch_Mux[20].Gen_Instr_DFF |MB_FDR_174 | 3||343 | \Instruction_Prefetch_Mux[20].PC_Mux_MUXF7 |MB_MUXF7_175 | 2||344 | \Instruction_Prefetch_Mux[21].Gen_Instr_DFF |MB_FDR_176 | 3||345 | \Instruction_Prefetch_Mux[21].PC_Mux_MUXF7 |MB_MUXF7_177 | 2||346 | \Instruction_Prefetch_Mux[22].Gen_Instr_DFF |MB_FDR_178 | 3||347 | \Instruction_Prefetch_Mux[22].PC_Mux_MUXF7 |MB_MUXF7_179 | 2||348 | \Instruction_Prefetch_Mux[23].Gen_Instr_DFF |MB_FDR_180 | 3||349 | \Instruction_Prefetch_Mux[23].PC_Mux_MUXF7 |MB_MUXF7_181 | 2||350 | \Instruction_Prefetch_Mux[24].Gen_Instr_DFF |MB_FDR_182 | 3||351 | \Instruction_Prefetch_Mux[24].PC_Mux_MUXF7 |MB_MUXF7_183 | 2||352 | \Instruction_Prefetch_Mux[25].Gen_Instr_DFF |MB_FDR_184 | 3||353 | \Instruction_Prefetch_Mux[25].PC_Mux_MUXF7 |MB_MUXF7_185 | 2||354 | \Instruction_Prefetch_Mux[26].Gen_Instr_DFF |MB_FDR_186 | 3||355 | \Instruction_Prefetch_Mux[26].PC_Mux_MUXF7 |MB_MUXF7_187 | 2||356 | \Instruction_Prefetch_Mux[27].Gen_Instr_DFF |MB_FDR_188 | 3||357 | \Instruction_Prefetch_Mux[27].PC_Mux_MUXF7 |MB_MUXF7_189 | 2||358 | \Instruction_Prefetch_Mux[28].Gen_Instr_DFF |MB_FDR_190 | 2||359 | \Instruction_Prefetch_Mux[28].PC_Mux_MUXF7 |MB_MUXF7_191 | 2||360 | \Instruction_Prefetch_Mux[29].Gen_Instr_DFF |MB_FDR_192 | 2||361 | \Instruction_Prefetch_Mux[29].PC_Mux_MUXF7 |MB_MUXF7_193 | 2||362 | \Instruction_Prefetch_Mux[2].Gen_Instr_DFF |MB_FDR_194 | 3||363 | \Instruction_Prefetch_Mux[2].PC_Mux_MUXF7 |MB_MUXF7_195 | 2||364 | \Instruction_Prefetch_Mux[30].Gen_Instr_DFF |MB_FDR_196 | 2||365 | \Instruction_Prefetch_Mux[30].PC_Mux_MUXF7 |MB_MUXF7_197 | 2||366 | \Instruction_Prefetch_Mux[31].Gen_Instr_DFF |MB_FDR_198 | 3||367 | \Instruction_Prefetch_Mux[31].PC_Mux_MUXF7 |MB_MUXF7_199 | 2||368 | \Instruction_Prefetch_Mux[3].Gen_Instr_DFF |MB_FDR_200 | 3||369 | \Instruction_Prefetch_Mux[3].PC_Mux_MUXF7 |MB_MUXF7_201 | 2||370 | \Instruction_Prefetch_Mux[4].Gen_Instr_DFF |MB_FDR_202 | 3||371 | \Instruction_Prefetch_Mux[4].PC_Mux_MUXF7 |MB_MUXF7_203 | 2||372 | \Instruction_Prefetch_Mux[5].Gen_Instr_DFF |MB_FDR_204 | 3||373 | \Instruction_Prefetch_Mux[5].PC_Mux_MUXF7 |MB_MUXF7_205 | 2||374 | \Instruction_Prefetch_Mux[6].Gen_Instr_DFF |MB_FDR_206 | 3||375 | \Instruction_Prefetch_Mux[6].PC_Mux_MUXF7 |MB_MUXF7_207 | 2||376 | \Instruction_Prefetch_Mux[7].Gen_Instr_DFF |MB_FDR_208 | 3||377 | \Instruction_Prefetch_Mux[7].PC_Mux_MUXF7 |MB_MUXF7_209 | 2||378 | \Instruction_Prefetch_Mux[8].Gen_Instr_DFF |MB_FDR_210 | 3||379 | \Instruction_Prefetch_Mux[8].PC_Mux_MUXF7 |MB_MUXF7_211 | 2||380 | \Instruction_Prefetch_Mux[9].Gen_Instr_DFF |MB_FDR_212 | 3||381 | \Instruction_Prefetch_Mux[9].PC_Mux_MUXF7 |MB_MUXF7_213 | 2||382 | \Using_FPGA.Incr_PC[0].MUXCY_XOR_I |MB_MUXCY_XORCY | 1||383 | \Using_FPGA.Incr_PC[10].MUXCY_XOR_I |MB_MUXCY_XORCY_214 | 2||384 | \Using_FPGA.Incr_PC[11].MUXCY_XOR_I |MB_MUXCY_XORCY_215 | 2||385 | \Using_FPGA.Incr_PC[12].MUXCY_XOR_I |MB_MUXCY_XORCY_216 | 2||386 | \Using_FPGA.Incr_PC[13].MUXCY_XOR_I |MB_MUXCY_XORCY_217 | 2||387 | \Using_FPGA.Incr_PC[14].MUXCY_XOR_I |MB_MUXCY_XORCY_218 | 2||388 | \Using_FPGA.Incr_PC[15].MUXCY_XOR_I |MB_MUXCY_XORCY_219 | 2||389 | \Using_FPGA.Incr_PC[16].MUXCY_XOR_I |MB_MUXCY_XORCY_220 | 2||390 | \Using_FPGA.Incr_PC[17].MUXCY_XOR_I |MB_MUXCY_XORCY_221 | 2||391 | \Using_FPGA.Incr_PC[18].MUXCY_XOR_I |MB_MUXCY_XORCY_222 | 2||392 | \Using_FPGA.Incr_PC[19].MUXCY_XOR_I |MB_MUXCY_XORCY_223 | 2||393 | \Using_FPGA.Incr_PC[1].MUXCY_XOR_I |MB_MUXCY_XORCY_224 | 2||394 | \Using_FPGA.Incr_PC[20].MUXCY_XOR_I |MB_MUXCY_XORCY_225 | 2||395 | \Using_FPGA.Incr_PC[21].MUXCY_XOR_I |MB_MUXCY_XORCY_226 | 2||396 | \Using_FPGA.Incr_PC[22].MUXCY_XOR_I |MB_MUXCY_XORCY_227 | 2||397 | \Using_FPGA.Incr_PC[23].MUXCY_XOR_I |MB_MUXCY_XORCY_228 | 2||398 | \Using_FPGA.Incr_PC[24].MUXCY_XOR_I |MB_MUXCY_XORCY_229 | 2||399 | \Using_FPGA.Incr_PC[25].MUXCY_XOR_I |MB_MUXCY_XORCY_230 | 2||400 | \Using_FPGA.Incr_PC[26].MUXCY_XOR_I |MB_MUXCY_XORCY_231 | 2||401 | \Using_FPGA.Incr_PC[27].MUXCY_XOR_I |MB_MUXCY_XORCY_232 | 2||402 | \Using_FPGA.Incr_PC[28].MUXCY_XOR_I |MB_MUXCY_XORCY_233 | 2||403 | \Using_FPGA.Incr_PC[29].MUXCY_XOR_I |MB_MUXCY_XORCY_234 | 2||404 | \Using_FPGA.Incr_PC[2].MUXCY_XOR_I |MB_MUXCY_XORCY_235 | 2||405 | \Using_FPGA.Incr_PC[3].MUXCY_XOR_I |MB_MUXCY_XORCY_236 | 2||406 | \Using_FPGA.Incr_PC[4].MUXCY_XOR_I |MB_MUXCY_XORCY_237 | 2||407 | \Using_FPGA.Incr_PC[5].MUXCY_XOR_I |MB_MUXCY_XORCY_238 | 2||408 | \Using_FPGA.Incr_PC[6].MUXCY_XOR_I |MB_MUXCY_XORCY_239 | 2||409 | \Using_FPGA.Incr_PC[7].MUXCY_XOR_I |MB_MUXCY_XORCY_240 | 2||410 | \Using_FPGA.Incr_PC[8].MUXCY_XOR_I |MB_MUXCY_XORCY_241 | 2||411 | \Using_FPGA.Incr_PC[9].MUXCY_XOR_I |MB_MUXCY_XORCY_242 | 2||412 | PreFetch_Buffer_I1 |PreFetch_Buffer_gti | 541||413 | \Gen_Mux_Select_LUT6[1].Gen_Sel_DFF |MB_FDR_56 | 5||414 | \Gen_Mux_Select_LUT6[1].Mux_Select_LUT6 |MB_LUT6 | 1||415 | \Gen_Mux_Select_LUT6[2].Gen_Sel_DFF |MB_FDR_57 | 4||416 | \Gen_Mux_Select_LUT6[2].Mux_Select_LUT6 |MB_LUT6_58 | 1||417 | \Gen_Mux_Select_LUT6[3].Gen_Sel_DFF |MB_FDR_59 | 1||418 | \Gen_Mux_Select_LUT6[3].Mux_Select_LUT6 |MB_LUT6_60 | 1||419 | \Gen_Mux_Select_LUT6[4].Gen_Sel_DFF |MB_FDR_61 | 44||420 | \Gen_Mux_Select_LUT6[4].Mux_Select_LUT6 |MB_LUT6_62 | 1||421 | \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Mux_Select_Delayslot_LUT6 |MB_LUT6__parameterized2 | 1||422 | \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Sel_Mux_MUXF7 |MB_MUXF7 | 2||423 | \Instruction_Prefetch_Mux[0].Gen_Instr_DFF |MB_FDR_63 | 1||424 | \Instruction_Prefetch_Mux[0].Instr_Mux_MUXF7 |MB_MUXF7_64 | 1||425 | \Instruction_Prefetch_Mux[10].Gen_Instr_DFF |MB_FDR_65 | 2||426 | \Instruction_Prefetch_Mux[10].Instr_Mux_MUXF7 |MB_MUXF7_66 | 1||427 | \Instruction_Prefetch_Mux[11].Gen_Instr_DFF |MB_FDR_67 | 1||428 | \Instruction_Prefetch_Mux[11].Instr_Mux_MUXF7 |MB_MUXF7_68 | 1||429 | \Instruction_Prefetch_Mux[12].Gen_Instr_DFF |MB_FDR_69 | 1||430 | \Instruction_Prefetch_Mux[12].Instr_Mux_MUXF7 |MB_MUXF7_70 | 1||431 | \Instruction_Prefetch_Mux[13].Gen_Instr_DFF |MB_FDR_71 | 1||432 | \Instruction_Prefetch_Mux[13].Instr_Mux_MUXF7 |MB_MUXF7_72 | 1||433 | \Instruction_Prefetch_Mux[14].Gen_Instr_DFF |MB_FDR_73 | 1||434 | \Instruction_Prefetch_Mux[14].Instr_Mux_MUXF7 |MB_MUXF7_74 | 1||435 | \Instruction_Prefetch_Mux[15].Gen_Instr_DFF |MB_FDR_75 | 1||436 | \Instruction_Prefetch_Mux[15].Instr_Mux_MUXF7 |MB_MUXF7_76 | 1||437 | \Instruction_Prefetch_Mux[16].Gen_Instr_DFF |MB_FDR_77 | 35||438 | \Instruction_Prefetch_Mux[16].Instr_Mux_MUXF7 |MB_MUXF7_78 | 1||439 | \Instruction_Prefetch_Mux[17].Gen_Instr_DFF |MB_FDR_79 | 5||440 | \Instruction_Prefetch_Mux[17].Instr_Mux_MUXF7 |MB_MUXF7_80 | 1||441 | \Instruction_Prefetch_Mux[18].Gen_Instr_DFF |MB_FDR_81 | 3||442 | \Instruction_Prefetch_Mux[18].Instr_Mux_MUXF7 |MB_MUXF7_82 | 1||443 | \Instruction_Prefetch_Mux[19].Gen_Instr_DFF |MB_FDR_83 | 3||444 | \Instruction_Prefetch_Mux[19].Instr_Mux_MUXF7 |MB_MUXF7_84 | 1||445 | \Instruction_Prefetch_Mux[1].Gen_Instr_DFF |MB_FDR_85 | 15||446 | \Instruction_Prefetch_Mux[1].Instr_Mux_MUXF7 |MB_MUXF7_86 | 1||447 | \Instruction_Prefetch_Mux[20].Gen_Instr_DFF |MB_FDR_87 | 3||448 | \Instruction_Prefetch_Mux[20].Instr_Mux_MUXF7 |MB_MUXF7_88 | 1||449 | \Instruction_Prefetch_Mux[21].Gen_Instr_DFF |MB_FDR_89 | 5||450 | \Instruction_Prefetch_Mux[21].Instr_Mux_MUXF7 |MB_MUXF7_90 | 1||451 | \Instruction_Prefetch_Mux[22].Gen_Instr_DFF |MB_FDR_91 | 3||452 | \Instruction_Prefetch_Mux[22].Instr_Mux_MUXF7 |MB_MUXF7_92 | 1||453 | \Instruction_Prefetch_Mux[23].Gen_Instr_DFF |MB_FDR_93 | 3||454 | \Instruction_Prefetch_Mux[23].Instr_Mux_MUXF7 |MB_MUXF7_94 | 1||455 | \Instruction_Prefetch_Mux[24].Gen_Instr_DFF |MB_FDR_95 | 3||456 | \Instruction_Prefetch_Mux[24].Instr_Mux_MUXF7 |MB_MUXF7_96 | 1||457 | \Instruction_Prefetch_Mux[25].Gen_Instr_DFF |MB_FDR_97 | 4||458 | \Instruction_Prefetch_Mux[25].Instr_Mux_MUXF7 |MB_MUXF7_98 | 1||459 | \Instruction_Prefetch_Mux[26].Gen_Instr_DFF |MB_FDR_99 | 3||460 | \Instruction_Prefetch_Mux[26].Instr_Mux_MUXF7 |MB_MUXF7_100 | 1||461 | \Instruction_Prefetch_Mux[27].Gen_Instr_DFF |MB_FDR_101 | 1||462 | \Instruction_Prefetch_Mux[27].Instr_Mux_MUXF7 |MB_MUXF7_102 | 1||463 | \Instruction_Prefetch_Mux[28].Gen_Instr_DFF |MB_FDR_103 | 1||464 | \Instruction_Prefetch_Mux[28].Instr_Mux_MUXF7 |MB_MUXF7_104 | 1||465 | \Instruction_Prefetch_Mux[29].Gen_Instr_DFF |MB_FDR_105 | 3||466 | \Instruction_Prefetch_Mux[29].Instr_Mux_MUXF7 |MB_MUXF7_106 | 1||467 | \Instruction_Prefetch_Mux[2].Gen_Instr_DFF |MB_FDR_107 | 16||468 | \Instruction_Prefetch_Mux[2].Instr_Mux_MUXF7 |MB_MUXF7_108 | 1||469 | \Instruction_Prefetch_Mux[30].Gen_Instr_DFF |MB_FDR_109 | 5||470 | \Instruction_Prefetch_Mux[30].Instr_Mux_MUXF7 |MB_MUXF7_110 | 1||471 | \Instruction_Prefetch_Mux[31].Gen_Instr_DFF |MB_FDR_111 | 6||472 | \Instruction_Prefetch_Mux[31].Instr_Mux_MUXF7 |MB_MUXF7_112 | 1||473 | \Instruction_Prefetch_Mux[32].Gen_Instr_DFF |MB_FDR_113 | 4||474 | \Instruction_Prefetch_Mux[32].Instr_Mux_MUXF7 |MB_MUXF7_114 | 2||475 | \Instruction_Prefetch_Mux[33].Gen_Instr_DFF |MB_FDR_115 | 42||476 | \Instruction_Prefetch_Mux[33].Instr_Mux_MUXF7 |MB_MUXF7_116 | 1||477 | \Instruction_Prefetch_Mux[34].Gen_Instr_DFF |MB_FDR_117 | 2||478 | \Instruction_Prefetch_Mux[34].Instr_Mux_MUXF7 |MB_MUXF7_118 | 1||479 | \Instruction_Prefetch_Mux[35].Gen_Instr_DFF |MB_FDR_119 | 2||480 | \Instruction_Prefetch_Mux[35].Instr_Mux_MUXF7 |MB_MUXF7_120 | 1||481 | \Instruction_Prefetch_Mux[36].Gen_Instr_DFF |MB_FDR_121 | 1||482 | \Instruction_Prefetch_Mux[36].Instr_Mux_MUXF7 |MB_MUXF7_122 | 1||483 | \Instruction_Prefetch_Mux[37].Gen_Instr_DFF |MB_FDR_123 | 3||484 | \Instruction_Prefetch_Mux[37].Instr_Mux_MUXF7 |MB_MUXF7_124 | 1||485 | \Instruction_Prefetch_Mux[38].Gen_Instr_DFF |MB_FDR_125 | 36||486 | \Instruction_Prefetch_Mux[38].Instr_Mux_MUXF7 |MB_MUXF7_126 | 1||487 | \Instruction_Prefetch_Mux[39].Gen_Instr_DFF |MB_FDR_127 | 2||488 | \Instruction_Prefetch_Mux[39].Instr_Mux_MUXF7 |MB_MUXF7_128 | 1||489 | \Instruction_Prefetch_Mux[3].Gen_Instr_DFF |MB_FDR_129 | 17||490 | \Instruction_Prefetch_Mux[3].Instr_Mux_MUXF7 |MB_MUXF7_130 | 1||491 | \Instruction_Prefetch_Mux[40].Gen_Instr_DFF |MB_FDR_131 | 4||492 | \Instruction_Prefetch_Mux[40].Instr_Mux_MUXF7 |MB_MUXF7_132 | 1||493 | \Instruction_Prefetch_Mux[41].Gen_Instr_DFF |MB_FDR_133 | 2||494 | \Instruction_Prefetch_Mux[41].Instr_Mux_MUXF7 |MB_MUXF7_134 | 1||495 | \Instruction_Prefetch_Mux[42].Gen_Instr_DFF |MB_FDR_135 | 2||496 | \Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7 |MB_MUXF7_136 | 1||497 | \Instruction_Prefetch_Mux[4].Gen_Instr_DFF |MB_FDR_137 | 4||498 | \Instruction_Prefetch_Mux[4].Instr_Mux_MUXF7 |MB_MUXF7_138 | 1||499 | \Instruction_Prefetch_Mux[5].Gen_Instr_DFF |MB_FDR_139 | 9||500 | \Instruction_Prefetch_Mux[5].Instr_Mux_MUXF7 |MB_MUXF7_140 | 1||501 | \Instruction_Prefetch_Mux[6].Gen_Instr_DFF |MB_FDR_141 | 6||502 | \Instruction_Prefetch_Mux[6].Instr_Mux_MUXF7 |MB_MUXF7_142 | 1||503 | \Instruction_Prefetch_Mux[7].Gen_Instr_DFF |MB_FDR_143 | 28||504 | \Instruction_Prefetch_Mux[7].Instr_Mux_MUXF7 |MB_MUXF7_144 | 1||505 | \Instruction_Prefetch_Mux[8].Gen_Instr_DFF |MB_FDR_145 | 46||506 | \Instruction_Prefetch_Mux[8].Instr_Mux_MUXF7 |MB_MUXF7_146 | 1||507 | \Instruction_Prefetch_Mux[9].Gen_Instr_DFF |MB_FDR_147 | 5||508 | \Instruction_Prefetch_Mux[9].Instr_Mux_MUXF7 |MB_MUXF7_148 | 1||509 | Last_Sel_DFF |MB_FDS | 44||510 | Mux_Select_Empty_LUT6 |MB_LUT6__parameterized4 | 1||511 | Mux_Select_OF_Valid_LUT6 |MB_LUT6__parameterized6 | 1||512 | OF_Valid_DFF |MB_FDR_149 | 4||513 | \Use_MuxCy[10].OF_Piperun_Stage |carry_and | 1||514 | MUXCY_I |MB_MUXCY_55 | 1||515 | \Use_MuxCy[11].OF_Piperun_Stage |carry_and_1 | 7||516 | MUXCY_I |MB_MUXCY_54 | 7||517 | \Use_MuxCy[1].OF_Piperun_Stage |carry_and_2 | 1||518 | MUXCY_I |MB_MUXCY_53 | 1||519 | \Use_MuxCy[2].OF_Piperun_Stage |carry_and_3 | 2||520 | MUXCY_I |MB_MUXCY_52 | 2||521 | \Use_MuxCy[3].OF_Piperun_Stage |carry_and_4 | 11||522 | MUXCY_I |MB_MUXCY_51 | 11||523 | \Use_MuxCy[4].OF_Piperun_Stage |carry_and_5 | 1||524 | MUXCY_I |MB_MUXCY_50 | 1||525 | \Use_MuxCy[5].OF_Piperun_Stage |carry_and_6 | 1||526 | MUXCY_I |MB_MUXCY_49 | 1||527 | \Use_MuxCy[6].OF_Piperun_Stage |carry_and_7 | 1||528 | MUXCY_I |MB_MUXCY_48 | 1||529 | \Use_MuxCy[7].OF_Piperun_Stage |carry_and_8 | 1||530 | MUXCY_I |MB_MUXCY_47 | 1||531 | \Use_MuxCy[8].OF_Piperun_Stage |carry_and_9 | 1||532 | MUXCY_I |MB_MUXCY_46 | 1||533 | \Use_MuxCy[9].OF_Piperun_Stage |carry_and_10 | 1||534 | MUXCY_I |MB_MUXCY_45 | 1||535 | \Using_FPGA.Gen_Bits[28].MEM_EX_Result_Inst |MB_FDRE | 3||536 | \Using_FPGA.Gen_Bits[29].MEM_EX_Result_Inst |MB_FDRE_11 | 3||537 | \Using_FPGA.Gen_Bits[30].MEM_EX_Result_Inst |MB_FDRE_12 | 2||538 | \Using_FPGA.Gen_Bits[31].MEM_EX_Result_Inst |MB_FDRE_13 | 3||539 | \Using_FPGA_2.ex_byte_access_i_Inst |MB_FDRE_14 | 1||540 | \Using_FPGA_2.ex_doublet_access_i_Inst |MB_FDRE_15 | 1||541 | \Using_FPGA_2.ex_is_load_instr_Inst |MB_FDRE_16 | 5||542 | \Using_FPGA_2.ex_is_lwx_instr_Inst |MB_FDRE_17 | 3||543 | \Using_FPGA_2.ex_is_swx_instr_Inst |MB_FDRE_18 | 3||544 | \Using_FPGA_2.ex_load_store_instr_Inst |MB_FDRE_19 | 7||545 | \Using_FPGA_3.ex_clear_MSR_BIP_instr_Inst |MB_FDRE_20 | 5||546 | \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst |MB_FDR | 3||547 | \Using_FPGA_4.of_read_ex_write_op1_conflict_INST1 |MB_LUT6__parameterized8 | 1||548 | \Using_FPGA_4.of_read_ex_write_op1_conflict_INST2 |MB_LUT6__parameterized10 | 2||549 | \Using_FPGA_4.of_read_ex_write_op2_conflict_INST1 |MB_LUT6__parameterized8_21 | 1||550 | \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2 |MB_LUT6__parameterized10_22 | 1||551 | \Using_FPGA_4.of_read_ex_write_op3_conflict_INST1 |MB_LUT6__parameterized8_23 | 1||552 | \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2 |MB_LUT6__parameterized10_24 | 2||553 | \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1 |MB_LUT6__parameterized8_25 | 1||554 | \Using_FPGA_4.of_read_mem_write_op1_conflict_INST2 |MB_LUT6__parameterized10_26 | 2||555 | \Using_FPGA_4.of_read_mem_write_op2_conflict_INST1 |MB_LUT6__parameterized8_27 | 1||556 | \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2 |MB_LUT6__parameterized10_28 | 1||557 | \Using_FPGA_4.of_read_mem_write_op3_conflict_INST1 |MB_LUT6__parameterized8_29 | 2||558 | \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2 |MB_LUT6__parameterized10_30 | 1||559 | if_pc_incr_carry_and_0 |carry_and_31 | 2||560 | MUXCY_I |MB_MUXCY_44 | 2||561 | if_pc_incr_carry_and_3 |carry_and_32 | 1||562 | MUXCY_I |MB_MUXCY_43 | 1||563 | jump_logic_I1 |jump_logic | 68||564 | MUXCY_JUMP_CARRY |MB_MUXCY_37 | 3||565 | MUXCY_JUMP_CARRY2 |MB_MUXCY_38 | 3||566 | MUXCY_JUMP_CARRY3 |MB_MUXCY_39 | 3||567 | MUXCY_JUMP_CARRY4 |MB_MUXCY_40 | 2||568 | MUXCY_JUMP_CARRY5 |MB_MUXCY_41 | 1||569 | MUXCY_JUMP_CARRY6 |MB_MUXCY_42 | 47||570 | mem_PipeRun_carry_and |carry_and_33 | 4||571 | MUXCY_I |MB_MUXCY_36 | 4||572 | mem_wait_on_ready_N_carry_or |carry_or_34 | 2||573 | MUXCY_I |MB_MUXCY_35 | 2||574 | \Use_DBUS.DAXI_Interface_I1 |DAXI_interface | 83||575 | \Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1 |MB_AND2B1L | 1||576 | mem_databus_ready_sel_carry_or |carry_or | 1||577 | MUXCY_I |MB_MUXCY | 1||578 | Reset_DFF |mb_sync_bit | 3||579 | \Using_Async_Wakeup_1.Wakeup_DFF |mb_sync_bit_0 | 3|+------+------------------------------------------------------------------------------+------------------------------+------+---------------------------------------------------------------------------------Finished Writing Synthesis Report : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873---------------------------------------------------------------------------------Synthesis finished with 0 errors, 0 critical warnings and 26899 warnings.Synthesis Optimization Runtime : Time (s): cpu = 00:01:33 ; elapsed = 00:02:01 . Memory (MB): peak = 2152.680 ; gain = 529.352 ; free physical = 963 ; free virtual = 92936Synthesis Optimization Complete : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.684 ; gain = 840.109 ; free physical = 966 ; free virtual = 92939INFO: [Project 1-571] Translating synthesized netlistINFO: [Netlist 29-17] Analyzing 533 Unisim elements for replacementINFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU secondsINFO: [Project 1-570] Preparing netlist for logic optimizationINFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).INFO: [Project 1-111] Unisim Transformation Summary:A total of 236 instances were transformed.(MUXCY,XORCY) => CARRY4: 34 instancesFDE => FDRE: 32 instancesFDR => FDRE: 88 instancesFDS => FDSE: 1 instancesLUT6_2 => LUT6_2 (LUT5, LUT6): 64 instancesMULT_AND => LUT2: 1 instancesRAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instancesINFO: [Common 17-83] Releasing license: Synthesis281 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.synth_design completed successfullysynth_design: Time (s): cpu = 00:02:00 ; elapsed = 00:02:50 . Memory (MB): peak = 2203.695 ; gain = 926.949 ; free physical = 1119 ; free virtual = 93094INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/microblaze_0.dcp' has been generated.