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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [bd4a7ee8a4ca1bdd.logs/] [runme.log] - Rev 2
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*** Running vivadowith args -log clk_gen.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_gen.tcl****** Vivado v2017.4 (64-bit)**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.source clk_gen.tcl -notraceCommand: synth_design -top clk_gen -part xc7k325tffg900-2 -mode out_of_contextStarting synth_designAttempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'INFO: Launching helper process for spawning children vivado processesINFO: Helper process launched with PID 3376---------------------------------------------------------------------------------Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1395.582 ; gain = 85.000 ; free physical = 669 ; free virtual = 93762---------------------------------------------------------------------------------INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]INFO: [Synth 8-638] synthesizing module 'clk_gen_clk_wiz' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]Parameter CAPACITANCE bound to: DONT_CARE - type: stringParameter DIFF_TERM bound to: FALSE - type: stringParameter DQS_BIAS bound to: FALSE - type: stringParameter IBUF_DELAY_VALUE bound to: 0 - type: stringParameter IBUF_LOW_PWR bound to: TRUE - type: stringParameter IFD_DELAY_VALUE bound to: AUTO - type: stringParameter IOSTANDARD bound to: DEFAULT - type: stringINFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]Parameter BANDWIDTH bound to: OPTIMIZED - type: stringParameter CLKFBOUT_MULT_F bound to: 5.000000 - type: floatParameter CLKFBOUT_PHASE bound to: 0.000000 - type: floatParameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: stringParameter CLKIN1_PERIOD bound to: 5.000000 - type: floatParameter CLKIN2_PERIOD bound to: 0.000000 - type: floatParameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: floatParameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT0_PHASE bound to: 0.000000 - type: floatParameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT1_DIVIDE bound to: 1 - type: integerParameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT1_PHASE bound to: 0.000000 - type: floatParameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT2_DIVIDE bound to: 1 - type: integerParameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT2_PHASE bound to: 0.000000 - type: floatParameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT3_DIVIDE bound to: 1 - type: integerParameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT3_PHASE bound to: 0.000000 - type: floatParameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT4_CASCADE bound to: FALSE - type: stringParameter CLKOUT4_DIVIDE bound to: 1 - type: integerParameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT4_PHASE bound to: 0.000000 - type: floatParameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT5_DIVIDE bound to: 1 - type: integerParameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT5_PHASE bound to: 0.000000 - type: floatParameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: stringParameter CLKOUT6_DIVIDE bound to: 1 - type: integerParameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: floatParameter CLKOUT6_PHASE bound to: 0.000000 - type: floatParameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: stringParameter COMPENSATION bound to: ZHOLD - type: stringParameter DIVCLK_DIVIDE bound to: 1 - type: integerParameter IS_CLKINSEL_INVERTED bound to: 1'b0Parameter IS_PSEN_INVERTED bound to: 1'b0Parameter IS_PSINCDEC_INVERTED bound to: 1'b0Parameter IS_PWRDWN_INVERTED bound to: 1'b0Parameter IS_RST_INVERTED bound to: 1'b0Parameter REF_JITTER1 bound to: 0.010000 - type: floatParameter REF_JITTER2 bound to: 0.010000 - type: floatParameter SS_EN bound to: FALSE - type: stringParameter SS_MODE bound to: CENTER_HIGH - type: stringParameter SS_MOD_PERIOD bound to: 10000 - type: integerParameter STARTUP_WAIT bound to: FALSE - type: stringINFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/cad/xilinx/Vivado2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]INFO: [Synth 8-256] done synthesizing module 'clk_gen_clk_wiz' (4#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]INFO: [Synth 8-256] done synthesizing module 'clk_gen' (5#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]---------------------------------------------------------------------------------Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1437.121 ; gain = 126.539 ; free physical = 669 ; free virtual = 93763---------------------------------------------------------------------------------Report Check Netlist:+------+------------------+-------+---------+-------+------------------+| |Item |Errors |Warnings |Status |Description |+------+------------------+-------+---------+-------+------------------+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |+------+------------------+-------+---------+-------+------------------+---------------------------------------------------------------------------------Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1437.121 ; gain = 126.539 ; free physical = 667 ; free virtual = 93762---------------------------------------------------------------------------------INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacementINFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU secondsINFO: [Device 21-403] Loading part xc7k325tffg900-2INFO: [Project 1-570] Preparing netlist for logic optimizationProcessing XDC ConstraintsInitializing timing engineParsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_gen_propImpl.xdc].Resolution: To avoid this warning, move constraints listed in [.Xil/clk_gen_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.INFO: [Timing 38-2] Deriving generated clocksParsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]Completed Processing XDC ConstraintsINFO: [Project 1-111] Unisim Transformation Summary:No Unisim elements were transformed.Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1774.355 ; gain = 0.996 ; free physical = 310 ; free virtual = 93077---------------------------------------------------------------------------------Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Loading Part and Timing Information---------------------------------------------------------------------------------Loading part: xc7k325tffg900-2---------------------------------------------------------------------------------Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Applying 'set_property' XDC Constraints---------------------------------------------------------------------------------Applied set_property DONT_TOUCH = true for inst. (constraint file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc, line 9).---------------------------------------------------------------------------------Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 334 ; free virtual = 93103------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 332 ; free virtual = 93102---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start RTL Component Statistics---------------------------------------------------------------------------------Detailed RTL Component Info :---------------------------------------------------------------------------------Finished RTL Component Statistics------------------------------------------------------------------------------------------------------------------------------------------------------------------Start RTL Hierarchical Component Statistics---------------------------------------------------------------------------------Hierarchical RTL Component report---------------------------------------------------------------------------------Finished RTL Hierarchical Component Statistics------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Part Resource Summary---------------------------------------------------------------------------------Part Resources:DSPs: 840 (col length:140)BRAMs: 890 (col length: RAMB18 140 RAMB36 70)---------------------------------------------------------------------------------Finished Part Resource Summary------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Cross Boundary and Area Optimization------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:53 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 333 ; free virtual = 93102---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Applying XDC Timing Constraints------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 572 ; free virtual = 93068------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Timing Optimization------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 572 ; free virtual = 93068---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Technology Mapping------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:01:05 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 578 ; free virtual = 93069---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Flattening Before IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Flattening Before IO Insertion------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Final Netlist Cleanup------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Final Netlist Cleanup------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062---------------------------------------------------------------------------------Report Check Netlist:+------+------------------+-------+---------+-------+------------------+| |Item |Errors |Warnings |Status |Description |+------+------------------+-------+---------+-------+------------------+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |+------+------------------+-------+---------+-------+------------------+---------------------------------------------------------------------------------Start Renaming Generated Instances------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062---------------------------------------------------------------------------------Report RTL Partitions:+-+--------------+------------+----------+| |RTL Partition |Replication |Instances |+-+--------------+------------+----------++-+--------------+------------+----------+---------------------------------------------------------------------------------Start Rebuilding User Hierarchy------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Renaming Generated Ports------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Handling Custom Attributes------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Renaming Generated Nets------------------------------------------------------------------------------------------------------------------------------------------------------------------Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062------------------------------------------------------------------------------------------------------------------------------------------------------------------Start Writing Synthesis Report---------------------------------------------------------------------------------Report BlackBoxes:+-+--------------+----------+| |BlackBox name |Instances |+-+--------------+----------++-+--------------+----------+Report Cell Usage:+------+-----------+------+| |Cell |Count |+------+-----------+------+|1 |BUFG | 2||2 |MMCME2_ADV | 1||3 |IBUFDS | 1|+------+-----------+------+Report Instance Areas:+------+---------+----------------+------+| |Instance |Module |Cells |+------+---------+----------------+------+|1 |top | | 4||2 | inst |clk_gen_clk_wiz | 4|+------+---------+----------------+------+---------------------------------------------------------------------------------Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 571 ; free virtual = 93062---------------------------------------------------------------------------------Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1774.355 ; gain = 126.539 ; free physical = 623 ; free virtual = 93114Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:01:06 . Memory (MB): peak = 1774.355 ; gain = 463.773 ; free physical = 627 ; free virtual = 93118INFO: [Project 1-571] Translating synthesized netlistINFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacementINFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU secondsINFO: [Project 1-570] Preparing netlist for logic optimizationINFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).INFO: [Project 1-111] Unisim Transformation Summary:No Unisim elements were transformed.INFO: [Common 17-83] Releasing license: Synthesis25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.synth_design completed successfullysynth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:01:07 . Memory (MB): peak = 1774.355 ; gain = 499.598 ; free physical = 603 ; free virtual = 93094INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.