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Subversion Repositories aes-128-ecb-encoder
[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module_sim/] [modelsim/] [compile.do] - Rev 2
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vlib modelsim_lib/workvlib modelsim_lib/msimvlib modelsim_lib/msim/xil_defaultlibvlib modelsim_lib/msim/xpmvlib modelsim_lib/msim/axi_lite_ipif_v3_0_4vlib modelsim_lib/msim/lib_pkg_v1_0_2vlib modelsim_lib/msim/lib_srl_fifo_v1_0_2vlib modelsim_lib/msim/lib_cdc_v1_0_2vlib modelsim_lib/msim/axi_uartlite_v2_0_19vmap xil_defaultlib modelsim_lib/msim/xil_defaultlibvmap xpm modelsim_lib/msim/xpmvmap axi_lite_ipif_v3_0_4 modelsim_lib/msim/axi_lite_ipif_v3_0_4vmap lib_pkg_v1_0_2 modelsim_lib/msim/lib_pkg_v1_0_2vmap lib_srl_fifo_v1_0_2 modelsim_lib/msim/lib_srl_fifo_v1_0_2vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2vmap axi_uartlite_v2_0_19 modelsim_lib/msim/axi_uartlite_v2_0_19vlog -work xil_defaultlib -64 -incr -sv -L xil_defaultlib "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" \"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \vcom -work xpm -64 -93 \"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \vcom -work axi_lite_ipif_v3_0_4 -64 -93 \"../../../ipstatic/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \vcom -work lib_pkg_v1_0_2 -64 -93 \"../../../ipstatic/hdl/lib_pkg_v1_0_rfs.vhd" \vcom -work lib_srl_fifo_v1_0_2 -64 -93 \"../../../ipstatic/hdl/lib_srl_fifo_v1_0_rfs.vhd" \vcom -work lib_cdc_v1_0_2 -64 -93 \"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \vcom -work axi_uartlite_v2_0_19 -64 -93 \"../../../ipstatic/hdl/axi_uartlite_v2_0_vh_rfs.vhd" \vcom -work xil_defaultlib -64 -93 \"../../../../aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/sim/axi_uartlite_module_sim.vhd" \vlog -work xil_defaultlib \"glbl.v"