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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module_sim/] [xsim/] [file_info.txt] - Rev 2
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axi_uartlite_module_sim.vhd,vhdl,xil_defaultlib,../../../../aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/sim/axi_uartlite_module_sim.vhd,glbl.v,Verilog,xil_defaultlib,glbl.v