URL
https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
Subversion Repositories aes-128-ecb-encoder
[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [clk_gen/] [riviera/] [compile.do] - Rev 2
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vlib workvlib rivieravlib riviera/xil_defaultlibvlib riviera/xpmvmap xil_defaultlib riviera/xil_defaultlibvmap xpm riviera/xpmvlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../ipstatic" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" \"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \vcom -work xpm -93 \"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../ipstatic" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" \"../../../../aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v" \"../../../../aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v" \vlog -work xil_defaultlib \"glbl.v"