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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [impl_1/] [aes128_ecb_fpga_wrap_clock_utilization_routed.rpt] - Rev 2
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.--------------------------------------------------------------------------------------------------| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017| Date : Thu Jul 30 13:56:20 2020| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS| Command : report_clock_utilization -file aes128_ecb_fpga_wrap_clock_utilization_routed.rpt| Design : aes128_ecb_fpga_wrap| Device : 7k325t-ffg900| Speed File : -2 PRODUCTION 1.12 2017-02-17--------------------------------------------------------------------------------------------------Clock Utilization ReportTable of Contents-----------------1. Clock Primitive Utilization2. Global Clock Resources3. Global Clock Source Details4. Clock Regions: Key Resource Utilization5. Clock Regions : Global Clock Summary6. Device Cell Placement Summary for Global Clock g07. Device Cell Placement Summary for Global Clock g18. Clock Region Cell Placement per Global Clock: Region X0Y19. Clock Region Cell Placement per Global Clock: Region X1Y110. Clock Region Cell Placement per Global Clock: Region X0Y411. Clock Region Cell Placement per Global Clock: Region X0Y51. Clock Primitive Utilization------------------------------+----------+------+-----------+-----+--------------+--------+| Type | Used | Available | LOC | Clock Region | Pblock |+----------+------+-----------+-----+--------------+--------+| BUFGCTRL | 2 | 32 | 0 | 0 | 0 || BUFH | 0 | 168 | 0 | 0 | 0 || BUFIO | 0 | 40 | 0 | 0 | 0 || BUFMR | 0 | 20 | 0 | 0 | 0 || BUFR | 0 | 40 | 0 | 0 | 0 || MMCM | 1 | 10 | 0 | 0 | 0 || PLL | 0 | 10 | 0 | 0 | 0 |+----------+------+-----------+-----+--------------+--------+2. Global Clock Resources-------------------------+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 982 | 0 | 10.000 | clk_out1_clk_gen | clkgen/inst/clkout1_buf/O | clkgen/inst/clk_out1 || g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 5.000 | clkfbout_clk_gen | clkgen/inst/clkf_buf/O | clkgen/inst/clkfbout_buf_clk_gen |+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)3. Global Clock Source Details------------------------------+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 10.000 | clk_out1_clk_gen | clkgen/inst/mmcm_adv_inst/CLKOUT0 | clkgen/inst/clk_out1_clk_gen || src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 5.000 | clkfbout_clk_gen | clkgen/inst/mmcm_adv_inst/CLKFBOUT | clkgen/inst/clkfbout_clk_gen |+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)4. Clock Regions: Key Resource Utilization------------------------------------------+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3700 | 0 | 1200 | 0 | 80 | 0 | 40 | 0 | 60 || X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2 | 4000 | 0 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3700 | 0 | 1200 | 0 | 80 | 0 | 40 | 0 | 60 || X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3400 | 0 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3700 | 0 | 1200 | 0 | 80 | 0 | 40 | 0 | 60 || X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3400 | 0 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 3150 | 0 | 1050 | 0 | 50 | 0 | 25 | 0 | 60 || X0Y4 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 614 | 4000 | 80 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3300 | 0 | 1100 | 0 | 60 | 0 | 30 | 0 | 60 || X0Y5 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 348 | 4000 | 43 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y5 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3300 | 0 | 1100 | 0 | 60 | 0 | 30 | 0 | 60 || X0Y6 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1150 | 0 | 60 | 0 | 30 | 0 | 60 || X1Y6 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3300 | 0 | 1100 | 0 | 60 | 0 | 30 | 0 | 60 |+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+* Global Clock column represents track count; while other columns represents cell counts5. Clock Regions : Global Clock Summary---------------------------------------All Modules+----+----+----+| | X0 | X1 |+----+----+----+| Y6 | 0 | 0 || Y5 | 1 | 0 || Y4 | 1 | 0 || Y3 | 0 | 0 || Y2 | 0 | 0 || Y1 | 1 | 1 || Y0 | 0 | 0 |+----+----+----+6. Device Cell Placement Summary for Global Clock g0----------------------------------------------------+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+| g0 | BUFG/O | n/a | clk_out1_clk_gen | 10.000 | {0.000 5.000} | 982 | 0 | 0 | 0 | clkgen/inst/clk_out1 |+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources** IO Loads column represents load cell count of IO types*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)**** GT Loads column represents load cell count of GT types+----+------+----+| | X0 | X1 |+----+------+----+| Y6 | 0 | 0 || Y5 | 348 | 0 || Y4 | 632 | 0 || Y3 | 0 | 0 || Y2 | 0 | 0 || Y1 | 2 | 0 || Y0 | 0 | 0 |+----+------+----+7. Device Cell Placement Summary for Global Clock g1----------------------------------------------------+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+| g1 | BUFG/O | n/a | clkfbout_clk_gen | 5.000 | {0.000 2.500} | 0 | 0 | 1 | 0 | clkgen/inst/clkfbout_buf_clk_gen |+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources** IO Loads column represents load cell count of IO types*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)**** GT Loads column represents load cell count of GT types+----+----+----+| | X0 | X1 |+----+----+----+| Y6 | 0 | 0 || Y5 | 0 | 0 || Y4 | 0 | 0 || Y3 | 0 | 0 || Y2 | 0 | 0 || Y1 | 0 | 1 || Y0 | 0 | 0 |+----+----+----+8. Clock Region Cell Placement per Global Clock: Region X0Y1------------------------------------------------------------+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+| g0 | n/a | BUFG/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clkgen/inst/clk_out1 |+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts9. Clock Region Cell Placement per Global Clock: Region X1Y1------------------------------------------------------------+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clkgen/inst/clkfbout_buf_clk_gen |+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts10. Clock Region Cell Placement per Global Clock: Region X0Y4-------------------------------------------------------------+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+| g0 | n/a | BUFG/O | None | 632 | 0 | 614 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | clkgen/inst/clk_out1 |+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts11. Clock Region Cell Placement per Global Clock: Region X0Y5-------------------------------------------------------------+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+| g0 | n/a | BUFG/O | None | 348 | 0 | 348 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clkgen/inst/clk_out1 |+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+* Clock Loads column represents the clock pin loads (pin count)** Non-Clock Loads column represents the non-clock pin loads (pin count)*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts# Location of BUFG Primitivesset_property LOC BUFGCTRL_X0Y1 [get_cells clkgen/inst/clkf_buf]set_property LOC BUFGCTRL_X0Y0 [get_cells clkgen/inst/clkout1_buf]# Location of IO Primitives which is load of clock spine# Location of clock portsset_property LOC IOB_X1Y75 [get_ports CLK_IN_N]set_property LOC IOB_X1Y76 [get_ports CLK_IN_P]# Clock net "clkgen/inst/clk_out1" driven by instance "clkgen/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"#startgroupcreate_pblock {CLKAG_clkgen/inst/clk_out1}add_cells_to_pblock [get_pblocks {CLKAG_clkgen/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkgen/inst/clk_out1"}]]]resize_pblock [get_pblocks {CLKAG_clkgen/inst/clk_out1}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}#endgroup