Subversion Repositories aes-128-ecb-encoder

Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date         : Thu Jul 30 13:56:11 2020
| Host         : orme22 running 64-bit Ubuntu 18.04.4 LTS
| Command      : report_methodology -file aes128_ecb_fpga_wrap_methodology_drc_routed.rpt -pb aes128_ecb_fpga_wrap_methodology_drc_routed.pb -rpx aes128_ecb_fpga_wrap_methodology_drc_routed.rpx
| Design       : aes128_ecb_fpga_wrap
| Device       : xc7k325tffg900-2
| Speed File   : -2
| Design State : Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 7
+-----------+----------+-------------------------------------------------------------+------------+
| Rule      | Severity | Description                                                 | Violations |
+-----------+----------+-------------------------------------------------------------+------------+
| TIMING-20 | Warning  | Non-clocked latch                                           | 4          |
| TIMING-30 | Warning  | Sub-optimal master source pin selection for generated clock | 1          |
| XDCH-2    | Warning  | Same min and max delay values on IO port                    | 2          |
+-----------+----------+-------------------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-20#1 Warning
Non-clocked latch  
The latch sys_mngr/axi_state_reg[0]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[0]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#2 Warning
Non-clocked latch  
The latch sys_mngr/axi_state_reg[10]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[10]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#3 Warning
Non-clocked latch  
The latch sys_mngr/axi_state_reg[1]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[1]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#4 Warning
Non-clocked latch  
The latch sys_mngr/axi_state_reg[2]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[2]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-30#1 Warning
Sub-optimal master source pin selection for generated clock  
The generated clock clk_gen has a sub-optimal master source pin selection, timing can be pessimistic
Related violations: <none>

XDCH-2#1 Warning
Same min and max delay values on IO port  
The same input delay of 1.000 ns has been defined on port 'uart_rx' relative to clock clk_gen for both max and min. Make sure this reflects the design intent.
set_input_delay -clock [get_clocks clk_gen] 1.000 [get_ports uart_rx]
/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc (Line: 13)
Related violations: <none>

XDCH-2#2 Warning
Same min and max delay values on IO port  
The same output delay of 1.000 ns has been defined on port 'uart_tx' relative to clock clk_gen for both max and min. Make sure this reflects the design intent.
set_output_delay -clock [get_clocks clk_gen] 1.000 [get_ports uart_tx]
/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc (Line: 14)
Related violations: <none>