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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [impl_1/] [aes128_ecb_fpga_wrap_power_routed.rpt] - Rev 2
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017| Date : Thu Jul 30 13:56:15 2020| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS| Command : report_power -file aes128_ecb_fpga_wrap_power_routed.rpt -pb aes128_ecb_fpga_wrap_power_summary_routed.pb -rpx aes128_ecb_fpga_wrap_power_routed.rpx| Design : aes128_ecb_fpga_wrap| Device : xc7k325tffg900-2| Design State : routed| Grade : commercial| Process : typical| Characterization : Production----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Power ReportTable of Contents-----------------1. Summary1.1 On-Chip Components1.2 Power Supply Summary1.3 Confidence Level2. Settings2.1 Environment2.2 Clock Constraints3. Detailed Reports3.1 By Hierarchy1. Summary----------+--------------------------+--------------+| Total On-Chip Power (W) | 0.319 || Design Power Budget (W) | Unspecified* || Power Budget Margin (W) | NA || Dynamic (W) | 0.158 || Device Static (W) | 0.161 || Effective TJA (C/W) | 1.8 || Max Ambient (C) | 84.4 || Junction Temperature (C) | 25.6 || Confidence Level | Medium || Setting File | --- || Simulation Activity File | --- || Design Nets Matched | NA |+--------------------------+--------------+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>1.1 On-Chip Components----------------------+-------------------------+-----------+----------+-----------+-----------------+| On-Chip | Power (W) | Used | Available | Utilization (%) |+-------------------------+-----------+----------+-----------+-----------------+| Clocks | 0.010 | 6 | --- | --- || Slice Logic | 0.018 | 5086 | --- | --- || LUT as Logic | 0.017 | 2820 | 203800 | 1.38 || F7/F8 Muxes | <0.001 | 907 | 203800 | 0.45 || Register | <0.001 | 968 | 407600 | 0.24 || CARRY4 | <0.001 | 8 | 50950 | 0.02 || LUT as Shift Register | <0.001 | 10 | 64000 | 0.02 || Others | 0.000 | 27 | --- | --- || Signals | 0.018 | 2485 | --- | --- || MMCM | 0.107 | 1 | 10 | 10.00 || I/O | 0.006 | 9 | 500 | 1.80 || Static Power | 0.161 | | | || Total | 0.319 | | | |+-------------------------+-----------+----------+-----------+-----------------+1.2 Power Supply Summary------------------------+-----------+-------------+-----------+-------------+------------+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |+-----------+-------------+-----------+-------------+------------+| Vccint | 1.000 | 0.116 | 0.047 | 0.069 || Vccaux | 1.800 | 0.089 | 0.061 | 0.028 || Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 || Vcco25 | 2.500 | 0.002 | 0.001 | 0.001 || Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 || Vcco15 | 1.500 | 0.001 | 0.000 | 0.001 || Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 || Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 || Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 || Vccbram | 1.000 | 0.001 | 0.000 | 0.001 || MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 || MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 || MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 || Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |+-----------+-------------+-----------+-------------+------------+1.3 Confidence Level--------------------+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+| User Input Data | Confidence | Details | Action |+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+| Design implementation state | High | Design is routed | || Clock nodes activity | High | User specified more than 95% of clocks | || I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view || Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views || Device models | High | Device models are Production | || | | | || Overall confidence level | Medium | | |+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+2. Settings-----------2.1 Environment---------------+-----------------------+--------------------------+| Ambient Temp (C) | 25.0 || ThetaJA (C/W) | 1.8 || Airflow (LFM) | 250 || Heat Sink | medium (Medium Profile) || ThetaSA (C/W) | 3.3 || Board Selection | medium (10"x10") || # of Board Layers | 12to15 (12 to 15 Layers) || Board Temperature (C) | 25.0 |+-----------------------+--------------------------+2.2 Clock Constraints---------------------+------------------+------------------------------+-----------------+| Clock | Domain | Constraint (ns) |+------------------+------------------------------+-----------------+| CLK_IN_P | CLK_IN_P | 5.0 || clk_out1_clk_gen | clkgen/inst/clk_out1 | 10.0 || clk_out1_clk_gen | clkgen/inst/clk_out1_clk_gen | 10.0 || clkfbout_clk_gen | clkgen/inst/clkfbout_clk_gen | 5.0 |+------------------+------------------------------+-----------------+3. Detailed Reports-------------------3.1 By Hierarchy----------------+---------------------------------------------------------------------------+-----------+| Name | Power (W) |+---------------------------------------------------------------------------+-----------+| aes128_ecb_fpga_wrap | 0.158 || clkgen | 0.113 || inst | 0.113 || enc | 0.036 || sys_mngr | 0.007 || uartlite | 0.001 || U0 | 0.001 || AXI_LITE_IPIF_I | <0.001 || I_SLAVE_ATTACHMENT | <0.001 || I_DECODER | <0.001 || MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | <0.001 || MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | <0.001 || UARTLITE_CORE_I | <0.001 || BAUD_RATE_I | <0.001 || UARTLITE_RX_I | <0.001 || DELAY_16_I | <0.001 || INPUT_DOUBLE_REGS3 | <0.001 || SRL_FIFO_I | <0.001 || I_SRL_FIFO_RBU_F | <0.001 || CNTR_INCR_DECR_ADDN_F_I | <0.001 || DYNSHREG_F_I | <0.001 || UARTLITE_TX_I | <0.001 || MID_START_BIT_SRL16_I | <0.001 || SRL_FIFO_I | <0.001 || I_SRL_FIFO_RBU_F | <0.001 || CNTR_INCR_DECR_ADDN_F_I | <0.001 || DYNSHREG_F_I | <0.001 |+---------------------------------------------------------------------------+-----------+