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https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
Subversion Repositories aes-128-ecb-encoder
[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [impl_1/] [gen_run.xml] - Rev 2
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<?xml version="1.0" encoding="UTF-8"?><GenRun Id="impl_1" LaunchPart="xc7k325tffg900-2" LaunchTime="1596106321"><File Type="PA-TCL" Name="aes128_ecb_fpga_wrap.tcl"/><File Type="PLACE-DCP" Name="aes128_ecb_fpga_wrap_placed.dcp"/><File Type="REPORTS-TCL" Name="aes128_ecb_fpga_wrap_reports.tcl"/><File Type="PWROPT-DCP" Name="aes128_ecb_fpga_wrap_pwropt.dcp"/><File Type="OPT-DCP" Name="aes128_ecb_fpga_wrap_opt.dcp"/><File Type="OPT-DRC" Name="aes128_ecb_fpga_wrap_drc_opted.rpt"/><File Type="OPT-HWDEF" Name="aes128_ecb_fpga_wrap.hwdef"/><File Type="RDI-RDI" Name="aes128_ecb_fpga_wrap.vdi"/><File Type="PLACE-IO" Name="aes128_ecb_fpga_wrap_io_placed.rpt"/><File Type="PLACE-UTIL" Name="aes128_ecb_fpga_wrap_utilization_placed.rpt"/><File Type="PLACE-UTIL-PB" Name="aes128_ecb_fpga_wrap_utilization_placed.pb"/><File Type="PLACE-CTRL" Name="aes128_ecb_fpga_wrap_control_sets_placed.rpt"/><File Type="PLACE-PRE-SIMILARITY" Name="aes128_ecb_fpga_wrap_incremental_reuse_pre_placed.rpt"/><File Type="POSTPLACE-PWROPT-DCP" Name="aes128_ecb_fpga_wrap_postplace_pwropt.dcp"/><File Type="PHYSOPT-DCP" Name="aes128_ecb_fpga_wrap_physopt.dcp"/><File Type="BG-BIT" Name="aes128_ecb_fpga_wrap.bit"/><File Type="ROUTE-STATUS-PB" Name="aes128_ecb_fpga_wrap_route_status.pb"/><File Type="BG-BIN" Name="aes128_ecb_fpga_wrap.bin"/><File Type="ROUTE-TIMINGSUMMARY" Name="aes128_ecb_fpga_wrap_timing_summary_routed.rpt"/><File Type="BITSTR-MSK" Name="aes128_ecb_fpga_wrap.msk"/><File Type="ROUTE-TIMING-PB" Name="aes128_ecb_fpga_wrap_timing_summary_routed.pb"/><File Type="BITSTR-RBT" Name="aes128_ecb_fpga_wrap.rbt"/><File Type="ROUTE-TIMING-RPX" Name="aes128_ecb_fpga_wrap_timing_summary_routed.rpx"/><File Type="BITSTR-NKY" Name="aes128_ecb_fpga_wrap.nky"/><File Type="BITSTR-BMM" Name="aes128_ecb_fpga_wrap_bd.bmm"/><File Type="ROUTE-CLK" Name="aes128_ecb_fpga_wrap_clock_utilization_routed.rpt"/><File Type="BG-DRC" Name="aes128_ecb_fpga_wrap.drc"/><File Type="ROUTE-ERROR-DCP" Name="aes128_ecb_fpga_wrap_routed_error.dcp"/><File Type="BITSTR-MMI" Name="aes128_ecb_fpga_wrap.mmi"/><File Type="WBT-USG" Name="usage_statistics_webtalk.html"/><File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="aes128_ecb_fpga_wrap_postroute_physopt_bb.dcp"/><File Type="BG-BGN" Name="aes128_ecb_fpga_wrap.bgn"/><File Type="ROUTE-BLACKBOX-DCP" Name="aes128_ecb_fpga_wrap_routed_bb.dcp"/><File Type="BITSTR-SYSDEF" Name="aes128_ecb_fpga_wrap.sysdef"/><File Type="BITSTR-LTX" Name="aes128_ecb_fpga_wrap.ltx"/><File Type="POSTROUTE-PHYSOPT-DCP" Name="aes128_ecb_fpga_wrap_postroute_physopt.dcp"/><File Type="ROUTE-STATUS" Name="aes128_ecb_fpga_wrap_route_status.rpt"/><File Type="ROUTE-PWR-RPX" Name="aes128_ecb_fpga_wrap_power_routed.rpx"/><File Type="ROUTE-PWR-SUM" Name="aes128_ecb_fpga_wrap_power_summary_routed.pb"/><File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="aes128_ecb_fpga_wrap_methodology_drc_routed.rpx"/><File Type="ROUTE-PWR" Name="aes128_ecb_fpga_wrap_power_routed.rpt"/><File Type="ROUTE-DRC-RPX" Name="aes128_ecb_fpga_wrap_drc_routed.rpx"/><File Type="ROUTE-METHODOLOGY-DRC-PB" Name="aes128_ecb_fpga_wrap_methodology_drc_routed.pb"/><File Type="ROUTE-DRC-PB" Name="aes128_ecb_fpga_wrap_drc_routed.pb"/><File Type="ROUTE-METHODOLOGY-DRC" Name="aes128_ecb_fpga_wrap_methodology_drc_routed.rpt"/><File Type="ROUTE-DRC" Name="aes128_ecb_fpga_wrap_drc_routed.rpt"/><File Type="ROUTE-DCP" Name="aes128_ecb_fpga_wrap_routed.dcp"/><FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"><Filter Type="Srcs"/><File Path="$PPRDIR/../../src/aes128_enc.sv"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/><Attr Name="UsedIn" Val="simulation"/></FileInfo></File><File Path="$PPRDIR/../../src/wrap/axi_interface.sv"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/><Attr Name="UsedIn" Val="simulation"/></FileInfo></File><File Path="$PPRDIR/../../src/wrap/system_manager.sv"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/><Attr Name="UsedIn" Val="simulation"/></FileInfo></File><File Path="$PPRDIR/../../src/wrap/aes128_ecb_fpga_wrap.sv"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/><Attr Name="UsedIn" Val="simulation"/></FileInfo></File><File Path="$PSRCDIR/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci"><FileInfo><Attr Name="AutoDisabled" Val="1"/><Attr Name="UsedIn" Val="simulation"/></FileInfo></File><Config><Option Name="DesignMode" Val="RTL"/><Option Name="TopModule" Val="aes128_ecb_fpga_wrap"/><Option Name="TopAutoSet" Val="TRUE"/></Config></FileSet><FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"><Filter Type="Constrs"/><File Path="$PSRCDIR/constrs_1/new/pinout.xdc"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/></FileInfo></File><File Path="$PSRCDIR/constrs_1/new/timings.xdc"><FileInfo><Attr Name="UsedIn" Val="synthesis"/><Attr Name="UsedIn" Val="implementation"/></FileInfo></File><Config><Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/timings.xdc"/><Option Name="ConstrsType" Val="XDC"/></Config></FileSet><Strategy Version="1" Minor="2"><StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/><Step Id="init_design"/><Step Id="opt_design"/><Step Id="power_opt_design"/><Step Id="place_design"/><Step Id="post_place_power_opt_design"/><Step Id="phys_opt_design"/><Step Id="route_design"/><Step Id="post_route_phys_opt_design"/><Step Id="write_bitstream"/></Strategy><BlockFileSet Type="BlockSrcs" Name="clk_gen"/><BlockFileSet Type="BlockSrcs" Name="axi_uartlite_module"/></GenRun>