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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [synth_1/] [aes128_ecb_fpga_wrap_utilization_synth.rpt] - Rev 2
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.-----------------------------------------------------------------------------------------------------------------------------------| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017| Date : Thu Jul 30 13:54:39 2020| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS| Command : report_utilization -file aes128_ecb_fpga_wrap_utilization_synth.rpt -pb aes128_ecb_fpga_wrap_utilization_synth.pb| Design : aes128_ecb_fpga_wrap| Device : 7k325tffg900-2| Design State : Synthesized-----------------------------------------------------------------------------------------------------------------------------------Utilization Design InformationTable of Contents-----------------1. Slice Logic1.1 Summary of Registers by Type2. Memory3. DSP4. IO and GT Specific5. Clocking6. Specific Feature7. Primitives8. Black Boxes9. Instantiated Netlists1. Slice Logic--------------+-------------------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+-------------------------+------+-------+-----------+-------+| Slice LUTs* | 2780 | 0 | 203800 | 1.36 || LUT as Logic | 2780 | 0 | 203800 | 1.36 || LUT as Memory | 0 | 0 | 64000 | 0.00 || Slice Registers | 876 | 0 | 407600 | 0.21 || Register as Flip Flop | 872 | 0 | 407600 | 0.21 || Register as Latch | 4 | 0 | 407600 | <0.01 || F7 Muxes | 637 | 0 | 101900 | 0.63 || F8 Muxes | 270 | 0 | 50950 | 0.53 |+-------------------------+------+-------+-----------+-------+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.1.1 Summary of Registers by Type--------------------------------+-------+--------------+-------------+--------------+| Total | Clock Enable | Synchronous | Asynchronous |+-------+--------------+-------------+--------------+| 0 | _ | - | - || 0 | _ | - | Set || 0 | _ | - | Reset || 0 | _ | Set | - || 0 | _ | Reset | - || 0 | Yes | - | - || 4 | Yes | - | Set || 872 | Yes | - | Reset || 0 | Yes | Set | - || 0 | Yes | Reset | - |+-------+--------------+-------------+--------------+2. Memory---------+----------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+----------------+------+-------+-----------+-------+| Block RAM Tile | 0 | 0 | 445 | 0.00 || RAMB36/FIFO* | 0 | 0 | 445 | 0.00 || RAMB18 | 0 | 0 | 890 | 0.00 |+----------------+------+-------+-----------+-------+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E13. DSP------+-----------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+-----------+------+-------+-----------+-------+| DSPs | 0 | 0 | 840 | 0.00 |+-----------+------+-------+-----------+-------+4. IO and GT Specific---------------------+-----------------------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+-----------------------------+------+-------+-----------+-------+| Bonded IOB | 7 | 0 | 500 | 1.40 || Bonded IPADs | 0 | 0 | 50 | 0.00 || Bonded OPADs | 0 | 0 | 32 | 0.00 || PHY_CONTROL | 0 | 0 | 10 | 0.00 || PHASER_REF | 0 | 0 | 10 | 0.00 || OUT_FIFO | 0 | 0 | 40 | 0.00 || IN_FIFO | 0 | 0 | 40 | 0.00 || IDELAYCTRL | 0 | 0 | 10 | 0.00 || IBUFDS | 0 | 0 | 480 | 0.00 || GTXE2_COMMON | 0 | 0 | 4 | 0.00 || GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 || PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 || PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 || IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 || ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 || IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 || ILOGIC | 0 | 0 | 500 | 0.00 || OLOGIC | 0 | 0 | 500 | 0.00 |+-----------------------------+------+-------+-----------+-------+5. Clocking-----------+------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+------------+------+-------+-----------+-------+| BUFGCTRL | 0 | 0 | 32 | 0.00 || BUFIO | 0 | 0 | 40 | 0.00 || MMCME2_ADV | 0 | 0 | 10 | 0.00 || PLLE2_ADV | 0 | 0 | 10 | 0.00 || BUFMRCE | 0 | 0 | 20 | 0.00 || BUFHCE | 0 | 0 | 168 | 0.00 || BUFR | 0 | 0 | 40 | 0.00 |+------------+------+-------+-----------+-------+6. Specific Feature-------------------+-------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+-------------+------+-------+-----------+-------+| BSCANE2 | 0 | 0 | 4 | 0.00 || CAPTUREE2 | 0 | 0 | 1 | 0.00 || DNA_PORT | 0 | 0 | 1 | 0.00 || EFUSE_USR | 0 | 0 | 1 | 0.00 || FRAME_ECCE2 | 0 | 0 | 1 | 0.00 || ICAPE2 | 0 | 0 | 2 | 0.00 || PCIE_2_1 | 0 | 0 | 1 | 0.00 || STARTUPE2 | 0 | 0 | 1 | 0.00 || XADC | 0 | 0 | 1 | 0.00 |+-------------+------+-------+-----------+-------+7. Primitives-------------+----------+------+---------------------+| Ref Name | Used | Functional Category |+----------+------+---------------------+| LUT6 | 1930 | LUT || FDCE | 868 | Flop & Latch || MUXF7 | 637 | MuxFx || LUT2 | 435 | LUT || LUT3 | 306 | LUT || MUXF8 | 270 | MuxFx || LUT5 | 220 | LUT || LUT4 | 154 | LUT || CARRY4 | 8 | CarryLogic || OBUF | 5 | IO || LDCE | 4 | Flop & Latch || FDPE | 4 | Flop & Latch || LUT1 | 3 | LUT || IBUF | 2 | IO |+----------+------+---------------------+8. Black Boxes--------------+---------------------+------+| Ref Name | Used |+---------------------+------+| clk_gen | 1 || axi_uartlite_module | 1 |+---------------------+------+9. Instantiated Netlists------------------------+----------+------+| Ref Name | Used |+----------+------+