Subversion Repositories aes-128-ecb-encoder

2017.4:
 * Version 2.0 (Rev. 19)
 * Revision change in one or more subcores

2017.3:
 * Version 2.0 (Rev. 18)
 * General: Updated example design subcore version. No Functional changes
 * Revision change in one or more subcores

2017.2:
 * Version 2.0 (Rev. 17)
 * Revision change in one or more subcores

2017.1:
 * Version 2.0 (Rev. 16)
 * General: Updated example design subcore version. No Functional changes
 * Revision change in one or more subcores

2016.4:
 * Version 2.0 (Rev. 15)
 * Revision change in one or more subcores

2016.3:
 * Version 2.0 (Rev. 14)
 * Bug Fix: GUI related updates. GUI allows setting of only valid baud rate values.
 * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
 * Revision change in one or more subcores

2016.2:
 * Version 2.0 (Rev. 13)
 * Revision change in one or more subcores

2016.1:
 * Version 2.0 (Rev. 12)
 * Updated example design subcore version.No functional changes
 * Revision change in one or more subcores

2015.4.2:
 * Version 2.0 (Rev. 11)
 * No changes

2015.4.1:
 * Version 2.0 (Rev. 11)
 * No changes

2015.4:
 * Version 2.0 (Rev. 11)
 * Revision change in one or more subcores

2015.3:
 * Version 2.0 (Rev. 10)
 * Minor updates to example design. No functional changes.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Revision change in one or more subcores

2015.2.1:
 * Version 2.0 (Rev. 9)
 * No changes

2015.2:
 * Version 2.0 (Rev. 9)
 * Minor updates to example design. No functional changes.

2015.1:
 * Version 2.0 (Rev. 8)
 * Supported devices and production status are now determined automatically, to simplify support for future devices
 * Enhanced support for IP Integrator

2014.4.1:
 * Version 2.0 (Rev. 7)
 * No changes

2014.4:
 * Version 2.0 (Rev. 7)
 * Minor updates to example design. No functional changes.

2014.3:
 * Version 2.0 (Rev. 6)
 * axi uartlite is modified to use new sub-cores in place of proc_common. No functional changes.
 * Updating core to use utils.tcl needed for board flow from common location

2014.2:
 * Version 2.0 (Rev. 5)
 * Example design XDC updated
 * Minor GUI related updates, no functional changes

2014.1:
 * Version 2.0 (Rev. 4)
 * Internal device family name change, no functional changes
 * Virtex UltraScale Pre-Production support.

2013.4:
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 2.0 (Rev. 2)
 * Added example design and demonstration testbench
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

2013.2:
 * Version 2.0 (Rev. 1)
 * Enable support for future devices

2013.1:
 * Version 2.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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