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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [clk_gen/] [clk_gen.xdc] - Rev 2

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# file: clk_gen.xdc
# 
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# 
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# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system. If required
# commented constraints can be used in the top level xdc 
#----------------------------------------------------------------
# Differential clock only needs one constraint
create_clock -period 5.000 [get_ports clk_in1_p]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05


set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]

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