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https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk
Subversion Repositories aes-128-ecb-encoder
[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [clk_gen/] [clk_gen_sim_netlist.v] - Rev 2
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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 // Date : Thu Jul 23 09:43:35 2020 // Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago) // Command : write_verilog -force -mode funcsim -rename_top clk_gen -prefix // clk_gen_ clk_gen_sim_netlist.v // Design : clk_gen // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* NotValidForBitStream *) module clk_gen (clk_out1, reset, locked, clk_in1_p, clk_in1_n); output clk_out1; input reset; output locked; input clk_in1_p; input clk_in1_n; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n; (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p; wire clk_out1; wire locked; wire reset; clk_gen_clk_gen_clk_wiz inst (.clk_in1_n(clk_in1_n), .clk_in1_p(clk_in1_p), .clk_out1(clk_out1), .locked(locked), .reset(reset)); endmodule module clk_gen_clk_gen_clk_wiz (clk_out1, reset, locked, clk_in1_p, clk_in1_n); output clk_out1; input reset; output locked; input clk_in1_p; input clk_in1_n; wire clk_in1_clk_gen; wire clk_in1_n; wire clk_in1_p; wire clk_out1; wire clk_out1_clk_gen; wire clkfbout_buf_clk_gen; wire clkfbout_clk_gen; wire locked; wire reset; wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_clk_gen), .O(clkfbout_buf_clk_gen)); (* BOX_TYPE = "PRIMITIVE" *) (* CAPACITANCE = "DONT_CARE" *) (* IBUF_DELAY_VALUE = "0" *) (* IFD_DELAY_VALUE = "AUTO" *) IBUFDS #( .IOSTANDARD("DEFAULT")) clkin1_ibufgds (.I(clk_in1_p), .IB(clk_in1_n), .O(clk_in1_clk_gen)); (* BOX_TYPE = "PRIMITIVE" *) BUFG clkout1_buf (.I(clk_out1_clk_gen), .O(clk_out1)); (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT_F(5.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE_F(10.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT3_USE_FINE_PS("FALSE"), .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .CLKOUT5_USE_FINE_PS("FALSE"), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.500000), .CLKOUT6_PHASE(0.000000), .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("ZHOLD"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PSEN_INVERTED(1'b0), .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .SS_EN("FALSE"), .SS_MODE("CENTER_HIGH"), .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) mmcm_adv_inst (.CLKFBIN(clkfbout_buf_clk_gen), .CLKFBOUT(clkfbout_clk_gen), .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), .CLKIN1(clk_in1_clk_gen), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), .CLKOUT0(clk_out1_clk_gen), .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(locked), .PSCLK(1'b0), .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), .PSEN(1'b0), .PSINCDEC(1'b0), .PWRDWN(1'b0), .RST(reset)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif